Our zero defects methodology is made up of a balanced set of quality processes

At NXP, we practice a zero defects methodology. We aim for the highest level of excellence—giving you the quality you require. Our products get the highest attention to detail in every phase of production: design, wafer fabrication, assembly and test.

Manufacturing Continuous Improvement

Part Average Testing and Statistical Bin Limits

Statistical methods are applied at unit probe and final test. Part Average Testing (PAT) is a die-level screen that gives the typical limits of a historical distribution for some of the electrical measures contributing to unit probe and/or final test. Any die that registers an electrical measure outside of a PAT limit is inked out and defined as an outlier.

Statistical Bin Limits (SBL) is a wafer-level screen that uses a statistical method to determine the typical fallout level of each bin at unit probe.

Detecting Outliers

Along with PAT and SBL, there are other screening methods applied at unit probe. The Good Die in Bad Cluster (GDBC) methodology identifies a working/passing die that may be surrounded by failing die. These good die are then removed as a precaution.

Wafer fabrication and die final manufacturing Statistical Process Control (SPC) limits identify processes that are out of control so they can be adjusted as necessary.

Specification limits are used as the gauge to determine if the product has been manufactured as per the design. An advanced method establishes inline process limits at median +/- 6 Sigma to identify “typical” product. Capability (CpK) studies are regularly done on various inline processes and class probe (electrical) parameters.

Product Improvement

Design for Manufacturing

The Design for Manufacturing (DFM) methodology aims to:

  • Optimize process operating windows in our manufacturing processes
  • Prevent faults from materializing

The DFM methodology ensures the best quality, reliability, cost, time to market and customer satisfaction.

Application/Test Correlation

This is a systematic effort to identify, classify and remove issues due to application or product test differences. The correlation effort is an iterative process. It involves working with you, our customers, to share application schematics and methods so we can implement tests that mirror your application.