///////////////////////////////////////////////////////////////////////////////
//                                                                            /
// IAR ANSI C/C++ Compiler V6.30.1.53127/W32 for ARM    08/Mar/2012  18:18:26 /
// Copyright 1999-2011 IAR Systems AB.                                        /
//                                                                            /
//    Cpu mode     =  thumb                                                   /
//    Endian       =  little                                                  /
//    Source file  =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\src\projects\TWRK20D50M_Demo\adc_test\adc_test.c     /
//    Command line =  "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\src\projects\TWRK20D50M_Demo\adc_test\adc_test.c"   /
//                    -D IAR -D TOWER -D TWR_K20D50M -lCN                     /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" /
//                     -lB "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" -o          /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\Obj\"  /
//                    --no_cse --no_unroll --no_inline --no_code_motion       /
//                    --no_tbaa --no_clustering --no_scheduling --debug       /
//                    --endian=little --cpu=Cortex-M4 -e --fpu=None           /
//                    --dlib_config "C:\Program Files\IAR Systems\Embedded    /
//                    Workbench 6.0_5\arm\INC\c\DLib_Config_Normal.h" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\common\" -I  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\" -I     /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\headers\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\uart\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\mcg\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\wdog\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\rcm\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\lptmr\" -I       /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\platforms\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\" -I                /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\projects\TWR /
//                    K20D50M_Demo\" -I "D:\Profiles\b01252\My                /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \dma\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc16\" -I "D:\Profiles\b01252\My                      /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \i2c\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \tsi\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \angle_calculation\" -I "D:\Profiles\b01252\My          /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \buzzer\" -I "D:\Profiles\b01252\My                     /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \fft_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \irda_test\" -I "D:\Profiles\b01252\My                  /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \cmt_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \protocol\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \task_mgr\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \TWRK20_specific\" -I "D:\Profiles\b01252\My            /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \rtc\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Lib\interm /
//                    ediateFiles\" -I "D:\Profiles\b01252\My                 /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Include\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \DeviceSupport\ARM\ARMCM4\" -I "D:\Profiles\b01252\My   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4\CoreSupport\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \CoreSupportLiker Options-Library\" -I                  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Li /
//                    b\Lib\intermediateFiles\arm_cortexM4_math.lib\" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\build\" -Ol      /
//                    --use_c++_inline -I "C:\Program Files\IAR               /
//                    Systems\Embedded Workbench 6.0_5\arm\CMSIS\Include\"    /
//                    -D ARM_MATH_CM4                                         /
//    List file    =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\ad /
//                    c_test.s                                                /
//                                                                            /
//                                                                            /
///////////////////////////////////////////////////////////////////////////////

        NAME adc_test

        #define SHT_PROGBITS 0x1

        EXTERN ADC_Cal
        EXTERN ADC_Config_Alt
        EXTERN ADC_Read_Cal
        EXTERN enable_irq
        EXTERN printf
        EXTERN real128_fft
        EXTERN ti_test_adc

        PUBLIC CalibrationStore
        PUBLIC DMA_errorCount
        PUBLIC Master_Adc_Config
        PUBLIC adc0_isr
        PUBLIC adc_buffer
        PUBLIC adc_init
        PUBLIC adc_read
        PUBLIC adc_reading_channel
        PUBLIC adc_sample0
        PUBLIC adc_sample1
        PUBLIC adc_start_conversion
        PUBLIC adc_test_init
        PUBLIC bSamplesReady
        PUBLIC bSeqErr
        PUBLIC buffer
        PUBLIC channel_no
        PUBLIC dmaIsrCount
        PUBLIC dma_error
        PUBLIC foobar
        PUBLIC intnum
        PUBLIC isr_flag
        PUBLIC last_adc_channel
        PUBLIC pdb_init
        PUBLIC pdb_isr
        PUBLIC pdb_seq_err_handle
        PUBLIC pdb_seq_error
        PUBLIC tcd
        PUBLIC tcd1
        PUBLIC tcd2
        PUBLIC vfnDMAADCCh_Init
        PUBLIC vfnDMACh14ISR
        PUBLIC vfnDMA_Config
        PUBLIC vfnDMA_ErrorIsr
        PUBLIC vfnDMAtoRAM
        PUBLIC wSamplesCounter

// D:\Profiles\b01252\My Documents\Freescale\P0\software\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\src\projects\TWRK20D50M_Demo\adc_test\adc_test.c
//    1 /****************************************************************************************************/
//    2 /**
//    3 Copyright (c) 2008 Freescale Semiconductor
//    4 Freescale Confidential Proprietary
//    5 \file       adc_test.c
//    6 \brief      configure the adc for single end mode, and software trigger. PDB enabled for ADC triggering
//    7 \author     FSL
//    8 \version    1.0
//    9 \date       Sep 29 2011
//   10 */
//   11 
//   12 
//   13 #include "common.h"
//   14 #include "edma_common.h"
//   15 #include "adc16.h"
//   16 #include "TWR_K20D50M_DEF.h"
//   17 #include "buzzer.h"   //include timers definitions
//   18 #include "adc_test.h"
//   19 #define MAX_SAMPLES   128u
//   20 
//   21 #define ADC_MIC_CHANNEL 3   //ADC0_DP3  single
//   22 #define ADC_POT_CHANNEL 21  //ADC0_DM3  single
//   23 
//   24 
//   25 #define BITS32    2
//   26 #define BITS16    1
//   27 #define BITS8     0
//   28 
//   29 
//   30 void vfnDMAADCCh_Init(void);
//   31 void vfnDMAtoRAM(uint32 *destiny_address);
//   32 
//   33 
//   34 /******************************************************************************* 
//   35 *  Global variables
//   36 *******************************************************************************/

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   37 dma_tcd tcd;
tcd:
        DS8 48

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   38 int intnum, channel_no;
intnum:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
channel_no:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   39 dma_tcd tcd1,tcd2;
tcd1:
        DS8 48

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
tcd2:
        DS8 48

        SECTION `.bss`:DATA:REORDER:NOROOT(0)
//   40 char buffer;   //If buffer = 0x80 flag of data ready  bit0 for buffer selection
buffer:
        DS8 1

        SECTION `.bss`:DATA:REORDER:NOROOT(0)
//   41 char adc_reading_channel;
adc_reading_channel:
        DS8 1

        SECTION `.bss`:DATA:REORDER:NOROOT(0)
//   42 char last_adc_channel;
last_adc_channel:
        DS8 1
//   43 
//   44 

        SECTION `.bss`:DATA:REORDER:NOROOT(0)
//   45 unsigned char foobar=0x00;    // ".data" variable example
foobar:
        DS8 1

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   46 int isr_flag, dma_error = 0;
isr_flag:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
dma_error:
        DS8 4
//   47 
//   48 
//   49 //globle variables

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   50 tADC_Config Master_Adc_Config;  
Master_Adc_Config:
        DS8 16

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   51 tADC_Cal_Blk CalibrationStore[2];
CalibrationStore:
        DS8 52

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
//   52 uint16 adc_sample0;
adc_sample0:
        DS8 2

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
//   53 uint16 adc_sample1;  
adc_sample1:
        DS8 2

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
//   54 uint16 DMA_errorCount;
DMA_errorCount:
        DS8 2

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
//   55 uint16 dmaIsrCount;
dmaIsrCount:
        DS8 2
//   56 

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   57 uint32 adc_buffer[256];
adc_buffer:
        DS8 1024
//   58 
//   59 //volatile uint16  wSamplesBuf[MAX_SAMPLES];
//   60 //volatile uint16  wSamplesBufOffline[MAX_SAMPLES];
//   61 

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
//   62 volatile uint16  wSamplesCounter;
wSamplesCounter:
        DS8 2

        SECTION `.bss`:DATA:REORDER:NOROOT(0)
//   63 volatile uint8   bSamplesReady;
bSamplesReady:
        DS8 1

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   64 volatile uint32  bSeqErr;
bSeqErr:
        DS8 4
//   65 
//   66 // Prototypes
//   67 void adc_init(void);
//   68 void pdb_init(void);   
//   69 void pdb_seq_error(uint16 channel,uint16 pretrigger);
//   70 void process_samples_offline(void);
//   71 void handle_pdb_seq_err(void);
//   72 void deinit_pdb_adc(void);
//   73 
//   74 
//   75 /**   adc_test_init
//   76  * \brief    initialize ADC and prepare for test
//   77  * \author   FSL
//   78  * \param    none
//   79  * \return   none
//   80  * \warning   ASSUME: IPBus clock is 48MHz
//   81  */  

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//   82 void adc_test_init(void)
//   83 {
adc_test_init:
        PUSH     {R7,LR}
//   84 
//   85     printf("Welcome to PDB trigger ADC demo!\r\n");
        LDR.W    R0,??DataTable13
        BL       printf
//   86     printf("Please make sure signal on ADC1 channel1 is ready, press any key to continue...!");
        LDR.W    R0,??DataTable13_1
        BL       printf
//   87     printf("\r\n");
        ADR.N    R0,??DataTable6  ;; 0x0D, 0x0A, 0x00, 0x00
        BL       printf
//   88     
//   89     // Initialize global variables
//   90     wSamplesCounter = 0;
        LDR.W    R0,??DataTable13_2
        MOVS     R1,#+0
        STRH     R1,[R0, #+0]
//   91     bSamplesReady = 0;
        LDR.W    R0,??DataTable13_3
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//   92     bSeqErr = 0;
        LDR.W    R0,??DataTable13_4
        MOVS     R1,#+0
        STR      R1,[R0, #+0]
//   93     adc_init();
        BL       adc_init
//   94     vfnDMAADCCh_Init();
        BL       vfnDMAADCCh_Init
//   95     vfnDMAtoRAM(adc_buffer);
        LDR.W    R0,??DataTable13_5
        BL       vfnDMAtoRAM
//   96     
//   97     pdb_init();
        BL       pdb_init
//   98  }
        POP      {R0,PC}          ;; return
//   99 
//  100 
//  101 /**   adc_init
//  102  * \brief    initialize and calibrate ADC0 module
//  103  * \brief    48MHz IPBus clock; ADC clock = 48M/2/8 = 3MHz
//  104  * \brief    Total conversion time: 56N+4ADCK
//  105  * \brief    given sampling rate Fs = 6.4K, 156us/sample,  156*3= 468 ADCK
//  106  * \author   FSL
//  107  * \param    none
//  108  * \return   none
//  109  * \warning  assumes 48MHz IPBus clock
//  110  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  111 void adc_init(void)
//  112 {
adc_init:
        PUSH     {R7,LR}
//  113   
//  114    uint8_t cal_ok;
//  115  
//  116   SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
        LDR.W    R0,??DataTable13_6  ;; 0x4004803c
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x8000000
        LDR.W    R1,??DataTable13_6  ;; 0x4004803c
        STR      R0,[R1, #+0]
//  117   enable_irq(INT_ADC0 - 16);
        MOVS     R0,#+22
        BL       enable_irq
//  118      
//  119   /* 48MHz IPBus clock
//  120    * ADC clock = 48M/2/8 = 3MHz
//  121    * Total conversion time: 56N+4ADCK
//  122    * Given sampling rate Fs = 6.4K, 156us/sample,  156*3= 468 ADCK
//  123    * the maximum h/w average number = 8
//  124    * use h/w average number = 4
//  125    * Total conversion time: 56*4+4 = 228 ADC clocks,76us
//  126    * There are 468-228 = 240 ADC clocks (ie. 80us) free for post processing
//  127    */
//  128  
//  129 
//  130  // Initialize ADC0
//  131   // Do calibration first with 32 h/w averages
//  132   Master_Adc_Config.CONFIG1  = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_16)
//  133                               | ADC_CFG1_ADICLK(ADICLK_BUS_2);  
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+125
        STRB     R1,[R0, #+0]
//  134   Master_Adc_Config.CONFIG2  = MUXSEL_ADCA | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ;
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+12
        STRB     R1,[R0, #+1]
//  135   Master_Adc_Config.COMPARE1 = 0x1234u ; 
        LDR.W    R0,??DataTable13_7
        MOVW     R1,#+4660
        STRH     R1,[R0, #+2]
//  136   Master_Adc_Config.COMPARE2 = 0x5678u ;
        LDR.W    R0,??DataTable13_7
        MOVW     R1,#+22136
        STRH     R1,[R0, #+4]
//  137   Master_Adc_Config.STATUS2  = ADTRG_SW | ACFE_DISABLED | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT);
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+24
        STRB     R1,[R0, #+6]
//  138   Master_Adc_Config.STATUS3  = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_32);
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+7
        STRB     R1,[R0, #+7]
//  139  // Master_Adc_Config.PGA      = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64);
//  140   Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);       
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+31
        STRB     R1,[R0, #+8]
//  141   Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);  
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+31
        STRB     R1,[R0, #+9]
//  142   
//  143   ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config ADC
        LDR.W    R1,??DataTable13_7
        LDR.W    R0,??DataTable13_8  ;; 0x4003b000
        BL       ADC_Config_Alt
//  144   cal_ok = ADC_Cal(ADC0_BASE_PTR);                    // do the calibration
        LDR.W    R0,??DataTable13_8  ;; 0x4003b000
        BL       ADC_Cal
//  145   if (cal_ok != 0) printf("ADC calibration error");
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        CMP      R0,#+0
        BEQ.N    ??adc_init_0
        LDR.W    R0,??DataTable13_9
        BL       printf
//  146   ADC_Read_Cal(ADC0_BASE_PTR,&CalibrationStore[1]);   // store the cal
??adc_init_0:
        LDR.W    R1,??DataTable13_10
        LDR.W    R0,??DataTable13_8  ;; 0x4003b000
        BL       ADC_Read_Cal
//  147   
//  148   // Now do normal ADC configuration with 4 h/w averages and h/w trigger from PDB
//  149   Master_Adc_Config.CONFIG1  = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_12)
//  150                               | ADC_CFG1_ADICLK(ADICLK_BUS_2);  
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+117
        STRB     R1,[R0, #+0]
//  151   Master_Adc_Config.CONFIG2  = MUXSEL_ADCA | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ;
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+12
        STRB     R1,[R0, #+1]
//  152   Master_Adc_Config.COMPARE1 = 0x1234u ; 
        LDR.W    R0,??DataTable13_7
        MOVW     R1,#+4660
        STRH     R1,[R0, #+2]
//  153   Master_Adc_Config.COMPARE2 = 0x5678u ;
        LDR.W    R0,??DataTable13_7
        MOVW     R1,#+22136
        STRH     R1,[R0, #+4]
//  154   Master_Adc_Config.STATUS2  = ADTRG_HW | ACFE_DISABLED | ACFGT_GREATER | ACREN_DISABLED | DMAEN_ENABLED | ADC_SC2_REFSEL(REFSEL_EXT);
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+84
        STRB     R1,[R0, #+6]
//  155   Master_Adc_Config.STATUS3  = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_4);
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+4
        STRB     R1,[R0, #+7]
//  156 //  Master_Adc_Config.PGA      = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64);
//  157 
//  158   Master_Adc_Config.STATUS1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC_MIC_CHANNEL);                                                               
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+3
        STRB     R1,[R0, #+8]
//  159   Master_Adc_Config.STATUS1B = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC_POT_CHANNEL);    
        LDR.W    R0,??DataTable13_7
        MOVS     R1,#+21
        STRB     R1,[R0, #+9]
//  160 
//  161   ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config the ADC again to default conditions    
        LDR.W    R1,??DataTable13_7
        LDR.W    R0,??DataTable13_8  ;; 0x4003b000
        BL       ADC_Config_Alt
//  162 
//  163    adc_reading_channel = ADC_MIC_CHANNEL;
        LDR.W    R0,??DataTable13_11
        MOVS     R1,#+3
        STRB     R1,[R0, #+0]
//  164    last_adc_channel =adc_reading_channel;
        LDR.W    R0,??DataTable13_12
        LDR.W    R1,??DataTable13_11
        LDRB     R1,[R1, #+0]
        STRB     R1,[R0, #+0]
//  165    
//  166 
//  167 
//  168   
//  169 }
        POP      {R0,PC}          ;; return
//  170 
//  171 
//  172 
//  173 /**   adc_start_conversion, result is stored in the ADC interrupt on a global variable
//  174  * \brief    start adc conversion of channel n
//  175  * \author   FSL
//  176  * \param    channel
//  177  * \return   none
//  178  * \warning  assumes 48MHz IPBus clock
//  179  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  180 void adc_start_conversion(uint8 channel)
//  181 {
//  182     ADC0_SC1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(channel);     
adc_start_conversion:
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        ANDS     R0,R0,#0x1F
        LDR.W    R1,??DataTable13_8  ;; 0x4003b000
        STR      R0,[R1, #+0]
//  183    
//  184    
//  185 }
        BX       LR               ;; return
//  186 
//  187 
//  188 /*
//  189   Esto es un prueba para ver si se puede hacer una conversion entre PDB sampleos
//  190 */
//  191 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  192 void adc_read(uint8 channel)
//  193 {
//  194    //uint16 temp_adc_ch;
//  195    
//  196   // temp_adc_ch = ADC_SC1_ADCH(channel);
//  197   
//  198   
//  199   
//  200    if (ti_test_adc==0) adc_reading_channel = ADC_MIC_CHANNEL;
adc_read:
        LDR.W    R0,??DataTable13_13
        LDRH     R0,[R0, #+0]
        CMP      R0,#+0
        BNE.N    ??adc_read_0
        LDR.W    R0,??DataTable13_11
        MOVS     R1,#+3
        STRB     R1,[R0, #+0]
        B.N      ??adc_read_1
//  201    else adc_reading_channel = ADC_POT_CHANNEL;
??adc_read_0:
        LDR.W    R0,??DataTable13_11
        MOVS     R1,#+21
        STRB     R1,[R0, #+0]
//  202    
//  203   /* 
//  204    ADC0_SC1A = ADC_SC1_ADCH(31); //disable adc
//  205    ADC0_SC2   &= ~ADC_SC2_ADTRG_MASK; // Select Software trigger
//  206    ADC0_SC1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(channel);     // start conversion
//  207    while((ADC0_SC1A & ADC_SC1_COCO_MASK)!= 0){};
//  208    adc_sample1 = ADC0_RA;
//  209 */
//  210    
//  211   // returns control to  HW trigger (PDB, DMA)  and select Microphone channel
//  212    ADC0_SC2   |= ADC_SC2_ADTRG_MASK; // Hardware trigger Software trigger
??adc_read_1:
        LDR.W    R0,??DataTable13_14  ;; 0x4003b020
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x40
        LDR.W    R1,??DataTable13_14  ;; 0x4003b020
        STR      R0,[R1, #+0]
//  213    ADC0_SC1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(adc_reading_channel);  // reads MIC or POT signal
        LDR.W    R0,??DataTable13_11
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0x1F
        LDR.W    R1,??DataTable13_8  ;; 0x4003b000
        STR      R0,[R1, #+0]
//  214   
//  215 }
        BX       LR               ;; return
//  216 
//  217  
//  218 
//  219 
//  220 
//  221 /**   adc0_isr,
//  222  * \brief    reads the results of the Adc conversion
//  223  * \brief    values is stored in a global variable  adc_sample0, adc_sample1
//  224  * \author   FSL
//  225  * \param    none
//  226  * \return   none
//  227  * \warning  
//  228  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  229 void adc0_isr(void){
//  230 
//  231 
//  232   if((ADC0_SC1A & ADC_SC1_COCO_MASK)!= 0){
adc0_isr:
        LDR.W    R0,??DataTable13_8  ;; 0x4003b000
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+24
        BPL.N    ??adc0_isr_0
//  233     adc_sample0 = ADC0_RA;
        LDR.W    R0,??DataTable13_15
        LDR.W    R1,??DataTable13_16  ;; 0x4003b010
        LDR      R1,[R1, #+0]
        STRH     R1,[R0, #+0]
//  234   }
//  235  
//  236   if((ADC0_SC1B & ADC_SC1_COCO_MASK)!= 0){
??adc0_isr_0:
        LDR.W    R0,??DataTable13_17  ;; 0x4003b004
        LDR      R0,[R0, #+0]
//  237     //adc_sample1 = ADC0_RB;
//  238   }
//  239      
//  240 }
        BX       LR               ;; return
//  241 
//  242 
//  243 
//  244 
//  245 /**   pdb_isr,
//  246  * \brief    PDB interrupt service
//  247  * \author   FSL
//  248  * \param    none
//  249  * \return   none
//  250  * \warning  
//  251  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  252 void pdb_isr(void) 
//  253 {
pdb_isr:
        PUSH     {R7,LR}
//  254    // Check if pdb sequence error
//  255    if(PDB0_CH0S & PDB_S_ERR(1))
        LDR.W    R0,??DataTable13_18  ;; 0x40036014
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+31
        BPL.N    ??pdb_isr_0
//  256    {
//  257       pdb_seq_error(0,0); // pretrigger 0 sequence error
        MOVS     R1,#+0
        MOVS     R0,#+0
        BL       pdb_seq_error
//  258    }
//  259    if(PDB0_CH0S & PDB_S_ERR(2))
??pdb_isr_0:
        LDR.W    R0,??DataTable13_18  ;; 0x40036014
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+30
        BPL.N    ??pdb_isr_1
//  260    {
//  261       pdb_seq_error(0,1); // pretrigger 1 sequence error
        MOVS     R1,#+1
        MOVS     R0,#+0
        BL       pdb_seq_error
//  262    }
//  263    if(PDB0_CH1S & PDB_S_ERR(1))
??pdb_isr_1:
        LDR.N    R0,??DataTable13_19  ;; 0x4003603c
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+31
        BPL.N    ??pdb_isr_2
//  264    {
//  265       pdb_seq_error(1,0); // pretrigger 0 sequence error
        MOVS     R1,#+0
        MOVS     R0,#+1
        BL       pdb_seq_error
//  266    }
//  267    if(PDB0_CH1S & PDB_S_ERR(2))
??pdb_isr_2:
        LDR.N    R0,??DataTable13_19  ;; 0x4003603c
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+30
        BPL.N    ??pdb_isr_3
//  268    {
//  269       pdb_seq_error(1,1); // pretrigger 1 sequence error
        MOVS     R1,#+1
        MOVS     R0,#+1
        BL       pdb_seq_error
//  270    }   
//  271    
//  272    
//  273    if(PDB0_SC & PDB_SC_PDBIF_MASK)
??pdb_isr_3:
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        LSLS     R0,R0,#+25
        BPL.N    ??pdb_isr_4
//  274    {
//  275       PDB0_SC &= ~PDB_SC_PDBIF_MASK;  // write 0 to PDBIF to clear which is different from EM256
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        BICS     R0,R0,#0x40
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  276    }
//  277 }
??pdb_isr_4:
        POP      {R0,PC}          ;; return
//  278 
//  279 /**   pdb_init,
//  280  * \brief    configure PDB module to trigger ADC
//  281  * \author   FSL
//  282  * \param    none
//  283  * \return   none
//  284  * \warning  assumes 48MHz IPBus clock
//  285  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  286 void pdb_init(void)
//  287 {
pdb_init:
        PUSH     {R7,LR}
//  288  
//  289    SIM_SCGC6 |= SIM_SCGC6_PDB_MASK;
        LDR.N    R0,??DataTable13_6  ;; 0x4004803c
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x400000
        LDR.N    R1,??DataTable13_6  ;; 0x4004803c
        STR      R0,[R1, #+0]
//  290    enable_irq(INT_PDB0 - 16);
        MOVS     R0,#+34
        BL       enable_irq
//  291   //-------------------------pdb setup---------------------------------
//  292  //1.Set to software trigger input 
//  293  //2.Enable pdb module
//  294  //3.Prescale set to 0
//  295  //4. LDMOD = 0: load immediately after setting LDOK
//  296  //5. enable PDB sequence error interrupt
//  297  //Only enable pdb module then you can write in all channel delay value
//  298  
//  299  PDB0_SC = 0x00000000;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        MOVS     R1,#+0
        STR      R1,[R0, #+0]
//  300  
//  301  // NOTE: PDB must be enabled before writting to buffered registers
//  302  // otherwise, it will be always previous value.
//  303  //Enable PDB
//  304  PDB0_SC |= PDB_SC_PDBEN_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x80
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  305  
//  306  PDB0_SC |= PDB_SC_TRGSEL(0xF); //Software trigger
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0xF00
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  307    
//  308   //Enable continuous mode
//  309  PDB0_SC |= PDB_SC_CONT_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x2
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  310  
//  311  //Enable pre-trigger out to ADC0/1
//  312  PDB0_CH0C1 = PDB_C1_TOS(1)|PDB_C1_EN(1);
        LDR.N    R0,??DataTable13_21  ;; 0x40036010
        MOVW     R1,#+257
        STR      R1,[R0, #+0]
//  313   
//  314 
//  315  
//  316  //Set CH0 DLY0/1
//  317  PDB0_CH0DLY0 = 1000;
        LDR.N    R0,??DataTable13_22  ;; 0x40036018
        MOV      R1,#+1000
        STR      R1,[R0, #+0]
//  318  PDB0_CH0DLY1 = 2000;    // delay the conversion time = 
        LDR.N    R0,??DataTable13_23  ;; 0x4003601c
        MOV      R1,#+2000
        STR      R1,[R0, #+0]
//  319  
//  320    
//  321  PDB0_MOD = 6250;  //50MHz/8KHz  = 6250
        LDR.N    R0,??DataTable13_24  ;; 0x40036004
        MOVW     R1,#+6250
        STR      R1,[R0, #+0]
//  322   
//  323  //Set interrupt delay value 
//  324  PDB0_IDLY = 5000;
        LDR.N    R0,??DataTable13_25  ;; 0x4003600c
        MOVW     R1,#+5000
        STR      R1,[R0, #+0]
//  325  
//  326  //Load delay value
//  327  PDB0_SC |= PDB_SC_LDOK_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x1
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  328  
//  329  //Enable interrupt 
//  330  PDB0_SC |= PDB_SC_PDBIE_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x20
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  331  PDB0_SC |= PDB_SC_PDBEIE_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x20000
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  332 
//  333  //Set software trigger
//  334  PDB0_SC |= PDB_SC_SWTRIG_MASK;
        LDR.N    R0,??DataTable13_20  ;; 0x40036000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x10000
        LDR.N    R1,??DataTable13_20  ;; 0x40036000
        STR      R0,[R1, #+0]
//  335  }
        POP      {R0,PC}          ;; return

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable6:
        DC8      0x0D, 0x0A, 0x00, 0x00
//  336 
//  337 /**   pdb_isr,
//  338  * \brief    count the pdb seq errors, and clear proper flags
//  339  * \author   FSL
//  340  * \param    none
//  341  * \return   none
//  342  * \warning 
//  343  */ 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  344 void pdb_seq_error(uint16 channel,uint16 pretrigger)
//  345 {
//  346     bSeqErr++;
pdb_seq_error:
        LDR.N    R2,??DataTable13_4
        LDR      R2,[R2, #+0]
        ADDS     R2,R2,#+1
        LDR.N    R3,??DataTable13_4
        STR      R2,[R3, #+0]
//  347     if(channel==1)
        UXTH     R0,R0            ;; ZeroExt  R0,R0,#+16,#+16
        CMP      R0,#+1
        BNE.N    ??pdb_seq_error_0
//  348     {
//  349       PDB0_CH1S &= ~PDB_S_ERR(1<<pretrigger);//clear interrupt flag   
        LDR.N    R0,??DataTable13_19  ;; 0x4003603c
        LDR      R0,[R0, #+0]
        MOVS     R2,#+1
        LSLS     R1,R2,R1
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        BICS     R0,R0,R1
        LDR.N    R1,??DataTable13_19  ;; 0x4003603c
        STR      R0,[R1, #+0]
        B.N      ??pdb_seq_error_1
//  350     }
//  351     else if(channel==0)
??pdb_seq_error_0:
        UXTH     R0,R0            ;; ZeroExt  R0,R0,#+16,#+16
        CMP      R0,#+0
        BNE.N    ??pdb_seq_error_1
//  352     {
//  353       PDB0_CH0S &= ~PDB_S_ERR(1<<pretrigger);//clear interrupt flag      
        LDR.N    R0,??DataTable13_18  ;; 0x40036014
        LDR      R0,[R0, #+0]
        MOVS     R2,#+1
        LSLS     R1,R2,R1
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        BICS     R0,R0,R1
        LDR.N    R1,??DataTable13_18  ;; 0x40036014
        STR      R0,[R1, #+0]
//  354     }
//  355 }
??pdb_seq_error_1:
        BX       LR               ;; return
//  356 
//  357 /**   pdb_isr,
//  358  * \brief    PDB handle routine
//  359  * \author   FSL
//  360  * \param    none
//  361  * \return   none
//  362  * \warning  
//  363  */ 
//  364 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  365 void pdb_seq_err_handle(void)
//  366 {
pdb_seq_err_handle:
        PUSH     {R7,LR}
//  367   printf("Error: PDB Sequence error!\r\n");
        LDR.N    R0,??DataTable13_26
        BL       printf
//  368 }
        POP      {R0,PC}          ;; return
//  369 
//  370 
//  371 /**   pdb_isr,
//  372  * \brief    Initialize DMA to store 256 samples of ADC in a ringbuffer
//  373  * \author   b01252 
//  374  * \param    none
//  375  * \return   none
//  376  * \warning  
//  377  */
//  378 
//  379 #define ADC0_DMA_CH_REQ   40
//  380 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  381 void vfnDMAADCCh_Init(void) 
//  382 {
vfnDMAADCCh_Init:
        PUSH     {R7,LR}
//  383   /* eDMA Configurations */
//  384     SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
        LDR.N    R0,??DataTable13_6  ;; 0x4004803c
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x2
        LDR.N    R1,??DataTable13_6  ;; 0x4004803c
        STR      R0,[R1, #+0]
//  385     
//  386     DMAMUX0_CHCFG1 = 0x00;
        LDR.N    R0,??DataTable13_27  ;; 0x40021001
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//  387     //DMAMUX_CHCFG15 = 0x00;        
//  388     
//  389     DMA_ERQ = (DMA_ERQ_ERQ0_MASK); // Enable DMA request 14,15
        LDR.N    R0,??DataTable13_28  ;; 0x4000800c
        MOVS     R1,#+1
        STR      R1,[R0, #+0]
//  390     DMA_CR |= DMA_CR_EDBG_MASK;
        LDR.N    R0,??DataTable13_29  ;; 0x40008000
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x2
        LDR.N    R1,??DataTable13_29  ;; 0x40008000
        STR      R0,[R1, #+0]
//  391     
//  392     DMAMUX0_CHCFG0 = (DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(ADC0_DMA_CH_REQ));  
        LDR.N    R0,??DataTable13_30  ;; 0x40021000
        MOVS     R1,#+168
        STRB     R1,[R0, #+0]
//  393     enable_irq(INT_DMA0-16);
        MOVS     R0,#+0
        BL       enable_irq
//  394 /*    
//  395 // configure DMA_15    
//  396     DMAMUX_CHCFG15 = 0x00;
//  397     
//  398     DMA_ERQ = (DMA_ERQ_ERQ15_MASK); // Enable DMA request 14,15
//  399     DMA_CR |= DMA_CR_EDBG_MASK;
//  400     
//  401     DMAMUX_CHCFG15 = (DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(ADC0_DMA_CH_REQ));  
//  402     enable_irq(INT_DMA15-16);
//  403  */
//  404     
//  405 }
        POP      {R0,PC}          ;; return
//  406 
//  407 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  408 void vfnDMA_Config (dma_tcd *tcdPtr)
//  409 {
vfnDMA_Config:
        PUSH     {R4}
//  410     int8 i; 
//  411   
//  412     i = tcdPtr->channelno ;
        LDR      R1,[R0, #+32]
//  413     
//  414     DMA_SADDR(i) = tcdPtr->saddr ;   
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        LDR.N    R3,??DataTable13_31  ;; 0x40009000
        LDR      R4,[R0, #+0]
        STR      R4,[R2, R3]
//  415     DMA_ATTR(i) = tcdPtr->tcdAttr;                                   
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDRH     R3,[R0, #+6]
        STRH     R3,[R2, #+6]
//  416     DMA_SOFF(i) = tcdPtr->soff;    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDRH     R3,[R0, #+4]
        STRH     R3,[R2, #+4]
//  417     DMA_NBYTES_MLNO(i) = tcdPtr->nbytes;    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDR      R3,[R0, #+8]
        STR      R3,[R2, #+8]
//  418     DMA_SLAST(i) = 0x0;    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        MOVS     R3,#+0
        STR      R3,[R2, #+12]
//  419     DMA_DADDR(i) = tcdPtr->daddr;    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDR      R3,[R0, #+16]
        STR      R3,[R2, #+16]
//  420     DMA_CITER_ELINKNO(i) = DMA_CITER_ELINKNO_CITER(tcdPtr->loopcount);                                            
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDR      R3,[R0, #+40]
        LSLS     R3,R3,#+17       ;; ZeroExtS R3,R3,#+17,#+17
        LSRS     R3,R3,#+17
        STRH     R3,[R2, #+22]
//  421     DMA_DOFF(i) = tcdPtr->doff;                                                  
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDRH     R3,[R0, #+20]
        STRH     R3,[R2, #+20]
//  422     DMA_DLAST_SGA(i) = 0x0;    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        MOVS     R3,#+0
        STR      R3,[R2, #+24]
//  423     DMA_BITER_ELINKNO(i) = DMA_BITER_ELINKNO_BITER(tcdPtr->loopcount);    
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R2,R1,#+5
        ADD      R2,R2,#+1073741824
        ADDS     R2,R2,#+36864
        LDR      R0,[R0, #+40]
        LSLS     R0,R0,#+17       ;; ZeroExtS R0,R0,#+17,#+17
        LSRS     R0,R0,#+17
        STRH     R0,[R2, #+30]
//  424     DMA_CSR(i) = /*DMA_CSR_INTHALF_MASK|*/DMA_CSR_INTMAJOR_MASK;	
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LSLS     R0,R1,#+5
        ADD      R0,R0,#+1073741824
        ADDS     R0,R0,#+36864
        MOVS     R1,#+2
        STRH     R1,[R0, #+28]
//  425 
//  426 }
        POP      {R4}
        BX       LR               ;; return
//  427 
//  428 /*   
//  429 void DAM_adc0(uint_32 *source_address)
//  430 {
//  431    // SPI2 TX
//  432     tcd2.saddr = (uint_32)source_address;
//  433     tcd2.daddr = (uint_32)&ADC0_RA;
//  434     tcd2.nbytes = 4;
//  435     tcd2.tcdAttr = (DMA_ATTR_SSIZE(BITS32)|DMA_ATTR_DSIZE(BITS32)) ;
//  436     tcd2.soff =0x04;
//  437     tcd2.doff =0x00;
//  438     tcd2.loopcount =SPI_NUMBER;
//  439     tcd2.channelno = 14;
//  440     
//  441     vfnDMA_Config(&tcd2);
//  442 }
//  443 */
//  444 
//  445 /*  Initializes DMA to read from ADC0 resulta and store result in RAM*/

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  446 void vfnDMAtoRAM(uint32 *destiny_address)
//  447 {
vfnDMAtoRAM:
        PUSH     {R7,LR}
//  448    // SPI1 RX
//  449     tcd1.saddr = (uint32)&ADC0_RA;
        LDR.N    R1,??DataTable13_32
        LDR.N    R2,??DataTable13_16  ;; 0x4003b010
        STR      R2,[R1, #+0]
//  450     tcd1.daddr = (uint32)destiny_address;
        LDR.N    R1,??DataTable13_32
        STR      R0,[R1, #+16]
//  451     tcd1.nbytes = 4;
        LDR.N    R0,??DataTable13_32
        MOVS     R1,#+4
        STR      R1,[R0, #+8]
//  452     tcd1.tcdAttr = (DMA_ATTR_SSIZE(BITS32)|DMA_ATTR_DSIZE(BITS32)) ;
        LDR.N    R0,??DataTable13_32
        MOVW     R1,#+514
        STRH     R1,[R0, #+6]
//  453     tcd1.soff =0x00;
        LDR.N    R0,??DataTable13_32
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
//  454     tcd1.doff =0x04;
        LDR.N    R0,??DataTable13_32
        MOVS     R1,#+4
        STRH     R1,[R0, #+20]
//  455     tcd1.loopcount = 128;
        LDR.N    R0,??DataTable13_32
        MOVS     R1,#+128
        STR      R1,[R0, #+40]
//  456     tcd1.channelno = 0; 
        LDR.N    R0,??DataTable13_32
        MOVS     R1,#+0
        STR      R1,[R0, #+32]
//  457     vfnDMA_Config(&tcd1);
        LDR.N    R0,??DataTable13_32
        BL       vfnDMA_Config
//  458 }
        POP      {R0,PC}          ;; return
//  459 
//  460 void  real128_fft(void);   
//  461 /*interrumpe al final */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  462 void vfnDMACh14ISR(void)
//  463 {	
vfnDMACh14ISR:
        PUSH     {R7,LR}
//  464         static uint16 buffer_flag =0;
//  465 
//  466       
//  467 	DMA_CINT = DMA_CINT_CINT(0); //Clear Interrupt Request Register (DMA_CINT)
        LDR.N    R0,??DataTable13_33  ;; 0x4000801f
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//  468         DMA_SSRT = DMA_SSRT_SSRT(0); //Set START Bit Register (DMA_SSRT)       
        LDR.N    R0,??DataTable13_34  ;; 0x4000801d
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//  469         if ((buffer_flag) == 0)
        LDR.N    R0,??DataTable13_35
        LDRH     R0,[R0, #+0]
        CMP      R0,#+0
        BNE.N    ??vfnDMACh14ISR_0
//  470         { 
//  471           buffer_flag = 0x1;          // prepare for following
        LDR.N    R0,??DataTable13_35
        MOVS     R1,#+1
        STRH     R1,[R0, #+0]
//  472           buffer=0x80;
        LDR.N    R0,??DataTable13_36
        MOVS     R1,#+128
        STRB     R1,[R0, #+0]
//  473           vfnDMAtoRAM(&adc_buffer[128]);
        LDR.N    R0,??DataTable13_37
        BL       vfnDMAtoRAM
        B.N      ??vfnDMACh14ISR_1
//  474         }
//  475         else
//  476         {
//  477           buffer_flag = 0x0;
??vfnDMACh14ISR_0:
        LDR.N    R0,??DataTable13_35
        MOVS     R1,#+0
        STRH     R1,[R0, #+0]
//  478           dmaIsrCount++;
        LDR.N    R0,??DataTable13_38
        LDRH     R0,[R0, #+0]
        ADDS     R0,R0,#+1
        LDR.N    R1,??DataTable13_38
        STRH     R0,[R1, #+0]
//  479           buffer=0x81;
        LDR.N    R0,??DataTable13_36
        MOVS     R1,#+129
        STRB     R1,[R0, #+0]
//  480           vfnDMAtoRAM(&adc_buffer[0]);         
        LDR.N    R0,??DataTable13_5
        BL       vfnDMAtoRAM
//  481         } 
//  482         
//  483         
//  484 // Select between  Microphone or Potentiometer channel        
//  485          if (ti_test_adc==0) adc_reading_channel = ADC_MIC_CHANNEL;
??vfnDMACh14ISR_1:
        LDR.N    R0,??DataTable13_13
        LDRH     R0,[R0, #+0]
        CMP      R0,#+0
        BNE.N    ??vfnDMACh14ISR_2
        LDR.N    R0,??DataTable13_11
        MOVS     R1,#+3
        STRB     R1,[R0, #+0]
        B.N      ??vfnDMACh14ISR_3
//  486          else adc_reading_channel = ADC_POT_CHANNEL;
??vfnDMACh14ISR_2:
        LDR.N    R0,??DataTable13_11
        MOVS     R1,#+21
        STRB     R1,[R0, #+0]
//  487 
//  488          if (adc_reading_channel != last_adc_channel)
??vfnDMACh14ISR_3:
        LDR.N    R0,??DataTable13_11
        LDRB     R0,[R0, #+0]
        LDR.N    R1,??DataTable13_12
        LDRB     R1,[R1, #+0]
        CMP      R0,R1
        BEQ.N    ??vfnDMACh14ISR_4
//  489          {
//  490            ADC0_SC2   |= ADC_SC2_ADTRG_MASK; // Hardware trigger Software trigger
        LDR.N    R0,??DataTable13_14  ;; 0x4003b020
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x40
        LDR.N    R1,??DataTable13_14  ;; 0x4003b020
        STR      R0,[R1, #+0]
//  491            ADC0_SC1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(adc_reading_channel);  // reads MIC or POT signal
        LDR.N    R0,??DataTable13_11
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0x1F
        LDR.N    R1,??DataTable13_8  ;; 0x4003b000
        STR      R0,[R1, #+0]
//  492            last_adc_channel = adc_reading_channel;
        LDR.N    R0,??DataTable13_12
        LDR.N    R1,??DataTable13_11
        LDRB     R1,[R1, #+0]
        STRB     R1,[R0, #+0]
//  493          }
//  494    
//  495         
//  496      
//  497          real128_fft();      
??vfnDMACh14ISR_4:
        BL       real128_fft
//  498 }
        POP      {R0,PC}          ;; return

        SECTION `.bss`:DATA:REORDER:NOROOT(1)
??buffer_flag:
        DS8 2
//  499 
//  500 
//  501 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  502 void vfnDMA_ErrorIsr(void)
//  503 {	
vfnDMA_ErrorIsr:
        PUSH     {R7,LR}
//  504      printf("DMA error");
        LDR.N    R0,??DataTable13_39
        BL       printf
//  505      DMA_errorCount++;
        LDR.N    R0,??DataTable13_40
        LDRH     R0,[R0, #+0]
        ADDS     R0,R0,#+1
        LDR.N    R1,??DataTable13_40
        STRH     R0,[R1, #+0]
//  506 }
        POP      {R0,PC}          ;; return

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13:
        DC32     `?<Constant "Welcome to PDB trigge...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_1:
        DC32     `?<Constant "Please make sure sign...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_2:
        DC32     wSamplesCounter

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_3:
        DC32     bSamplesReady

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_4:
        DC32     bSeqErr

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_5:
        DC32     adc_buffer

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_6:
        DC32     0x4004803c

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_7:
        DC32     Master_Adc_Config

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_8:
        DC32     0x4003b000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_9:
        DC32     `?<Constant "ADC calibration error">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_10:
        DC32     CalibrationStore+0x1A

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_11:
        DC32     adc_reading_channel

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_12:
        DC32     last_adc_channel

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_13:
        DC32     ti_test_adc

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_14:
        DC32     0x4003b020

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_15:
        DC32     adc_sample0

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_16:
        DC32     0x4003b010

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_17:
        DC32     0x4003b004

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_18:
        DC32     0x40036014

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_19:
        DC32     0x4003603c

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_20:
        DC32     0x40036000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_21:
        DC32     0x40036010

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_22:
        DC32     0x40036018

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_23:
        DC32     0x4003601c

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_24:
        DC32     0x40036004

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_25:
        DC32     0x4003600c

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_26:
        DC32     `?<Constant "Error: PDB Sequence e...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_27:
        DC32     0x40021001

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_28:
        DC32     0x4000800c

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_29:
        DC32     0x40008000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_30:
        DC32     0x40021000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_31:
        DC32     0x40009000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_32:
        DC32     tcd1

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_33:
        DC32     0x4000801f

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_34:
        DC32     0x4000801d

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_35:
        DC32     ??buffer_flag

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_36:
        DC32     buffer

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_37:
        DC32     adc_buffer+0x200

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_38:
        DC32     dmaIsrCount

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_39:
        DC32     `?<Constant "DMA error">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable13_40:
        DC32     DMA_errorCount

        SECTION `.iar_vfe_header`:DATA:REORDER:NOALLOC:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
        DC32 0

        SECTION __DLIB_PERTHREAD:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        SECTION __DLIB_PERTHREAD_init:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "Welcome to PDB trigge...">`:
        DATA
        DC8 "Welcome to PDB trigger ADC demo!\015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "Please make sure sign...">`:
        DATA
        DC8 50H, 6CH, 65H, 61H, 73H, 65H, 20H, 6DH
        DC8 61H, 6BH, 65H, 20H, 73H, 75H, 72H, 65H
        DC8 20H, 73H, 69H, 67H, 6EH, 61H, 6CH, 20H
        DC8 6FH, 6EH, 20H, 41H, 44H, 43H, 31H, 20H
        DC8 63H, 68H, 61H, 6EH, 6EH, 65H, 6CH, 31H
        DC8 20H, 69H, 73H, 20H, 72H, 65H, 61H, 64H
        DC8 79H, 2CH, 20H, 70H, 72H, 65H, 73H, 73H
        DC8 20H, 61H, 6EH, 79H, 20H, 6BH, 65H, 79H
        DC8 20H, 74H, 6FH, 20H, 63H, 6FH, 6EH, 74H
        DC8 69H, 6EH, 75H, 65H, 2EH, 2EH, 2EH, 21H
        DC8 0
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
        DATA
        DC8 "\015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "ADC calibration error">`:
        DATA
        DC8 "ADC calibration error"
        DC8 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "Error: PDB Sequence e...">`:
        DATA
        DC8 "Error: PDB Sequence error!\015\012"
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "DMA error">`:
        DATA
        DC8 "DMA error"
        DC8 0, 0

        END
//  507 
//  508 
// 
// 1 273 bytes in section .bss
//   192 bytes in section .rodata
// 1 358 bytes in section .text
// 
// 1 358 bytes of CODE  memory
//   192 bytes of CONST memory
// 1 273 bytes of DATA  memory
//
//Errors: none
//Warnings: none
