///////////////////////////////////////////////////////////////////////////////
//                                                                            /
// IAR ANSI C/C++ Compiler V6.30.1.53127/W32 for ARM    08/Mar/2012  18:18:20 /
// Copyright 1999-2011 IAR Systems AB.                                        /
//                                                                            /
//    Cpu mode     =  thumb                                                   /
//    Endian       =  little                                                  /
//    Source file  =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\src\drivers\smc\smc.c                                /
//    Command line =  "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\src\drivers\smc\smc.c" -D IAR -D TOWER -D           /
//                    TWR_K20D50M -lCN "D:\Profiles\b01252\My                 /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" -lB         /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" /
//                     -o "D:\Profiles\b01252\My                              /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\FLASH_128KB_PFLASH\Obj\" --no_cse     /
//                    --no_unroll --no_inline --no_code_motion --no_tbaa      /
//                    --no_clustering --no_scheduling --debug                 /
//                    --endian=little --cpu=Cortex-M4 -e --fpu=None           /
//                    --dlib_config "C:\Program Files\IAR Systems\Embedded    /
//                    Workbench 6.0_5\arm\INC\c\DLib_Config_Normal.h" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\common\" -I  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\" -I     /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\headers\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\uart\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\mcg\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\wdog\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\rcm\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\lptmr\" -I       /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\platforms\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\" -I                /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\projects\TWR /
//                    K20D50M_Demo\" -I "D:\Profiles\b01252\My                /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \dma\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc16\" -I "D:\Profiles\b01252\My                      /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \i2c\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \tsi\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \angle_calculation\" -I "D:\Profiles\b01252\My          /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \buzzer\" -I "D:\Profiles\b01252\My                     /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \fft_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \irda_test\" -I "D:\Profiles\b01252\My                  /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \cmt_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \protocol\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \task_mgr\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \TWRK20_specific\" -I "D:\Profiles\b01252\My            /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \rtc\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Lib\interm /
//                    ediateFiles\" -I "D:\Profiles\b01252\My                 /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Include\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \DeviceSupport\ARM\ARMCM4\" -I "D:\Profiles\b01252\My   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4\CoreSupport\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \CoreSupportLiker Options-Library\" -I                  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Li /
//                    b\Lib\intermediateFiles\arm_cortexM4_math.lib\" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\build\" -Ol      /
//                    --use_c++_inline -I "C:\Program Files\IAR               /
//                    Systems\Embedded Workbench 6.0_5\arm\CMSIS\Include\"    /
//                    -D ARM_MATH_CM4                                         /
//    List file    =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\sm /
//                    c.s                                                     /
//                                                                            /
//                                                                            /
///////////////////////////////////////////////////////////////////////////////

        NAME `smc`

        #define SHT_PROGBITS 0x1

        EXTERN printf
        EXTERN stop
        EXTERN wait

        PUBLIC disable_lpwui
        PUBLIC enable_lpwui
        PUBLIC enter_lls
        PUBLIC enter_stop
        PUBLIC enter_vlls0
        PUBLIC enter_vlls0_nopor
        PUBLIC enter_vlls1
        PUBLIC enter_vlls2
        PUBLIC enter_vlls3
        PUBLIC enter_vlpr
        PUBLIC enter_vlps
        PUBLIC enter_wait
        PUBLIC exit_vlpr

// D:\Profiles\b01252\My Documents\Freescale\P0\software\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\src\drivers\smc\smc.c
//    1 /*
//    2  * File:        smc.c
//    3  * Purpose:     Provides routines for entering low power modes.
//    4  *
//    5  * Notes:	Since the wakeup mechanism for low power modes
//    6  *              will be application specific, these routines
//    7  *              do not include code to setup interrupts to exit
//    8  *              from the low power modes. The desired means of
//    9  *              low power mode exit should be configured before
//   10  *              calling any of these functions.
//   11  *
//   12  *              These routines do not include protection to
//   13  *              prevent illegal state transitions in the mode
//   14  *              controller, and all routines that write to the
//   15  *              PMPROT register write a value to allow all
//   16  *              possible low power modes (it is write once, so
//   17  *              if only the currently requested mode is enabled
//   18  *              a different mode couldn't be enabled later on).
//   19  *              
//   20  */
//   21 
//   22 #include "common.h"
//   23 #include "smc.h"
//   24 
//   25 /********************************************************************/
//   26 /* WAIT mode entry routine. Puts the processor into wait mode.
//   27  * In this mode the core clock is disabled (no code executing), but 
//   28  * bus clocks are enabled (peripheral modules are operational). 
//   29  *
//   30  * Mode transitions:
//   31  * RUN -> WAIT
//   32  * VLPR -> VLPW
//   33  *
//   34  * This function can be used to enter normal wait mode or VLPW
//   35  * mode. If you are executing in normal run mode when calling this
//   36  * function, then you will enter normal wait mode. If you are in VLPR
//   37  * mode when calling this function, then you will enter VLPW mode instead.
//   38  *
//   39  * NOTE: Some modules include a programmable option to disable them in 
//   40  * wait mode. If those modules are programmed to disable in wait mode, 
//   41  * they will not be able to generate interrupts to wake up the core.
//   42  *
//   43  * WAIT mode is exited using any enabled interrupt or RESET, so no
//   44  * exit_wait routine is needed. 
//   45  *
//   46 * If in VLPW mode, the statue of the SMC_PMCTRL[LPWUI] bit determines if 
//   47  * the processor exits to VLPR (LPWUI cleared) or normal run mode (LPWUI 
//   48  * set). The enable_lpwui() and disable_lpwui()functions can be used to set
//   49  * this bit to the desired option prior to calling enter_wait().
//   50  * 
//   51  * 
//   52  * Parameters:
//   53  * none
//   54  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//   55 void enter_wait(void)
//   56 {
enter_wait:
        PUSH     {R7,LR}
//   57     wait();
        BL       wait
//   58 }
        POP      {R0,PC}          ;; return
//   59 /********************************************************************/
//   60 /* STOP mode entry routine. Puts the processor into normal stop mode.
//   61  * In this mode core, bus and peripheral clocks are disabled.
//   62  *
//   63  * Mode transitions:
//   64  * RUN -> STOP
//   65  * VLPR -> VLPS
//   66  *
//   67  * This function can be used to enter normal stop mode or VLPS
//   68  * mode. If you are executing in normal run mode when calling this
//   69  * function, then you will enter normal stop mode. If you are in VLPR
//   70  * mode when calling this function, then you will enter VLPS mode instead.
//   71  *
//   72  * STOP mode is exited using any enabled interrupt or RESET, so no
//   73  * exit_stop routine is needed.
//   74  *
//   75  * Parameters:
//   76  * none
//   77  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//   78 void enter_stop(void)
//   79 {
enter_stop:
        PUSH     {R7,LR}
//   80     /* Set the STOPM field to 0b000 for normal STOP mode - Need to retain state of LPWUI bit 8 */
//   81     SMC_PMCTRL =  SMC_PMCTRL_STOPM(0);           // set STOPM = 0b000
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//   82     stop();
        BL       stop
//   83 }
        POP      {R0,PC}          ;; return
//   84 /********************************************************************/
//   85 /* VLPR mode entry routine. Puts the processor into very low power
//   86  * run mode. In this mode all clocks are enabled, but the core, bus,
//   87  * and peripheral clocks are limited to 2MHz or less. The flash 
//   88  * clock is limited to 1MHz or less. 
//   89  *
//   90  * Mode transitions:
//   91  * RUN -> VLPR
//   92  *
//   93  * exit_vlpr() function or an interrupt with LPWUI set can be used 
//   94  * to switch from VLPR back to RUN. The enable_lpwui() and disable_lpwui()
//   95  * functions can be used to set LPWUI to the desired option prior to 
//   96  * calling enter_vlpr().
//   97  *
//   98  * Parameters:
//   99  * none
//  100  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  101 void enter_vlpr(char lpwui_value)
//  102 {
enter_vlpr:
        PUSH     {R7,LR}
//  103    
//  104   if ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4){
        LDR.N    R1,??DataTable11_1  ;; 0x4007e003
        LDRB     R1,[R1, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        ANDS     R1,R1,#0x7F
        CMP      R1,#+4
        BNE.N    ??enter_vlpr_0
//  105     	 printf(" \n[enter_vlpr] Already in VLPR Mode ! ");
        LDR.N    R0,??DataTable11_2
        BL       printf
//  106          return;
        B.N      ??enter_vlpr_1
//  107          }
//  108   SMC_PMPROT = SMC_PMPROT_AVLP_MASK;  // write oneif not all set make sure all enabled
??enter_vlpr_0:
        LDR.N    R1,??DataTable11_3  ;; 0x4007e000
        MOVS     R2,#+32
        STRB     R2,[R1, #+0]
//  109                                        //this write-once bit allows the MCU to enter the
//  110                                        //very low power modes: VLPR, VLPW, and VLPS.
//  111     
//  112    if(lpwui_value){
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        CMP      R0,#+0
        BEQ.N    ??enter_vlpr_2
//  113        SMC_PMCTRL = SMC_PMCTRL_LPWUI_MASK | SMC_PMCTRL_RUNM(2);   
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        MOVS     R1,#+192
        STRB     R1,[R0, #+0]
        B.N      ??enter_vlpr_3
//  114    } else {
//  115        SMC_PMCTRL = (~SMC_PMCTRL_LPWUI_MASK) & SMC_PMCTRL_RUNM(2);  
??enter_vlpr_2:
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        MOVS     R1,#+64
        STRB     R1,[R0, #+0]
        B.N      ??enter_vlpr_3
//  116    }    
//  117         
//  118     
//  119       /* Wait for VLPS regulator mode to be confirmed */
//  120 
//  121    while((PMC_REGSC & PMC_REGSC_REGONS_MASK) ==0x04){
//  122      printf(" \n[enter_vlpr] Waiting on REGONS to clear ! ");
??enter_vlpr_4:
        LDR.N    R0,??DataTable11_4
        BL       printf
//  123    }   // 0 Regulator in stop Reg mode
??enter_vlpr_3:
        LDR.N    R0,??DataTable11_5  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        LSLS     R0,R0,#+29
        BMI.N    ??enter_vlpr_4
//  124        // 1 MCU is in Run regulation mode
//  125    printf("[enter_vlpr] Now in VLPR at 19200 baud  \r\n");
        LDR.N    R0,??DataTable11_6
        BL       printf
        B.N      ??enter_vlpr_5
//  126    
//  127          while((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK) != 4){
//  128     	 printf(" \n[enter_vlpr] HALT PMSTAT does not indicate in VLPR Mode ! ");
??enter_vlpr_6:
        LDR.N    R0,??DataTable11_7
        BL       printf
//  129          }
??enter_vlpr_5:
        LDR.N    R0,??DataTable11_1  ;; 0x4007e003
        LDRB     R0,[R0, #+0]
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        ANDS     R0,R0,#0x7F
        CMP      R0,#+4
        BNE.N    ??enter_vlpr_6
//  130 }
??enter_vlpr_1:
        POP      {R0,PC}          ;; return
//  131 /********************************************************************/
//  132 /* VLPR mode exit routine. Puts the processor into normal run mode
//  133  * from VLPR mode. You can transition from VLPR to normal run using
//  134  * this function or an interrupt with LPWUI set. The enable_lpwui() 
//  135  * and disable_lpwui() functions can be used to set LPWUI to the 
//  136  * desired option prior to calling enter_vlpr().
//  137  *
//  138  * Mode transitions:
//  139  * VLPR -> RUN
//  140  *
//  141  * Parameters:
//  142  * none
//  143  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  144 void exit_vlpr(void)
//  145 {
exit_vlpr:
        PUSH     {R7,LR}
//  146     /* check to make sure in VLPR before exiting    */
//  147     if  ((SMC_PMSTAT & SMC_PMSTAT_PMSTAT_MASK)== 4) {
        LDR.N    R0,??DataTable11_1  ;; 0x4007e003
        LDRB     R0,[R0, #+0]
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        ANDS     R0,R0,#0x7F
        CMP      R0,#+4
        BNE.N    ??exit_vlpr_0
//  148       
//  149        /* Clear RUNM */
//  150        SMC_PMCTRL &= ~(SMC_PMCTRL_RUNM(0x3));
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0x9F
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
        B.N      ??exit_vlpr_1
//  151                       
//  152        /* Wait for normal RUN regulation mode to be confirmed */                   
//  153        // 0 MCU is not in run regulation mode
//  154        // 1 MCU is in run regulation mode
//  155        while(!(PMC_REGSC & PMC_REGSC_REGONS_MASK)){
//  156     	 printf(" \n[exit_vlpr] Waiting on REGONS bit to set to indicate Run regulation mode ! ");
??exit_vlpr_2:
        LDR.N    R0,??DataTable11_8
        BL       printf
//  157          } 
??exit_vlpr_1:
        LDR.N    R0,??DataTable11_5  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        LSLS     R0,R0,#+29
        BPL.N    ??exit_vlpr_2
//  158        
//  159     }  //if in VLPR mode
//  160      // else if not in VLPR ignore call
//  161 }
??exit_vlpr_0:
        POP      {R0,PC}          ;; return
//  162 /********************************************************************/
//  163 /* VLPS mode entry routine. Puts the processor into VLPS mode directly
//  164  * from normal run mode. 
//  165  *
//  166  * Mode transitions:
//  167  * RUN -> VLPS
//  168  *
//  169  * If VLPS mode is entered directly from normal RUN mode, then the 
//  170  * LPWUI bit is forced to 1 by hardware. This means that when an
//  171  * interrupt occurs you will exit to normal run mode instead of VLPR.
//  172  *
//  173  * If however VLPS mode is entered from VLPR the state of the LPWUI bit
//  174  * determines the state the MCU will return to upon exit from VLPS.If LPWUI is set
//  175  * and an interrupt occurs you will exit to normal run mode instead of VLPR. 
//  176  * If LPWUI is clear and an interrupt occurs you will exit to VLPR.
//  177  *
//  178  * Parameters:  value of LPWUI
//  179  * none
//  180  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  181 void enter_vlps(char lpwui_value)
//  182 {
enter_vlps:
        PUSH     {R7,LR}
//  183     /* Write to PMPROT to allow VLPS power modes */
//  184     SMC_PMPROT = SMC_PMPROT_AVLP_MASK;   // write oneif not all set make sure all enabled
        LDR.N    R1,??DataTable11_3  ;; 0x4007e000
        MOVS     R2,#+32
        STRB     R2,[R1, #+0]
//  185                                        //this write-once bit allows the MCU to enter the
//  186                                        //very low power modes: VLPR, VLPW, and VLPS.
//  187         
//  188     /* Set the LPLLSM field to 0b010 for VLPS mode - Need to set state of LPWUI bit 8 */
//  189     if(lpwui_value){
        UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
        CMP      R0,#+0
        BEQ.N    ??enter_vlps_0
//  190      SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  191                   SMC_PMCTRL_STOPM(0x2) | 
//  192                   SMC_PMCTRL_LPWUI_MASK ;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x82
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
        B.N      ??enter_vlps_1
//  193      } else {
//  194      SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |~SMC_PMCTRL_LPWUI_MASK)) |
//  195                   SMC_PMCTRL_STOPM(0x2) ;
??enter_vlps_0:
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0x7F
        ORRS     R0,R0,#0x2
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  196      }  
//  197     /* Now execute the stop instruction to go into VLPS */
//  198     stop();
??enter_vlps_1:
        BL       stop
//  199 }
        POP      {R0,PC}          ;; return
//  200 /********************************************************************/
//  201 /* LLS mode entry routine. Puts the processor into LLS mode from
//  202  * normal run mode or VLPR. 
//  203  *
//  204  * Mode transitions:
//  205  * RUN -> LLS
//  206  * VLPR -> LLS
//  207  *
//  208  * NOTE: LLS mode will always exit to RUN mode even if you were 
//  209  * in VLPR mode before entering LLS.
//  210  *
//  211  * Wakeup from LLS mode is controlled by the LLWU module. Most
//  212  * modules cannot issue a wakeup interrupt in LLS mode, so make
//  213  * sure to setup the desired wakeup sources in the LLWU before 
//  214  * calling this function.
//  215  *
//  216  * Parameters:
//  217  * none
//  218  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  219 void enter_lls(void)
//  220 {
enter_lls:
        PUSH     {R7,LR}
//  221     /* Write to PMPROT to allow LLS power modes */
//  222     SMC_PMPROT = SMC_PMPROT_ALLS_MASK;   //this write-once bit allows the MCU to enter the
        LDR.N    R0,??DataTable11_3  ;; 0x4007e000
        MOVS     R1,#+8
        STRB     R1,[R0, #+0]
//  223                                        //LLS low power mode
//  224     /* Set the LPLLSM field to 0b011 for LLS mode  */
//  225     SMC_PMCTRL = SMC_PMCTRL_STOPM(0x3) ; 
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        MOVS     R1,#+3
        STRB     R1,[R0, #+0]
//  226     /* Now execute the stop instruction to go into LLS */
//  227     stop();
        BL       stop
//  228 }
        POP      {R0,PC}          ;; return
//  229 /********************************************************************/
//  230 /* VLLS3 mode entry routine. Puts the processor into VLLS3 mode from
//  231  * normal run mode or VLPR. 
//  232  *
//  233  * Mode transitions:
//  234  * RUN -> VLLS3
//  235  * VLPR -> VLLS3
//  236  *
//  237  * NOTE: VLLSx modes will always exit to RUN mode even if you were 
//  238  * in VLPR mode before entering VLLSx.
//  239  *
//  240  * Wakeup from VLLSx mode is controlled by the LLWU module. Most
//  241  * modules cannot issue a wakeup interrupt in VLLSx mode, so make
//  242  * sure to setup the desired wakeup sources in the LLWU before 
//  243  * calling this function.
//  244  *
//  245  * Parameters:
//  246  * none  
//  247  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  248 void enter_vlls3(void)
//  249 {
enter_vlls3:
        PUSH     {R7,LR}
//  250     /* Write to PMPROT to allow VLLS3 power modes */
//  251     SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
        LDR.N    R0,??DataTable11_3  ;; 0x4007e000
        MOVS     R1,#+2
        STRB     R1,[R0, #+0]
//  252         
//  253     /* Set the VLLSM field to 0b100 for VLLS3 mode - Need to retain state of LPWUI bit 8 */
//  254     SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  255                   SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x4
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  256  
//  257     SMC_VLLSCTRL =  SMC_VLLSCTRL_VLLSM(3);           // set VLLSM = 0b11
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        MOVS     R1,#+3
        STRB     R1,[R0, #+0]
//  258 
//  259     /* Now execute the stop instruction to go into VLLS3 */
//  260     stop();
        BL       stop
//  261 }
        POP      {R0,PC}          ;; return
//  262 /********************************************************************/
//  263 /* VLLS2 mode entry routine. Puts the processor into VLLS2 mode from
//  264  * normal run mode or VLPR. 
//  265  *
//  266  * Mode transitions:
//  267  * RUN -> VLLS2
//  268  * VLPR -> VLLS2
//  269  *
//  270  * NOTE: VLLSx modes will always exit to RUN mode even if you were 
//  271  * in VLPR mode before entering VLLSx.
//  272  *
//  273  * Wakeup from VLLSx mode is controlled by the LLWU module. Most
//  274  * modules cannot issue a wakeup interrupt in VLLSx mode, so make
//  275  * sure to setup the desired wakeup sources in the LLWU before 
//  276  * calling this function.
//  277  *
//  278  * Parameters:
//  279  * none  
//  280  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  281 void enter_vlls2(void)
//  282 {
enter_vlls2:
        PUSH     {R7,LR}
//  283     /* Write to PMPROT to allow VLLS2 power modes */
//  284     SMC_PMPROT = SMC_PMPROT_AVLLS_MASK;
        LDR.N    R0,??DataTable11_3  ;; 0x4007e000
        MOVS     R1,#+2
        STRB     R1,[R0, #+0]
//  285         
//  286     /* Set the VLLSM field to 0b100 for VLLS2 mode - Need to retain state of LPWUI bit 8 */
//  287     SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  288                   SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x4
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  289  
//  290     SMC_VLLSCTRL =  SMC_VLLSCTRL_VLLSM(2);           // set VLLSM = 0b10
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        MOVS     R1,#+2
        STRB     R1,[R0, #+0]
//  291         
//  292     /* Now execute the stop instruction to go into VLLS2 */
//  293     stop();
        BL       stop
//  294 }
        POP      {R0,PC}          ;; return
//  295 /********************************************************************/
//  296 /* VLLS1 mode entry routine. Puts the processor into VLLS1 mode from
//  297  * normal run mode or VLPR. 
//  298  *
//  299  * Mode transitions:
//  300  * RUN -> VLLS1
//  301  * VLPR -> VLLS1
//  302  *
//  303  * NOTE: VLLSx modes will always exit to RUN mode even if you were 
//  304  * in VLPR mode before entering VLLSx.
//  305  *
//  306  * Wakeup from VLLSx mode is controlled by the LLWU module. Most
//  307  * modules cannot issue a wakeup interrupt in VLLSx mode, so make
//  308  * sure to setup the desired wakeup sources in the LLWU before 
//  309  * calling this function.
//  310  *
//  311  * Parameters:
//  312  * none  
//  313  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  314 void enter_vlls1(void)
//  315 {
enter_vlls1:
        PUSH     {R7,LR}
//  316     /* Write to PMPROT to allow all possible power modes */
//  317     /* Set the VLLSM field to 0b100 for VLLS1 mode - Need to retain state of LPWUI bit 8 */
//  318     SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  319                   SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x4
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  320 
//  321     SMC_VLLSCTRL =  SMC_VLLSCTRL_VLLSM(1);           // set VLLSM = 0b01
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        MOVS     R1,#+1
        STRB     R1,[R0, #+0]
//  322        
//  323     /* Now execute the stop instruction to go into VLLS1 */
//  324     stop();
        BL       stop
//  325 }
        POP      {R0,PC}          ;; return
//  326 
//  327 /********************************************************************/
//  328 /* VLLS0 mode entry routine. Puts the processor into VLLS0 mode from
//  329  * normal run mode or VLPR. 
//  330  *
//  331  * Mode transitions:
//  332  * RUN -> VLLS0
//  333  * VLPR -> VLLS0
//  334  *
//  335  * NOTE: VLLSx modes will always exit to RUN mode even if you were 
//  336  * in VLPR mode before entering VLLSx.
//  337  *
//  338  * Wakeup from VLLSx mode is controlled by the LLWU module. Most
//  339  * modules cannot issue a wakeup interrupt in VLLSx mode, so make
//  340  * sure to setup the desired wakeup sources in the LLWU before 
//  341  * calling this function.
//  342  *
//  343  * Parameters:
//  344  * none  
//  345  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  346 void enter_vlls0(void)
//  347 {
enter_vlls0:
        PUSH     {R7,LR}
//  348     /* Write to PMPROT to allow all possible power modes */
//  349     /* Set the VLLSM field to 0b100 for VLLS1 mode - Need to retain state of LPWUI bit 8 */
//  350     SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  351                   SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x4
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  352 
//  353     SMC_VLLSCTRL =  SMC_VLLSCTRL_VLLSM(0) ;    // set PORPO = 0b00
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        MOVS     R1,#+0
        STRB     R1,[R0, #+0]
//  354      /* Now execute the stop instruction to go into VLLS1 */
//  355     printf("[enter_vlls0]SMC_PMPROT   = %#02X \r\n", (SMC_PMPROT))  ;
        LDR.N    R0,??DataTable11_3  ;; 0x4007e000
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_10
        BL       printf
//  356     printf("[enter_vlls0]SMC_PMCTRL   = %#02X \r\n", (SMC_PMCTRL))  ;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_11
        BL       printf
//  357     printf("[enter_vlls0]SMC_VLLSCTRL   = %#02X \r\n", (SMC_VLLSCTRL))  ;
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_12
        BL       printf
//  358     printf("[enter_vlls0]SMC_PMSTAT   = %#02X \r\n", (SMC_PMSTAT))  ;
        LDR.N    R0,??DataTable11_1  ;; 0x4007e003
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_13
        BL       printf
//  359     printf("\n                                        ");
        LDR.N    R0,??DataTable11_14
        BL       printf
//  360     stop();
        BL       stop
//  361 }
        POP      {R0,PC}          ;; return
//  362 /********************************************************************/
//  363 /* VLLS0 mode entry routine. Puts the processor into VLLS0 mode from
//  364  * normal run mode or VLPR with the POR circuit disabled
//  365  *
//  366  * Mode transitions:
//  367  * RUN -> VLLS0
//  368  * VLPR -> VLLS0
//  369  *
//  370  * NOTE: VLLSx modes will always exit to RUN mode even if you were 
//  371  * in VLPR mode before entering VLLSx.
//  372  *
//  373  * Wakeup from VLLSx mode is controlled by the LLWU module. Most
//  374  * modules cannot issue a wakeup interrupt in VLLSx mode, so make
//  375  * sure to setup the desired wakeup sources in the LLWU before 
//  376  * calling this function.
//  377  *
//  378  * Parameters:
//  379  * none  
//  380  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  381 void enter_vlls0_nopor(void)
//  382 {
enter_vlls0_nopor:
        PUSH     {R7,LR}
//  383     /* Write to PMPROT to allow all possible power modes */
//  384     /* Set the VLLSM field to 0b100 for VLLS1 mode - Need to retain state of LPWUI bit 8 */
//  385     SMC_PMCTRL = (SMC_PMCTRL & (SMC_PMCTRL_RUNM_MASK |SMC_PMCTRL_LPWUI_MASK)) |
//  386                   SMC_PMCTRL_STOPM(0x4) ; // retain LPWUI
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0xE0
        ORRS     R0,R0,#0x4
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  387 
//  388     SMC_VLLSCTRL =  SMC_VLLSCTRL_VLLSM(0) | SMC_VLLSCTRL_PORPO_MASK;    // set PORPO = 0b01
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        MOVS     R1,#+32
        STRB     R1,[R0, #+0]
//  389      /* Now execute the stop instruction to go into VLLS1 */
//  390     printf("[enter_vlls0_nopor]SMC_PMPROT   = %#02X \r\n", (SMC_PMPROT))  ;
        LDR.N    R0,??DataTable11_3  ;; 0x4007e000
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_15
        BL       printf
//  391     printf("[enter_vlls0_nopor]SMC_PMCTRL   = %#02X \r\n", (SMC_PMCTRL))  ;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_16
        BL       printf
//  392     printf("[enter_vlls0_nopor]SMC_VLLSCTRL   = %#02X \r\n", (SMC_VLLSCTRL))  ;
        LDR.N    R0,??DataTable11_9  ;; 0x4007e002
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_17
        BL       printf
//  393     printf("[enter_vlls0_nopor]SMC_PMSTAT   = %#02X \r\n", (SMC_PMSTAT))  ;
        LDR.N    R0,??DataTable11_1  ;; 0x4007e003
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_18
        BL       printf
//  394     printf("\n                                        ");
        LDR.N    R0,??DataTable11_14
        BL       printf
//  395     stop();
        BL       stop
//  396 }
        POP      {R0,PC}          ;; return
//  397 /********************************************************************/
//  398 /* Enable low power wake up on interrupt. This function can be used
//  399  * to set the LPWUI bit. When this bit is set VLPx modes will exit
//  400  * to normal run mode. When this bit is cleared VLPx modes will exit
//  401  * to VLPR mode.
//  402  *
//  403  * The disable_lpwui() function can be used to clear the LPWUI bit.
//  404  *
//  405  * Parameters:
//  406  * none
//  407  */
//  408 
//  409    
//  410 

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  411 void enable_lpwui(void)
//  412 {
enable_lpwui:
        PUSH     {R7,LR}
//  413     SMC_PMCTRL |= SMC_PMCTRL_LPWUI_MASK;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ORRS     R0,R0,#0x80
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  414     printf("[enable_lpwui]SMC_PMCTRL   = %#02X \r\n", (SMC_PMCTRL))  ;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_19
        BL       printf
//  415 }
        POP      {R0,PC}          ;; return
//  416 /********************************************************************/
//  417 /* Disable low power wake up on interrupt. This function can be used
//  418  * to clear the LPWUI bit. When this bit is set VLPx modes will exit
//  419  * to normal run mode. When this bit is cleared VLPx modes will exit
//  420  * to VLPR mode.
//  421  *
//  422  * The enable_lpwui() function can be used to set the LPWUI bit.
//  423  *
//  424  * Parameters:
//  425  * none
//  426  */

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  427 void disable_lpwui(void)
//  428 {
disable_lpwui:
        PUSH     {R7,LR}
//  429     SMC_PMCTRL &= ~SMC_PMCTRL_LPWUI_MASK;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R0,[R0, #+0]
        ANDS     R0,R0,#0x7F
        LDR.N    R1,??DataTable11  ;; 0x4007e001
        STRB     R0,[R1, #+0]
//  430     printf("[disable_lpwui]SMC_PMCTRL   = %#02X \r\n", (SMC_PMCTRL))  ;
        LDR.N    R0,??DataTable11  ;; 0x4007e001
        LDRB     R1,[R0, #+0]
        UXTB     R1,R1            ;; ZeroExt  R1,R1,#+24,#+24
        LDR.N    R0,??DataTable11_20
        BL       printf
//  431 }
        POP      {R0,PC}          ;; return

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11:
        DC32     0x4007e001

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_1:
        DC32     0x4007e003

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_2:
        DC32     `?<Constant " \\n[enter_vlpr] Alread...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_3:
        DC32     0x4007e000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_4:
        DC32     `?<Constant " \\n[enter_vlpr] Waitin...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_5:
        DC32     0x4007d002

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_6:
        DC32     `?<Constant "[enter_vlpr] Now in V...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_7:
        DC32     `?<Constant " \\n[enter_vlpr] HALT P...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_8:
        DC32     `?<Constant " \\n[exit_vlpr] Waiting...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_9:
        DC32     0x4007e002

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_10:
        DC32     `?<Constant "[enter_vlls0]SMC_PMPR...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_11:
        DC32     `?<Constant "[enter_vlls0]SMC_PMCT...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_12:
        DC32     `?<Constant "[enter_vlls0]SMC_VLLS...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_13:
        DC32     `?<Constant "[enter_vlls0]SMC_PMST...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_14:
        DC32     `?<Constant "\\n                    ...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_15:
        DC32     `?<Constant "[enter_vlls0_nopor]SM...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_16:
        DC32     `?<Constant "[enter_vlls0_nopor]SM...">_1`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_17:
        DC32     `?<Constant "[enter_vlls0_nopor]SM...">_2`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_18:
        DC32     `?<Constant "[enter_vlls0_nopor]SM...">_3`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_19:
        DC32     `?<Constant "[enable_lpwui]SMC_PMC...">`

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable11_20:
        DC32     `?<Constant "[disable_lpwui]SMC_PM...">`

        SECTION `.iar_vfe_header`:DATA:REORDER:NOALLOC:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
        DC32 0

        SECTION __DLIB_PERTHREAD:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        SECTION __DLIB_PERTHREAD_init:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant " \\n[enter_vlpr] Alread...">`:
        DATA
        DC8 " \012[enter_vlpr] Already in VLPR Mode ! "
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant " \\n[enter_vlpr] Waitin...">`:
        DATA
        DC8 " \012[enter_vlpr] Waiting on REGONS to clear ! "
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlpr] Now in V...">`:
        DATA
        DC8 "[enter_vlpr] Now in VLPR at 19200 baud  \015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant " \\n[enter_vlpr] HALT P...">`:
        DATA
        DC8 20H, 0AH, 5BH, 65H, 6EH, 74H, 65H, 72H
        DC8 5FH, 76H, 6CH, 70H, 72H, 5DH, 20H, 48H
        DC8 41H, 4CH, 54H, 20H, 50H, 4DH, 53H, 54H
        DC8 41H, 54H, 20H, 64H, 6FH, 65H, 73H, 20H
        DC8 6EH, 6FH, 74H, 20H, 69H, 6EH, 64H, 69H
        DC8 63H, 61H, 74H, 65H, 20H, 69H, 6EH, 20H
        DC8 56H, 4CH, 50H, 52H, 20H, 4DH, 6FH, 64H
        DC8 65H, 20H, 21H, 20H, 0
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant " \\n[exit_vlpr] Waiting...">`:
        DATA
        DC8 20H, 0AH, 5BH, 65H, 78H, 69H, 74H, 5FH
        DC8 76H, 6CH, 70H, 72H, 5DH, 20H, 57H, 61H
        DC8 69H, 74H, 69H, 6EH, 67H, 20H, 6FH, 6EH
        DC8 20H, 52H, 45H, 47H, 4FH, 4EH, 53H, 20H
        DC8 62H, 69H, 74H, 20H, 74H, 6FH, 20H, 73H
        DC8 65H, 74H, 20H, 74H, 6FH, 20H, 69H, 6EH
        DC8 64H, 69H, 63H, 61H, 74H, 65H, 20H, 52H
        DC8 75H, 6EH, 20H, 72H, 65H, 67H, 75H, 6CH
        DC8 61H, 74H, 69H, 6FH, 6EH, 20H, 6DH, 6FH
        DC8 64H, 65H, 20H, 21H, 20H, 0
        DC8 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0]SMC_PMPR...">`:
        DATA
        DC8 "[enter_vlls0]SMC_PMPROT   = %#02X \015\012"
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0]SMC_PMCT...">`:
        DATA
        DC8 "[enter_vlls0]SMC_PMCTRL   = %#02X \015\012"
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0]SMC_VLLS...">`:
        DATA
        DC8 "[enter_vlls0]SMC_VLLSCTRL   = %#02X \015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0]SMC_PMST...">`:
        DATA
        DC8 "[enter_vlls0]SMC_PMSTAT   = %#02X \015\012"
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "\\n                    ...">`:
        DATA
        DC8 "\012                                        "
        DC8 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0_nopor]SM...">`:
        DATA
        DC8 "[enter_vlls0_nopor]SMC_PMPROT   = %#02X \015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0_nopor]SM...">_1`:
        DATA
        DC8 "[enter_vlls0_nopor]SMC_PMCTRL   = %#02X \015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0_nopor]SM...">_2`:
        DATA
        DC8 "[enter_vlls0_nopor]SMC_VLLSCTRL   = %#02X \015\012"
        DC8 0, 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enter_vlls0_nopor]SM...">_3`:
        DATA
        DC8 "[enter_vlls0_nopor]SMC_PMSTAT   = %#02X \015\012"
        DC8 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[enable_lpwui]SMC_PMC...">`:
        DATA
        DC8 "[enable_lpwui]SMC_PMCTRL   = %#02X \015\012"
        DC8 0, 0

        SECTION `.rodata`:CONST:REORDER:NOROOT(2)
`?<Constant "[disable_lpwui]SMC_PM...">`:
        DATA
        DC8 "[disable_lpwui]SMC_PMCTRL   = %#02X \015\012"
        DC8 0

        END
//  432 
//  433 /********************************************************************/
// 
// 740 bytes in section .rodata
// 650 bytes in section .text
// 
// 650 bytes of CODE  memory
// 740 bytes of CONST memory
//
//Errors: none
//Warnings: none
