///////////////////////////////////////////////////////////////////////////////
//                                                                            /
// IAR ANSI C/C++ Compiler V6.30.1.53127/W32 for ARM    08/Mar/2012  18:18:24 /
// Copyright 1999-2011 IAR Systems AB.                                        /
//                                                                            /
//    Cpu mode     =  thumb                                                   /
//    Endian       =  little                                                  /
//    Source file  =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\src\cpu\sysinit.c                                    /
//    Command line =  "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\src\cpu\sysinit.c" -D IAR -D TOWER -D TWR_K20D50M   /
//                    -lCN "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" -lB         /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\" /
//                     -o "D:\Profiles\b01252\My                              /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\FLASH_128KB_PFLASH\Obj\" --no_cse     /
//                    --no_unroll --no_inline --no_code_motion --no_tbaa      /
//                    --no_clustering --no_scheduling --debug                 /
//                    --endian=little --cpu=Cortex-M4 -e --fpu=None           /
//                    --dlib_config "C:\Program Files\IAR Systems\Embedded    /
//                    Workbench 6.0_5\arm\INC\c\DLib_Config_Normal.h" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\common\" -I  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\" -I     /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\cpu\headers\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\uart\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\mcg\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\wdog\" -I        /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\drivers\rcm\ /
//                    " -I "D:\Profiles\b01252\My                             /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\drivers\lptmr\" -I       /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\platforms\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\" -I                /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\projects\TWR /
//                    K20D50M_Demo\" -I "D:\Profiles\b01252\My                /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \dma\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc16\" -I "D:\Profiles\b01252\My                      /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \i2c\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \tsi\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \adc_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \angle_calculation\" -I "D:\Profiles\b01252\My          /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \buzzer\" -I "D:\Profiles\b01252\My                     /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \fft_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \irda_test\" -I "D:\Profiles\b01252\My                  /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \cmt_test\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \protocol\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \task_mgr\" -I "D:\Profiles\b01252\My                   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \TWRK20_specific\" -I "D:\Profiles\b01252\My            /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\projects\TWRK20D50M_Demo /
//                    \rtc\" -I "D:\Profiles\b01252\My                        /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Lib\interm /
//                    ediateFiles\" -I "D:\Profiles\b01252\My                 /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Lib\Include\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \DeviceSupport\ARM\ARMCM4\" -I "D:\Profiles\b01252\My   /
//                    Documents\Freescale\P0\software\sample code             /
//                    cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\build\ia /
//                    r\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4\CoreSupport\"  /
//                    -I "D:\Profiles\b01252\My Documents\Freescale\P0\softwa /
//                    re\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50 /
//                    MHz_sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\CM4 /
//                    \CoreSupportLiker Options-Library\" -I                  /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\src\CMSIS\DSP_Li /
//                    b\Lib\intermediateFiles\arm_cortexM4_math.lib\" -I      /
//                    "D:\Profiles\b01252\My Documents\Freescale\P0\software\ /
//                    sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz /
//                    _sc\build\iar\TWRK20D50M_Demo\..\..\..\build\" -Ol      /
//                    --use_c++_inline -I "C:\Program Files\IAR               /
//                    Systems\Embedded Workbench 6.0_5\arm\CMSIS\Include\"    /
//                    -D ARM_MATH_CM4                                         /
//    List file    =  D:\Profiles\b01252\My Documents\Freescale\P0\software\s /
//                    ample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_ /
//                    sc\build\iar\TWRK20D50M_Demo\FLASH_128KB_PFLASH\List\sy /
//                    sinit.s                                                 /
//                                                                            /
//                                                                            /
///////////////////////////////////////////////////////////////////////////////

        NAME sysinit

        #define SHT_PROGBITS 0x1

        EXTERN pll_init
        EXTERN uart_init

        PUBLIC core_clk_khz
        PUBLIC core_clk_mhz
        PUBLIC fb_clk_init
        PUBLIC mcg_clk_hz
        PUBLIC mcg_clk_khz
        PUBLIC periph_clk_khz
        PUBLIC pll_clk_khz
        PUBLIC sysinit
        PUBLIC trace_clk_init

// D:\Profiles\b01252\My Documents\Freescale\P0\software\sample code cesar\TWR-K20D50M_LABS_AND_CE\kinetis_50MHz_sc\src\cpu\sysinit.c
//    1 /*
//    2  * File:        sysinit.c
//    3  * Purpose:     Kinetis Configuration
//    4  *              Initializes processor to a default state
//    5  *
//    6  * Notes:
//    7  *
//    8  */
//    9 
//   10 #include "common.h"
//   11 #include "sysinit.h"
//   12 #include "uart.h"
//   13 #include "mcg.h"
//   14 
//   15 /********************************************************************/
//   16 /* Actual system clock frequency */

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   17 int mcg_clk_hz;
mcg_clk_hz:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   18 int mcg_clk_khz;
mcg_clk_khz:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   19 int core_clk_khz;
core_clk_khz:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   20 int periph_clk_khz;
periph_clk_khz:
        DS8 4

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   21 int pll_clk_khz;
pll_clk_khz:
        DS8 4
//   22 

        SECTION `.bss`:DATA:REORDER:NOROOT(2)
//   23 int core_clk_mhz;
core_clk_mhz:
        DS8 4
//   24 
//   25 /********************************************************************/

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//   26 void sysinit (void)
//   27 {
sysinit:
        PUSH     {LR}
        SUB      SP,SP,#+12
//   28         /*
//   29          * Enable all of the port clocks. These have to be enabled to configure
//   30          * pin muxing options, so most code will need all of these on anyway.
//   31          */
//   32         SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
//   33                       | SIM_SCGC5_PORTB_MASK
//   34                       | SIM_SCGC5_PORTC_MASK
//   35                       | SIM_SCGC5_PORTD_MASK
//   36                       | SIM_SCGC5_PORTE_MASK );
        LDR.N    R0,??DataTable2  ;; 0x40048038
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x3E00
        LDR.N    R1,??DataTable2  ;; 0x40048038
        STR      R0,[R1, #+0]
//   37         
//   38             // releases hold with ACKISO:  Only has an effect if recovering from VLLS1, VLLS2, or VLLS3
//   39     // if ACKISO is set you must clear ackiso before calling pll_init 
//   40     //    or pll init hangs waiting for OSC to initialize
//   41     // if osc enabled in low power modes - enable it first before ack
//   42     // if I/O needs to be maintained without glitches enable outputs and modules first before ack.
//   43 //LP 10/25 #ifdef MCU_MK20DZ50        
//   44 #ifdef MCU_MK20DZ50 
//   45        // printf(" PMC_REGSC = %x", PMC_REGSC);
//   46     if (PMC_REGSC &  PMC_REGSC_ACKISO_MASK)
        LDR.N    R0,??DataTable2_1  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        LSLS     R0,R0,#+28
        BPL.N    ??sysinit_0
//   47         PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
        LDR.N    R0,??DataTable2_1  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        ORRS     R0,R0,#0x8
        LDR.N    R1,??DataTable2_1  ;; 0x4007d002
        STRB     R0,[R1, #+0]
//   48 #endif
//   49     
//   50         
//   51 #if defined(NO_PLL_INIT)
//   52     // ON REV 1.0 THE SLOW IRC IS NON-FUNCTIONAL AT < 2.05V. THE DEFAULT FREQUENCY WILL VARY FROM PART TO PART IN FEI MODE
//   53           mcg_clk_hz = 21000000; //FEI mode
//   54 #else 
//   55        /* Ramp up the system clock */
//   56        /* Set the system dividers */
//   57        /* NOTE: The PLL init will not configure the system clock dividers,
//   58         * so they must be configured appropriately before calling the PLL
//   59         * init function to ensure that clocks remain in valid ranges.
//   60         */  
//   61         SIM_CLKDIV1 = ( 0
//   62                         | SIM_CLKDIV1_OUTDIV1(0)
//   63                         | SIM_CLKDIV1_OUTDIV2(0)
//   64                         | SIM_CLKDIV1_OUTDIV4(1) );
??sysinit_0:
        LDR.N    R0,??DataTable2_2  ;; 0x40048044
        MOVS     R1,#+65536
        STR      R1,[R0, #+0]
//   65     // releases hold with ACKISO:  Only has an effect if recovering from VLLS1, VLLS2, or VLLS3
//   66     // if ACKISO is set you must clear ackiso before calling pll_init 
//   67     //    or pll init hangs waiting for OSC to initialize
//   68     // if osc enabled in low power modes - enable it first before ack
//   69     // if I/O needs to be maintained without glitches enable outputs and modules first before ack.
//   70     if (PMC_REGSC &  PMC_REGSC_ACKISO_MASK)
        LDR.N    R0,??DataTable2_1  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        LSLS     R0,R0,#+28
        BPL.N    ??sysinit_1
//   71         PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
        LDR.N    R0,??DataTable2_1  ;; 0x4007d002
        LDRB     R0,[R0, #+0]
        ORRS     R0,R0,#0x8
        LDR.N    R1,??DataTable2_1  ;; 0x4007d002
        STRB     R0,[R1, #+0]
//   72 
//   73        /* Initialize PLL */
//   74        /* PLL will be the source for MCG CLKOUT so the core, system, and flash clocks are derived from it */ 
//   75        mcg_clk_hz = pll_init(CLK0_FREQ_HZ,  /* CLKIN0 frequency */
//   76                              LOW_POWER,     /* Set the oscillator for low power mode */
//   77                              CLK0_TYPE,     /* Crystal or canned oscillator clock input */
//   78                              PLL0_PRDIV,    /* PLL predivider value */
//   79                              PLL0_VDIV,     /* PLL multiplier */
//   80                              MCGOUT);       /* Use the output from this PLL as the MCGOUT */
??sysinit_1:
        MOVS     R0,#+1
        STR      R0,[SP, #+4]
        MOVS     R0,#+25
        STR      R0,[SP, #+0]
        MOVS     R3,#+4
        MOVS     R2,#+1
        MOVS     R1,#+0
        LDR.N    R0,??DataTable2_3  ;; 0x7a1200
        BL       pll_init
        LDR.N    R1,??DataTable2_4
        STR      R0,[R1, #+0]
//   81 
//   82        /* Check the value returned from pll_init() to make sure there wasn't an error */
//   83        if (mcg_clk_hz < 0x100)
        LDR.N    R0,??DataTable2_4
        LDR      R0,[R0, #+0]
        CMP      R0,#+255
        BGT.N    ??sysinit_2
//   84          while(1);
??sysinit_3:
        B.N      ??sysinit_3
//   85 #endif
//   86 
//   87 	/*
//   88          * Use the value obtained from the pll_init function to define variables
//   89 	 * for the core clock in kHz and also the peripheral clock. These
//   90 	 * variables can be used by other functions that need awareness of the
//   91 	 * system frequency.
//   92 	 */
//   93         mcg_clk_khz = mcg_clk_hz / 1000;
??sysinit_2:
        LDR.N    R0,??DataTable2_4
        LDR      R0,[R0, #+0]
        MOV      R1,#+1000
        SDIV     R0,R0,R1
        LDR.N    R1,??DataTable2_5
        STR      R0,[R1, #+0]
//   94 	core_clk_khz = mcg_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> 28)+ 1);
        LDR.N    R0,??DataTable2_5
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable2_2  ;; 0x40048044
        LDR      R1,[R1, #+0]
        LSRS     R1,R1,#+28
        ADDS     R1,R1,#+1
        UDIV     R0,R0,R1
        LDR.N    R1,??DataTable2_6
        STR      R0,[R1, #+0]
//   95   	periph_clk_khz = mcg_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
        LDR.N    R0,??DataTable2_5
        LDR      R0,[R0, #+0]
        LDR.N    R1,??DataTable2_2  ;; 0x40048044
        LDR      R1,[R1, #+0]
        UBFX     R1,R1,#+24,#+4
        ADDS     R1,R1,#+1
        UDIV     R0,R0,R1
        LDR.N    R1,??DataTable2_7
        STR      R0,[R1, #+0]
//   96         
//   97   	/* For debugging purposes, enable the trace clock and/or FB_CLK so that
//   98   	 * we'll be able to monitor clocks and know the PLL is at the frequency
//   99   	 * that we expect.
//  100   	 */
//  101 	//trace_clk_init();
//  102 #ifndef NO_CLKOUT_SUPPORT
//  103   	/* Enable the pins for the clock out pins */
//  104 	trace_clk_init();
        BL       trace_clk_init
//  105   	fb_clk_init();
        BL       fb_clk_init
//  106 #endif
//  107         
//  108 #ifndef CONSOLE_SUPPORT
//  109   	/* Enable the pins for the selected UART */
//  110          if (TERM_PORT == UART0_BASE_PTR)
//  111          {
//  112 #ifdef TWR_K20DX256
//  113            /* Enable the UART0_TXD function on PTB17 */
//  114             PORTB_PCR17 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
//  115 
//  116             /* Enable the UART0_RXD function on PTB16 */
//  117             PORTB_PCR16 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin    
//  118 #elif 0//P0_DC_64LQFP
//  119            /* Enable the UART0_TXD function on PTA2*/
//  120             PORTA_PCR2 = PORT_PCR_MUX(0x2); // UART is alt2 function for this pin
//  121 
//  122             /* Enable the UART0_RXD function on PTA1 */
//  123             PORTA_PCR1 = PORT_PCR_MUX(0x2); // UART is alt2 function for this pin            
//  124 #else
//  125             /* Enable the UART0_TXD function on PTD6 */
//  126             PORTD_PCR6 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
//  127 
//  128             /* Enable the UART0_RXD function on PTD7 */
//  129             PORTD_PCR7 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
//  130 #endif
//  131          }
//  132 
//  133          if (TERM_PORT == UART1_BASE_PTR)
//  134   	 {
//  135            /* Enable the UART0_TXD function on PTE0 (1) */
//  136             PORTE_PCR0 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
        LDR.N    R0,??DataTable2_8  ;; 0x4004d000
        MOV      R1,#+768
        STR      R1,[R0, #+0]
//  137 
//  138             /* Enable the UART0_RXD function on PTE1 (2) */
//  139             PORTE_PCR1 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin   
        LDR.N    R0,??DataTable2_9  ;; 0x4004d004
        MOV      R1,#+768
        STR      R1,[R0, #+0]
//  140   	}
//  141 
//  142   	if (TERM_PORT == UART2_BASE_PTR)
//  143   	{
//  144                  /* Enable the UART2_TXD function on PTD3 */
//  145   		PORTD_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
//  146 
//  147   		/* Enable the UART2_RXD function on PTD2 */
//  148   		PORTD_PCR2 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
//  149   	}
//  150         
//  151   	/* UART0 and UART1 are clocked from the core clock, but all other UARTs are
//  152          * clocked from the peripheral clock. So we have to determine which clock
//  153          * to send to the uart_init function.
//  154          */
//  155         if ((TERM_PORT == UART0_BASE_PTR) | (TERM_PORT == UART1_BASE_PTR))
//  156             uart_init (TERM_PORT, core_clk_khz, TERMINAL_BAUD);
        MOVS     R2,#+115200
        LDR.N    R0,??DataTable2_6
        LDR      R1,[R0, #+0]
        LDR.N    R0,??DataTable2_10  ;; 0x4006b000
        BL       uart_init
//  157         else
//  158   	    uart_init (TERM_PORT, periph_clk_khz, TERMINAL_BAUD);
//  159 #endif
//  160 }
        POP      {R0-R2,PC}       ;; return
//  161 /********************************************************************/

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  162 void trace_clk_init(void)
//  163 {
//  164 	/* Set the trace clock to the core clock frequency */
//  165 	SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;
trace_clk_init:
        LDR.N    R0,??DataTable2_11  ;; 0x40048004
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x1000
        LDR.N    R1,??DataTable2_11  ;; 0x40048004
        STR      R0,[R1, #+0]
//  166 
//  167 	/* Enable the TRACE_CLKOUT pin function on PTA6 (alt7 function) */
//  168 	PORTA_PCR6 = ( PORT_PCR_MUX(0x7));
        LDR.N    R0,??DataTable2_12  ;; 0x40049018
        MOV      R1,#+1792
        STR      R1,[R0, #+0]
//  169 }
        BX       LR               ;; return
//  170 /********************************************************************/

        SECTION `.text`:CODE:NOROOT(1)
        THUMB
//  171 void fb_clk_init(void)
//  172 {
//  173  	/* Enable the FB_CLKOUT function on PTC3 (alt5 function) */
//  174         SIM_SOPT2 &= ~SIM_SOPT2_CLKOUTSEL_MASK; // clear clkoout field
fb_clk_init:
        LDR.N    R0,??DataTable2_11  ;; 0x40048004
        LDR      R0,[R0, #+0]
        BICS     R0,R0,#0xE0
        LDR.N    R1,??DataTable2_11  ;; 0x40048004
        STR      R0,[R1, #+0]
//  175         SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(2);    // select flash clock
        LDR.N    R0,??DataTable2_11  ;; 0x40048004
        LDR      R0,[R0, #+0]
        ORRS     R0,R0,#0x40
        LDR.N    R1,??DataTable2_11  ;; 0x40048004
        STR      R0,[R1, #+0]
//  176 	PORTC_PCR3 = ( PORT_PCR_MUX(0x5) | PORT_PCR_DSE_MASK );
        LDR.N    R0,??DataTable2_13  ;; 0x4004b00c
        MOV      R1,#+1344
        STR      R1,[R0, #+0]
//  177 }
        BX       LR               ;; return

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2:
        DC32     0x40048038

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_1:
        DC32     0x4007d002

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_2:
        DC32     0x40048044

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_3:
        DC32     0x7a1200

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_4:
        DC32     mcg_clk_hz

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_5:
        DC32     mcg_clk_khz

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_6:
        DC32     core_clk_khz

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_7:
        DC32     periph_clk_khz

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_8:
        DC32     0x4004d000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_9:
        DC32     0x4004d004

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_10:
        DC32     0x4006b000

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_11:
        DC32     0x40048004

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_12:
        DC32     0x40049018

        SECTION `.text`:CODE:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
??DataTable2_13:
        DC32     0x4004b00c

        SECTION `.iar_vfe_header`:DATA:REORDER:NOALLOC:NOROOT(2)
        SECTION_TYPE SHT_PROGBITS, 0
        DATA
        DC32 0

        SECTION __DLIB_PERTHREAD:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        SECTION __DLIB_PERTHREAD_init:DATA:REORDER:NOROOT(0)
        SECTION_TYPE SHT_PROGBITS, 0

        END
//  178 /********************************************************************/
// 
//  24 bytes in section .bss
// 308 bytes in section .text
// 
// 308 bytes of CODE memory
//  24 bytes of DATA memory
//
//Errors: none
//Warnings: none
