/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : FC1.c
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : Init_CAN
**     Version     : Component 01.006, Driver 01.06, CPU db: 3.50.001
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-07-05, 11:45, # CodeGen: 23
**     Abstract    :
**          This file implements the CAN (CAN) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
**     Settings    :
**          Component name                                 : FC1
**          Device                                         : CAN
**          Settings                                       : 
**            Clock settings                               : 
**              Clock divisor select value                 : 30
**              Phase segment 1                            : 4
**              Phase segment 2                            : 2
**              Propagation segment                        : 1
**              CAN clock source                           : Internal bus clock
**              CAN frequency                              : 0.4032 MHz
**              Resync jump width                          : 1
**              Free-running timer                         : 0
**            Timer synchronize mode                       : Enabled
**            Lowest buffer transmitted first              : Lowest number buffer is transmitted first
**            Freeze mode                                  : Enabled
**            Samples per bit                              : Three samples
**            Bus off recovery mode                        : Disabled
**            Loop back mode                               : Enabled
**            Listen only mode                             : Disabled
**            Abort                                        : Disabled
**            Wake-up                                      : Disabled
**            Wake-up source filtered                      : no
**            Rx FIFO                                      : Disabled
**            Supervisor mode                              : yes
**            Doze mode                                    : no
**            Write-Access to memory in Freeze mode        : Enabled
**            Self reception disable                       : no
**            Local priority                               : Disabled
**            ID Acceptance Mode                           : Format A
**            Mailboxes reception priority                 : from Mailboxes to Rx FIFO
**            Remote Request Storing                       : Disabled
**            Entire Frame Arbitration Field Comparison for Rx Mailboxes : Disabled
**            Tx Arbitration Start Delay                   : 9
**            Number of the Last Message Buffer            : 15
**            Individual Rx Masking and Queue              : Disabled
**            Rx FIFO global data mask                     : FFFFFFFF
**            Rx Individual MB data mask                   : 
**              Mailbox 0 data mask                        : FFFFFFFF
**              Mailbox 1 data mask                        : FFFFFFFF
**              Mailbox 2 data mask                        : FFFFFFFF
**              Mailbox 3 data mask                        : FFFFFFFF
**              Mailbox 4 data mask                        : FFFFFFFF
**              Mailbox 5 data mask                        : FFFFFFFF
**              Mailbox 6 data mask                        : FFFFFFFF
**              Mailbox 7 data mask                        : FFFFFFFF
**              Mailbox 8 data mask                        : FFFFFFFF
**              Mailbox 9 data mask                        : FFFFFFFF
**              Mailbox 10 data mask                       : FFFFFFFF
**              Mailbox 11 data mask                       : FFFFFFFF
**              Mailbox 12 data mask                       : FFFFFFFF
**              Mailbox 13 data mask                       : FFFFFFFF
**              Mailbox 14 data mask                       : FFFFFFFF
**              Mailbox 15 data mask                       : FFFFFFFF
**            Global data mask                             : 00000000
**            Data buffer 14 mask                          : FFFFFFFF
**            Data buffer 15 mask                          : FFFFFFFF
**            Number of Rx FIFO filters                    : 8
**          Pins                                           : 
**            Receiver pin                                 : 
**              Pin                                        : GPIOC12/CANRX/SDA1/RXD1
**              Pin signal                                 : 
**            Transmitter pin                              : 
**              Pin                                        : GPIOC11/CANTX/SCL1/TXD1
**              Pin signal                                 : 
**          Interrupts                                     : 
**            MB logical OR interrupt                      : 
**              Interrupt                                  : INT_MB_OR
**              Interrupt priority                         : maximal priority
**              ISR name                                   : CAN_MB_or_ISR
**              Message buffer 0 interrupt                 : Enabled
**              Message buffer 1 interrupt                 : Enabled
**              Message buffer 2 interrupt                 : Disabled
**              Message buffer 3 interrupt                 : Disabled
**              Message buffer 4 interrupt                 : Disabled
**              Message buffer 5 interrupt                 : Disabled
**              Message buffer 6 interrupt                 : Disabled
**              Message buffer 7 interrupt                 : Disabled
**              Message buffer 8 interrupt                 : Disabled
**              Message buffer 9 interrupt                 : Disabled
**              Message buffer 10 interrupt                : Disabled
**              Message buffer 11 interrupt                : Disabled
**              Message buffer 12 interrupt                : Disabled
**              Message buffer 13 interrupt                : Disabled
**              Message buffer 14 interrupt                : Disabled
**              Message buffer 15 interrupt                : Disabled
**            Bus-off interrupt                            : 
**              Interrupt                                  : INT_BUS_OFF
**              Interrupt priority                         : minimal priority
**              ISR name                                   : BusOff_ISR
**              Bus-off interrupt                          : Disabled
**            Error interrupt                              : 
**              Interrupt                                  : INT_ERROR
**              Interrupt priority                         : minimal priority
**              ISR name                                   : Error_ISR
**              Error interrupt                            : Disabled
**            Warning interrupt                            : Disabled
**            Wakeup interrupt                             : 
**              Interrupt                                  : INT_WAKEUP
**              Interrupt priority                         : default
**              ISR name                                   : 
**              Wakeup interrupt                           : Disabled
**          Initialization                                 : 
**            Peripheral clock enable                      : Enabled
**            Module enable                                : yes
**            Keep in Freeze/Halt                          : no
**            Call Init method                             : yes
**     Contents    :
**         Init - void FC1_Init(void);
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

/* MODULE FC1. */

#include "FC1.h"
  /* Including shared modules, which are used in the whole project */
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
#include "Cpu.h"


/*
** ===================================================================
**     Method      :  FC1_Init (component Init_CAN)
**
**     Description :
**         This method initializes registers of the CAN module
**         according to the Peripheral Initialization settings.
**         Call this method in user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void FC1_Init(void)
{
  /* CAN_MCR: MDIS=1 */
  setReg32Bits(CAN_MCR, 0x80000000UL);  
  /* CAN_TIMER: TIMER=0 */
  clrReg32Bits(CAN_TIMER, 0xFFFFUL);    
  /* CAN_CTRL1: CLKSRC=1 */
  setReg32Bits(CAN_CTRL1, 0x2000UL);    
  /* CAN_MCR: MDIS=0,SOFTRST=1 */
  clrSetReg32Bits(CAN_MCR, 0x80000000UL, 0x02000000UL); 
  while(!(CAN_MCR & CAN_MCR_FRZACK_MASK)){} /* Wait for entering the freeze mode */
  /* CAN_MCR: RFEN=0,SUPV=1,SLFWAK=0,WAKSRC=0,DOZE=0,SRXDIS=0,IRMQ=0,LPRIOEN=0,AEN=0,IDAM=0 */
  clrSetReg32Bits(CAN_MCR, 0x204F3300UL, 0x00800000UL); 
  /* CAN_CTRL1: PRESDIV=0x1E,RJW=0,PSEG1=3,PSEG2=1,LPB=1,SMP=1,BOFFREC=1,TSYN=1,LBUF=1,LOM=0,PROPSEG=0 */
  clrSetReg32Bits(CAN_CTRL1, 0xE1E6000FUL, 0x1E1910F0UL); 
  /* CAN_CTRL2: ??=0,WRMFRZ=1,RFFN=0,TASD=9,MRP=1,RRS=0,EACEN=0 */
  clrSetReg32Bits(CAN_CTRL2, 0x8FB30000UL, 0x104C0000UL); 
  /* CAN_RXMGMASK: MG=0 */
  setReg32(CAN_RXMGMASK, 0x00UL);       
  /* CAN_RX14MASK: RX14M=0xFFFFFFFF */
  setReg32(CAN_RX14MASK, 0xFFFFFFFFUL); 
  /* CAN_RX15MASK: RX15M=0xFFFFFFFF */
  setReg32(CAN_RX15MASK, 0xFFFFFFFFUL); 
  /* CAN_RXFGMASK: FGM=0xFFFFFFFF */
  setReg32(CAN_RXFGMASK, 0xFFFFFFFFUL); 
  /* CAN_RXIMR0: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR0, 0xFFFFFFFFUL);   
  /* CAN_RXIMR1: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR1, 0xFFFFFFFFUL);   
  /* CAN_RXIMR2: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR2, 0xFFFFFFFFUL);   
  /* CAN_RXIMR3: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR3, 0xFFFFFFFFUL);   
  /* CAN_RXIMR4: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR4, 0xFFFFFFFFUL);   
  /* CAN_RXIMR5: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR5, 0xFFFFFFFFUL);   
  /* CAN_RXIMR6: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR6, 0xFFFFFFFFUL);   
  /* CAN_RXIMR7: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR7, 0xFFFFFFFFUL);   
  /* CAN_RXIMR8: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR8, 0xFFFFFFFFUL);   
  /* CAN_RXIMR9: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR9, 0xFFFFFFFFUL);   
  /* CAN_RXIMR10: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR10, 0xFFFFFFFFUL);  
  /* CAN_RXIMR11: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR11, 0xFFFFFFFFUL);  
  /* CAN_RXIMR12: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR12, 0xFFFFFFFFUL);  
  /* CAN_RXIMR13: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR13, 0xFFFFFFFFUL);  
  /* CAN_RXIMR14: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR14, 0xFFFFFFFFUL);  
  /* CAN_RXIMR15: MI=0xFFFFFFFF */
  setReg32(CAN_RXIMR15, 0xFFFFFFFFUL);  
  /* CAN_ESR1: TWRNINT=1,RWRNINT=1,BOFFINT=1,ERRINT=1,WAKINT=1 */
  setReg32Bits(CAN_ESR1, 0x00030007UL); 
  /* CAN_IFLAG1: BUF31TO8I=0x00FFFFFF,BUF7I=1,BUF6I=1,BUF5I=1,BUF4TO0I=0x1F */
  setReg32(CAN_IFLAG1, 0xFFFFFFFFUL);   
  /* CAN_MCR: WAKMSK=0,WRNEN=0 */
  clrReg32Bits(CAN_MCR, 0x04200000UL);  
  /* CAN_CTRL1: BOFFMSK=0,ERRMSK=0 */
  clrReg32Bits(CAN_CTRL1, 0xC000UL);    
  /* CAN_IMASK1: BUFLM&=~0xFFFC,BUFLM|=3 */
  clrSetReg32Bits(CAN_IMASK1, 0xFFFCUL, 0x03UL); 
  /* CAN_MCR: MDIS=0,FRZ=1,HALT=0,MAXMB=0x0F */
  clrSetReg32Bits(CAN_MCR, 0x90000070UL, 0x4000000FUL); 
}

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      ProcessorExpert.c
**      Events.c
**
** ###################################################################
#if defined(CAN_MB_or_ISR_FAST_INT)
#pragma interrupt fast
#elif defined(CAN_MB_or_ISR_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt
#endif
void CAN_MB_or_ISR(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      ProcessorExpert.c
**      Events.c
**
** ###################################################################
#if defined(BusOff_ISR_FAST_INT)
#pragma interrupt fast
#elif defined(BusOff_ISR_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt
#endif
void BusOff_ISR(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      ProcessorExpert.c
**      Events.c
**
** ###################################################################
#if defined(Error_ISR_FAST_INT)
#pragma interrupt fast
#elif defined(Error_ISR_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt
#endif
void Error_ISR(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/


/* END FC1. */
/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
