/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : eFPWM1.c
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : Init_eFlexPWM
**     Version     : Component 01.000, Driver 01.00, CPU db: 3.50.001
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-07-05, 11:54, # CodeGen: 46
**     Abstract    :
**          This file implements the eFlexPWM (PWMA) module initialization
**          according to the Peripheral Initialization settings, and
**          defines interrupt service routines prototypes.
**     Settings    :
**          Component name                                 : eFPWM1
**          Device                                         : PWMA
**          Settings                                       : 
**            Submodule 0                                  : Enabled
**              Clock setting                              : 
**                PWM clock source                         : IP Bus clock
**                PWM generator clock                      : Enabled
**                PWM prescaler                            : 2
**                Module clock                             : 50.0000 MHz
**                Init counter value                       : 0
**                PWM value 0 - half cycle point           : 2000
**                PWM value 1 - counter modulo             : 3999
**                Fractional circuit power up              : Disabled
**                Fractional value 1 circuit               : Disabled
**                Fractional value 1                       : 0
**                Dead time value 0                        : 0
**                Dead time value 1                        : 0
**                PWM frequency                            : 12.5000 kHz
**                PWM period                               : 80.0000 us
**                PWM dead time 0                          : 0
**                PWM dead time 1                          : 0
**              Enabled in Wait mode                       : yes
**              Enabled in Debug mode                      : yes
**              Channel settings                           : 
**                Mode of PWM ch A and B                   : Complementary
**                Complementary PWM source                 : PWM23
**                Double switching                         : Disabled
**                Channel A (PWM23)                        : 
**                  PWM function                           : 
**                    PWM value 2                          : 2000
**                    Fractional value 2 and 3 circuit     : Disabled
**                    Fractional value 2                   : 0
**                    PWM value 3                          : 3999
**                    Fractional value 3                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Enabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select A                       : Raw PWMA input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel B (PWM45)                        : 
**                  PWM function                           : 
**                    PWM value 4                          : 0
**                    Fractional value 4 and 5 circuit     : Disabled
**                    Fractional value 4                   : 0
**                    PWM value 5                          : 0
**                    Fractional value 5                   : 0
**                    SW output                            : Logic 0
**                    Deadtime source                      : Generated PWM
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select B                       : Raw PWMB input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**                Channel X (PWM01)                        : 
**                  PWM function                           : 
**                    Output fault state                   : Forced to 0 prior to output polarity
**                    Output polarity                      : Not inverted
**                    Channel masked                       : no
**                    X Double switching                   : Disabled
**                    Channel output                       : Disabled
**                    Fault channel 0                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                    Fault channel 1                      : 
**                      Disable by fault 0                 : no
**                      Disable by fault 1                 : no
**                      Disable by fault 2                 : no
**                      Disable by fault 3                 : no
**                  E-capture function                     : 
**                    FIFOs water mark level               : 0
**                    Edge counter                         : Disabled
**                    Edge compare                         : 0
**                    Input select X                       : Raw PWMX input signal
**                    Capture 0 circuitry                  : Disabled
**                    Capture 1 circuitry                  : Disabled
**                    Capture circuitry mode               : Free running
**                    Input capture process                : Disabled
**              Output trigger settings                    : 
**                Output trigger 0 source select           : OUT_TRIG0 signal
**                Output trigger 1 source select           : OUT_TRIG1 signal
**                OUT_TRIG0 signal settings                : 
**                  Output trigger for Val 0               : Disabled
**                  Output trigger for Val 2               : Disabled
**                  Output trigger for Val 4               : Disabled
**                OUT_TRIG1 signal settings                : 
**                  Output trigger for Val 1               : Disabled
**                  Output trigger for Val 3               : Disabled
**                  Output trigger for Val 5               : Disabled
**              Reload settings                            : 
**                Reload source                            : Local reload signal
**                Reload frequency                         : 1
**                Half cycle reload                        : Disabled
**                Full cycle reload                        : Disabled
**                Load mode                                : Load at next PWM reload if LDOK is set
**              Force and initialization settings          : 
**                Initialization source                    : Local sync signal
**                Force initialization                     : Disabled
**                Force source                             : Local force signal
**                Init value ch A                          : Low
**                Init value ch B                          : Low
**                Init value ch X                          : Low
**            Submodule 1                                  : Disabled
**            Submodule 2                                  : Disabled
**            Submodule 3                                  : Disabled
**            Fault channel 0 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Disabled
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**            Fault channel 1 protection settings          : 
**              Common fault settings                      : 
**                Input filter                             : Disabled
**                Fault Glitch Stretch                     : Disabled
**              Fault 0                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 1                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 2                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**              Fault 3                                    : 
**                Fault active level                       : Logic 0
**                Fault clearing mode                      : Manual
**                Fault safety mode                        : Normal
**                Half cycle recovery                      : no
**                Full cycle recovery                      : no
**          Pins                                           : 
**            SM0 pins                                     : Enabled
**              PWM/Input capture channels                 : 
**                Channel A                                : Enabled
**                  PWM/Input capture pin A                : GPIOE1/PWMA_0A
**                  PWM/Input capture pin A signal         : 
**                Channel B                                : Disabled
**                Channel X                                : Disabled
**              External control A - EXTA                  : Disabled
**              External control B - EXTB                  : Enabled
**                External control B input                 : ADC12_CH0_High_and_low_limit
**                External control B input signal          : 
**              External synchronization                   : Disabled
**              Output trigger 0                           : Disabled
**              Output trigger 1                           : Disabled
**            SM1 pins                                     : Disabled
**            SM2 pins                                     : Disabled
**            SM3 pins                                     : Disabled
**            PWM Faults                                   : 
**              Fault channel 0                            : 
**                Fault 0                                  : Enabled
**                  Fault pin 0                            : GPIOC2/TXD0/TB0/XB_IN2/CLKO0
**                  Fault pin 0 signal                     : 
**                Fault 1                                  : Enabled
**                  Fault pin 1                            : GPIOD6/TXD2/XB_IN4/XB_OUT8
**                  Fault pin 1 signal                     : 
**                Fault 2                                  : Enabled
**                  Fault pin 2                            : GPIOD5/RXD2/XB_IN5/XB_OUT9
**                  Fault pin 2 signal                     : 
**                Fault 3                                  : Enabled
**                  Fault pin 3                            : GPIOC4/TA1/CMPB_O/XB_IN8/EWM_OUT_B
**                  Fault pin 3 signal                     : 
**              Fault channel 1                            : 
**                Fault 4                                  : Enabled
**                  Fault pin 4                            : GPIOG6/PWMA_FAULT4/PWMB_FAULT4/TB2/XB_OUT8
**                  Fault pin 4 signal                     : 
**                Fault 5                                  : Enabled
**                  Fault pin 5                            : GPIOG7/PWMA_FAULT5/PWMB_FAULT5/XB_OUT9
**                  Fault pin 5 signal                     : 
**                Fault 6                                  : Enabled
**                  Fault pin 6                            : GPIOF10/TXD2/PWMA_FAULT6/PWMB_FAULT6/XB_OUT10
**                  Fault pin 6 signal                     : 
**                Fault 7                                  : Enabled
**                  Fault pin 7                            : GPIOF9/RXD2/PWMA_FAULT7/PWMB_FAULT7/XB_OUT11
**                  Fault pin 7 signal                     : 
**            External clock                               : 
**              External clock                             : Disabled
**              External clock frequency                   : 1
**            External force                               : Disabled
**          Interrupts/DMA                                 : 
**            SM0 Interrupts/DMA                           : Enabled
**              Compare interrupt                          : 
**                Interrupt                                : INT_eFlexPWMA_CMP0
**                Interrupt priority                       : 0
**                ISR Name                                 : PWM_Compare
**                Compare interrupt 0                      : Disabled
**                Compare interrupt 1                      : Disabled
**                Compare interrupt 2                      : Disabled
**                Compare interrupt 3                      : Disabled
**                Compare interrupt 4                      : Disabled
**                Compare interrupt 5                      : Disabled
**              Capture interrupt                          : 
**                Interrupt                                : INT_eFlexPWMA_CAP
**                Interrupt priority                       : default
**                ISR Name                                 : 
**                Capture A 0 interrupt                    : Disabled
**                Capture A 1 interrupt                    : Disabled
**                Capture B 0 interrupt                    : Disabled
**                Capture B 1 interrupt                    : Disabled
**                Capture X 0 interrupt                    : Disabled
**                Capture X 1 interrupt                    : Disabled
**              Reload interrupt                           : 
**                Interrupt                                : INT_eFlexPWMA_RELOAD0
**                Interrupt priority                       : disabled
**                ISR Name                                 : 
**                Reload interrupt                         : Disabled
**              Reload error interrupt                     : 
**                Interrupt                                : INT_eFlexPWMA_RERR
**                Interrupt priority                       : default
**                ISR Name                                 : 
**                SM0 reload error interrupt               : Disabled
**              DMA settings                               : 
**                DMA for value registers                  : Disabled
**                Selected capture FIFO watermarks         : OR'ed together
**                Capture FIFO read DMA request            : Disabled
**                Capture A 0 FIFO DMA                     : Disabled
**                Capture A 1 FIFO DMA                     : Disabled
**                Capture B 0 FIFO DMA                     : Disabled
**                Capture B 1 FIFO DMA                     : Disabled
**                Capture X 0 FIFO DMA                     : Disabled
**                Capture X 1 FIFO DMA                     : Disabled
**            SM1 Interrupts/DMA                           : Disabled
**            SM2 Interrupts/DMA                           : Disabled
**            SM3 Interrupts/DMA                           : Disabled
**            Fault interrupt                              : 
**              Interrupt                                  : INT_eFlexPWMA_FAULT
**              Interrupt priority                         : default
**              ISR Name                                   : 
**              Channel 0 fault 0 interrupt                : Disabled
**              Channel 0 fault 1 interrupt                : Disabled
**              Channel 0 fault 2 interrupt                : Disabled
**              Channel 0 fault 3 interrupt                : Disabled
**              Channel 1 Fault 0 interrupt                : Disabled
**              Channel 1 Fault 1 interrupt                : Disabled
**              Channel 1 Fault 2 interrupt                : Disabled
**              Channel 1 Fault 3 interrupt                : Disabled
**          Initialization                                 : 
**            Load values after init into SM0              : yes
**            Load values after init into SM1              : no
**            Load values after init into SM2              : no
**            Load values after init into SM3              : no
**            Enable peripheral clock for SM0              : Enabled
**            Enable peripheral clock for SM1              : Enabled
**            Enable peripheral clock for SM2              : Enabled
**            Enable peripheral clock for SM3              : Enabled
**            Fault channel 0 test                         : No simulated fault
**            Fault channel 1 test                         : No simulated fault
**            Fault flag clearing                          : 
**              Fault channel 0 flag 0                     : Clear
**              Fault channel 0 flag 1                     : Clear
**              Fault channel 0 flag 2                     : Clear
**              Fault channel 0 flag 3                     : Clear
**              Fault channel 1 flag 0                     : Clear
**              Fault channel 1 flag 1                     : Clear
**              Fault channel 1 flag 2                     : Clear
**              Fault channel 1 flag 3                     : Clear
**            Monitor PLL mode                             : Do not monitor PLL
**            Call Init method                             : yes
**     Contents    :
**         Init - void eFPWM1_Init(void);
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

/* MODULE eFPWM1. */

#include "eFPWM1.h"
  /* Including shared modules, which are used in the whole project */
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
#include "Cpu.h"


/*
** ===================================================================
**     Method      :  eFPWM1_Init (component Init_eFlexPWM)
**
**     Description :
**         This method initializes registers of the eFlexPWM module
**         according to the Peripheral Initialization settings.
**         Call this method in user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void eFPWM1_Init(void)
{
  /* PWMA_MCTRL: IPOL&=~1,RUN&=~1,CLDOK|=1,LDOK&=~1 */
  clrSetReg16Bits(PWMA_MCTRL, 0x1101U, 0x10U); 
  /* PWMA_SM0INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
  setReg16(PWMA_SM0INTEN, 0x00U);       
  /* PWMA_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMA_FCTRL0, 0x00U);         
  /* PWMA_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMA_FCTRL1, 0x00U);         
  /* PWMA_SM0OCTRL: PWMA_IN=0,PWMB_IN=0,PWMX_IN=0,??=0,??=0,POLA=0,POLB=0,POLX=0,??=0,??=0,PWMAFS=0,PWMBFS=0,PWMXFS=0 */
  setReg16(PWMA_SM0OCTRL, 0x00U);       
  /* PWMA_SM0INIT: INIT=0 */
  setReg16(PWMA_SM0INIT, 0x00U);        
  /* PWMA_SM0CTRL2: DBGEN=1,WAITEN=1,INDEP=0,PWM23_INIT=0,PWM45_INIT=0,PWMX_INIT=0,INIT_SEL=0,FRCEN=0,FORCE=0,FORCE_SEL=0,RELOAD_SEL=0,CLK_SEL=0 */
  setReg16(PWMA_SM0CTRL2, 0xC000U);     
  /* PWMA_SM0CTRL: LDFQ=0,HALF=0,FULL=0,DT=0,??=0,PRSC=1,??=0,LDMOD=0,DBLX=0,DBLEN=0 */
  setReg16(PWMA_SM0CTRL, 0x10U);        
  /* PWMA_SM0TCTRL: PWAOT0=0,PWBOT1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUT_TRIG_EN=0 */
  setReg16(PWMA_SM0TCTRL, 0x00U);       
  /* PWMA_SM0VAL0: VAL0=0x07D0 */
  setReg16(PWMA_SM0VAL0, 0x07D0U);      
  /* PWMA_SM0VAL1: VAL1=0x0F9F */
  setReg16(PWMA_SM0VAL1, 0x0F9FU);      
  /* PWMA_SM0VAL2: VAL2=0x07D0 */
  setReg16(PWMA_SM0VAL2, 0x07D0U);      
  /* PWMA_SM0VAL3: VAL3=0x0F9F */
  setReg16(PWMA_SM0VAL3, 0x0F9FU);      
  /* PWMA_SM0VAL4: VAL4=0 */
  setReg16(PWMA_SM0VAL4, 0x00U);        
  /* PWMA_SM0VAL5: VAL5=0 */
  setReg16(PWMA_SM0VAL5, 0x00U);        
  /* PWMA_SM0FRACVAL1: FRACVAL1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMA_SM0FRACVAL1, 0x00U);    
  /* PWMA_SM0FRACVAL2: FRACVAL2=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMA_SM0FRACVAL2, 0x00U);    
  /* PWMA_SM0FRACVAL3: FRACVAL3=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMA_SM0FRACVAL3, 0x00U);    
  /* PWMA_SM0FRACVAL4: FRACVAL4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMA_SM0FRACVAL4, 0x00U);    
  /* PWMA_SM0FRACVAL5: FRACVAL5=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(PWMA_SM0FRACVAL5, 0x00U);    
  /* PWMA_SM0FRCTRL: TEST=0,??=0,??=0,??=0,??=0,??=0,??=0,FRAC_PU=0,??=0,??=0,??=0,FRAC45_EN=0,??=0,FRAC23_EN=0,FRAC1_EN=0,??=0 */
  setReg16(PWMA_SM0FRCTRL, 0x00U);      
  /* PWMA_SM0DISMAP0: ??=1,??=1,??=1,??=1,DIS0X=0,DIS0B=0,DIS0A=0 */
  setReg16(PWMA_SM0DISMAP0, 0xF000U);   
  /* PWMA_SM0DISMAP1: ??=1,??=1,??=1,??=1,DIS1X=0,DIS1B=0,DIS1A=0 */
  setReg16(PWMA_SM0DISMAP1, 0xF000U);   
  /* PWMA_SM0DTCNT0: ??=0,??=0,??=0,??=0,??=0,DTCNT0=0 */
  setReg16(PWMA_SM0DTCNT0, 0x00U);      
  /* PWMA_SM0DTCNT1: ??=0,??=0,??=0,??=0,??=0,DTCNT1=0 */
  setReg16(PWMA_SM0DTCNT1, 0x00U);      
  /* PWMA_SM0CAPTCOMPA: EDGCNTA=0,EDGCMPA=0 */
  setReg16(PWMA_SM0CAPTCOMPA, 0x00U);   
  /* PWMA_SM0CAPTCOMPB: EDGCNTB=0,EDGCMPB=0 */
  setReg16(PWMA_SM0CAPTCOMPB, 0x00U);   
  /* PWMA_SM0CAPTCOMPX: EDGCNTX=0,EDGCMPX=0 */
  setReg16(PWMA_SM0CAPTCOMPX, 0x00U);   
  /* PWMA_FFILT0: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
  setReg16(PWMA_FFILT0, 0x00U);         
  /* PWMA_FFILT1: GSTR=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
  setReg16(PWMA_FFILT1, 0x00U);         
  /* PWMA_MASK: ??=0,??=0,??=0,??=0,MASKA&=~1,MASKB&=~1,MASKX&=~1 */
  clrReg16Bits(PWMA_MASK, 0xF111U);     
  /* PWMA_SWCOUT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SM0OUT23=0,SM0OUT45=0 */
  clrReg16Bits(PWMA_SWCOUT, 0xFF03U);   
  /* PWMA_DTSRCSEL: SM0SEL23=0,SM0SEL45=0 */
  clrReg16Bits(PWMA_DTSRCSEL, 0x0FU);   
  /* PWMA_MCTRL2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MONPLL=0 */
  setReg16(PWMA_MCTRL2, 0x00U);         
  /* PWMA_OUTEN: ??=0,??=0,??=0,??=0,PWMA_EN|=1,PWMB_EN&=~1,PWMX_EN&=~1 */
  clrSetReg16Bits(PWMA_OUTEN, 0xF011U, 0x0100U); 
  /* PWMA_SM0CAPTCTRLA: CA1CNT=0,CA0CNT=0,CFAWM=0,EDGCNTA_EN=0,INP_SELA=0,EDGA1=0,EDGA0=0,ONESHOTA=0,ARMA=0 */
  setReg16(PWMA_SM0CAPTCTRLA, 0x00U);   
  /* PWMA_SM0CAPTCTRLB: CB1CNT=0,CB0CNT=0,CFBWM=0,EDGCNTB_EN=0,INP_SELB=0,EDGB1=0,EDGB0=0,ONESHOTB=0,ARMB=0 */
  setReg16(PWMA_SM0CAPTCTRLB, 0x00U);   
  /* PWMA_SM0CAPTCTRLX: CX1CNT=0,CX0CNT=0,CFXWM=0,EDGCNTX_EN=0,INP_SELX=0,EDGX1=0,EDGX0=0,ONESHOTX=0,ARMX=0 */
  setReg16(PWMA_SM0CAPTCTRLX, 0x00U);   
  /* PWMA_MCTRL: IPOL&=~1,RUN=0,CLDOK=0,LDOK=1 */
  clrSetReg16Bits(PWMA_MCTRL, 0x1FFEU, 0x01U); 
  /* PWMA_FSTS0: FHALF=0,FFPIN=0x0F,FFULL=0,FFLAG=0x0F */
  setReg16(PWMA_FSTS0, 0x0F0FU);        
  /* PWMA_FSTS1: FHALF=0,FFPIN=0x0F,FFULL=0,FFLAG=0x0F */
  setReg16(PWMA_FSTS1, 0x0F0FU);        
  /* PWMA_FCTRL0: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMA_FCTRL0, 0x00U);         
  /* PWMA_FCTRL1: FLVL=0,FAUTO=0,FSAFE=0,FIE=0 */
  setReg16(PWMA_FCTRL1, 0x00U);         
  /* PWMA_MCTRL: RUN|=1 */
  setReg16Bits(PWMA_MCTRL, 0x0100U);    
  /* PWMA_SM0STS: ??=0,RUF=0,REF=1,RF=1,CFA1=1,CFA0=1,CFB1=1,CFB0=1,CFX1=1,CFX0=1,CMPF=0x3F */
  setReg16(PWMA_SM0STS, 0x3FFFU);       
  /* PWMA_SM0INTEN: ??=0,??=0,REIE=0,RIE=0,CA1IE=0,CA0IE=0,CB1IE=0,CB0IE=0,CX1IE=0,CX0IE=0,CMPIE=0 */
  setReg16(PWMA_SM0INTEN, 0x00U);       
  /* PWMA_SM0DMAEN: ??=0,??=0,??=0,??=0,??=0,??=0,VALDE=0,FAND=0,CAPTDE=0,CA1DE=0,CA0DE=0,CB1DE=0,CB0DE=0,CX1DE=0,CX0DE=0 */
  setReg16(PWMA_SM0DMAEN, 0x00U);       
  /* PWMA_FTST0: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
  setReg16(PWMA_FTST0, 0x00U);          
  /* PWMA_FTST1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FTEST=0 */
  setReg16(PWMA_FTST1, 0x00U);          
}

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      ProcessorExpert.c
**      Events.c
**
** ###################################################################
#if defined(PWM_Compare_FAST_INT)
#pragma interrupt fast
#elif defined(PWM_Compare_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt
#endif
void PWM_Compare(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/


/* END eFPWM1. */
/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
