/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : CyclicADC.h
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : Init_ADC
**     Version     : Component 01.349, Driver 01.25, CPU db: 3.50.001
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-05-15, 17:58, # CodeGen: 5
**     Abstract    :
**         This "Init_ADC" Peripheral Inspector implements the
**         Analog-to-Digital converter module (ADC), basic 
**         initialization and settings.
**     Settings    :
**          Component name                                 : CyclicADC
**          Device                                         : ADC12
**          Settings                                       : 
**            Clock setting                                : 
**              Clock divisor select value                 : 10
**              A/D Frequency                              : 10 MHz
**              Speed control                              : clock frequency =< 5MHz
**              Clock divisor select value 1               : 10
**              A/D Frequency 1                            : 10 MHz
**              Speed control 1                            : clock frequency =< 5MHz
**            Stop mode (0)                                : yes
**            Stop mode 1                                  : yes
**            ADC mode                                     : Triggered Parallel
**            Parallel mode                                : simultaneous
**            Trigger mode (0)                             : SYNC input or START bit
**            Trigger mode 1                               : SYNC input or START bit
**            Sampling time (0)                            : 2 ADC clocks
**            Sampling time 1                              : 2 ADC clocks
**            Power savings mode                           : Disabled
**            Power-up delay                               : 26
**            Auto standby                                 : Disabled
**            DMA trigger source                           : EOSI
**            High volt. ref. source 0                     : internal
**            Low volt. ref. source 0                      : internal
**            High volt. ref. source 1                     : internal
**            Low volt. ref. source 1                      : internal
**            A/D Channels                                 : 
**              Channels configuration                     : 
**                ANA0-ANA1                                : Single ended mode
**                ANA2-ANA3                                : Single ended mode
**                ANB0-ANB1                                : Single ended mode
**                ANB2-ANB3                                : Single ended mode
**                ANA4-ANA5                                : Differential mode
**                ANA6-ANA7                                : Differential mode
**                ANB4-ANB5                                : Differential mode
**                ANB6-ANB7                                : Differential mode
**              Sample 0                                   : Enabled
**                Channel                                  : GPIOA4/ANA4/ANC8/CMPD_IN0
**                Channel signal                           : rt4
**                Negative input                           : Enabled
**                  Channel                                : GPIOA5/ANA5/ANC9
**                  Channel signal                         : rt3
**              Sample 1                                   : Enabled
**                Channel                                  : GPIOA6/ANA6/ANC10
**                Channel signal                           : 
**                Negative input                           : Enabled
**                  Channel                                : GPIOA7/ANA7/ANC11
**                  Channel signal                         : 
**              Sample 2                                   : Disabled
**              Sample 3                                   : Disabled
**              Sample 4                                   : Disabled
**              Sample 5                                   : Disabled
**              Sample 6                                   : Disabled
**              Sample 7                                   : Disabled
**              Sample 8                                   : Enabled
**                Channel                                  : GPIOB4/ANB4/ANC12/CMPC_IN1
**                Channel signal                           : rt1
**                Negative input                           : Enabled
**                  Channel                                : GPIOB5/ANB5/ANC13/CMPC_IN2
**                  Channel signal                         : 
**              Sample 9                                   : Enabled
**                Channel                                  : GPIOB6/ANB6/ANC14/CMPB_IN1
**                Channel signal                           : rt2
**                Negative input                           : Enabled
**                  Channel                                : GPIOB7/ANB7/ANC15/CMPB_IN2
**                  Channel signal                         : 
**              Sample 10                                  : Disabled
**              Sample 11                                  : Disabled
**              Sample 12                                  : Disabled
**              Sample 13                                  : Disabled
**              Sample 14                                  : Disabled
**              Sample 15                                  : Disabled
**              Internal trigger (0)                       : Disabled
**              Internal trigger 1                         : Disabled
**            Zero crossing                                : 
**              Sample 0                                   : disabled
**              Sample 1                                   : disabled
**              Sample 2                                   : disabled
**              Sample 3                                   : disabled
**              Sample 4                                   : disabled
**              Sample 5                                   : disabled
**              Sample 6                                   : disabled
**              Sample 7                                   : disabled
**              Sample 8                                   : disabled
**              Sample 9                                   : disabled
**              Sample 10                                  : disabled
**              Sample 11                                  : disabled
**              Sample 12                                  : disabled
**              Sample 13                                  : disabled
**              Sample 14                                  : disabled
**              Sample 15                                  : disabled
**            Low limit                                    : 
**              Low limit register 0                       : 0
**              Low limit register 1                       : 0
**              Low limit register 2                       : 0
**              Low limit register 3                       : 0
**              Low limit register 4                       : 0
**              Low limit register 5                       : 0
**              Low limit register 6                       : 0
**              Low limit register 7                       : 0
**              Low limit register 8                       : 0
**              Low limit register 9                       : 0
**              Low limit register 10                      : 0
**              Low limit register 11                      : 0
**              Low limit register 12                      : 0
**              Low limit register 13                      : 0
**              Low limit register 14                      : 0
**              Low limit register 15                      : 0
**            High limit                                   : 
**              High limit register 0                      : 7FF8
**              High limit register 1                      : 7FF8
**              High limit register 2                      : 7FF8
**              High limit register 3                      : 7FF8
**              High limit register 4                      : 7FF8
**              High limit register 5                      : 7FF8
**              High limit register 6                      : 7FF8
**              High limit register 7                      : 7FF8
**              High limit register 8                      : 7FF8
**              High limit register 9                      : 7FF8
**              High limit register 10                     : 7FF8
**              High limit register 11                     : 7FF8
**              High limit register 12                     : 7FF8
**              High limit register 13                     : 7FF8
**              High limit register 14                     : 7FF8
**              High limit register 15                     : 7FF8
**            Offset                                       : 
**              Offset register 0                          : 4000
**              Offset register 1                          : 4000
**              Offset register 2                          : 4000
**              Offset register 3                          : 4000
**              Offset register 4                          : 4000
**              Offset register 5                          : 4000
**              Offset register 6                          : 4000
**              Offset register 7                          : 4000
**              Offset register 8                          : 4000
**              Offset register 9                          : 4000
**              Offset register 10                         : 4000
**              Offset register 11                         : 4000
**              Offset register 12                         : 4000
**              Offset register 13                         : 4000
**              Offset register 14                         : 4000
**              Offset register 15                         : 4000
**            Gain control                                 : 
**              ANA0                                       : x1 amplification
**              ANA1                                       : x1 amplification
**              ANA2                                       : x1 amplification
**              ANA3                                       : x1 amplification
**              ANA4                                       : x1 amplification
**              ANA5                                       : x1 amplification
**              ANA6                                       : x2 amplification
**              ANA7                                       : x2 amplification
**              ANB0                                       : x1 amplification
**              ANB1                                       : x1 amplification
**              ANB2                                       : x1 amplification
**              ANB3                                       : x1 amplification
**              ANB4                                       : x4 amplification
**              ANB5                                       : x4 amplification
**              ANB6                                       : x1 amplification
**              ANB7                                       : x1 amplification
**            Scan control                                 : 
**              Sample 0                                   : Continue
**              Sample 1                                   : Continue
**              Sample 2                                   : Continue
**              Sample 3                                   : Continue
**              Sample 4                                   : Continue
**              Sample 5                                   : Continue
**              Sample 6                                   : Continue
**              Sample 7                                   : Continue
**              Sample 8                                   : Continue
**              Sample 9                                   : Continue
**              Sample 10                                  : Continue
**              Sample 11                                  : Continue
**              Sample 12                                  : Continue
**              Sample 13                                  : Continue
**              Sample 14                                  : Continue
**              Sample 15                                  : Continue
**          Interrupts/DMA                                 : 
**            Conversion complete (0)                      : 
**              Interrupt                                  : INT_ADC12_CC0
**              End of scan interrupt                      : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : ADC_EndofScanISR
**              DMA request                                : Disabled
**            Conversion complete 1                        : 
**              Interrupt                                  : INT_ADC12_CC1
**              End of scan interrupt                      : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : 
**              DMA request                                : Disabled
**            Scan halted interrupt enable                 : 
**              Sample 0                                   : Disabled
**              Sample 1                                   : Disabled
**              Sample 2                                   : Disabled
**              Sample 3                                   : Disabled
**              Sample 4                                   : Disabled
**              Sample 5                                   : Disabled
**              Sample 6                                   : Disabled
**              Sample 7                                   : Disabled
**              Sample 8                                   : Disabled
**              Sample 9                                   : Disabled
**              Sample 10                                  : Disabled
**              Sample 11                                  : Disabled
**              Sample 12                                  : Disabled
**              Sample 13                                  : Disabled
**              Sample 14                                  : Disabled
**              Sample 15                                  : Disabled
**            Zero crossing or limit error                 : 
**              Interrupt                                  : INT_ADC12_ERR
**              Zero crossing interrupt                    : Disabled
**              Low limit error interrupt                  : Disabled
**              High limit error interrupt                 : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : 
**          Initialization                                 : 
**            Call Init method                             : yes
**            Enable peripheral clock                      : yes
**            Start ADC conversion (0)                     : no
**            Start ADC conversion 1                       : no
**            Power down ADC 0                             : no
**            Power down ADC 1                             : no
**     Contents    :
**         Init - void CyclicADC_Init(void);
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

#ifndef __CyclicADC
#define __CyclicADC

/* MODULE CyclicADC. */

/*Include shared modules, which are used for whole project*/
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
/* Include inherited beans */
#include "Cpu.h"

/* PESL device mapping  */
#define CyclicADC_DEVICE ADC12

void ADC_EndofScanISR(void);
/*
** ===================================================================
** The interrupt service routine must be implemented by user in one
** of the user modules (see CyclicADC.c file for more information).
** ===================================================================
*/

void CyclicADC_Init(void);
/*
** ===================================================================
**     Method      :  CyclicADC_Init (component Init_ADC)
**
**     Description :
**         This method initializes registers of the ADC module
**         according to this Peripheral Initialization settings. Call
**         this method in the user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/

/* END CyclicADC. */

#endif /* ifndef __CyclicADC */
/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
