/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : IO_Map.h
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : IO_Map
**     Version     : Driver 01.00
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-07-05, 11:55, # CodeGen: 8
**     Abstract    :
**         IO_Map.h - implements an IO device's mapping. 
**         This module contains symbol definitions of all peripheral 
**         registers and bits. 
**     Settings    :
**
**     Contents    :
**         No public methods
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

#ifndef __IO_Map_H
#define __IO_Map_H

/*lint -save  -e621 Disable MISRA rule (1.4) checking. */
/* Based on CPU DB MC56F84789VLL, version 3.50.001 (RegistersPrg V2.33) */
/* DataSheet : MC56F847XXRM Rev.0RC 10/201 */

#include "PE_Types.h"

/******************************************
*** Peripheral MCM
*******************************************/
typedef volatile struct {
  /*** MCM_PLASC - Crossbar switch (AXBS) slave configuration; 0x00018008 ***/
  union {
    word Word;
  } MCM_PLASC_STR;

  #define MCM_PLASC_ASC0_MASK           0x01U
  #define MCM_PLASC_ASC1_MASK           0x02U
  #define MCM_PLASC_ASC2_MASK           0x04U
  #define MCM_PLASC_ASC3_MASK           0x08U
  #define MCM_PLASC_ASC4_MASK           0x10U
  #define MCM_PLASC_ASC5_MASK           0x20U
  #define MCM_PLASC_ASC6_MASK           0x40U
  #define MCM_PLASC_ASC7_MASK           0x80U
  #define MCM_PLASC_DP64_MASK           0x8000U
  #define MCM_PLASC_ASC_MASK            0xFFU
  #define MCM_PLASC_ASC_BITNUM          0x00U
  #define MCM_PLASC                     (*((volatile word *)0x0000C004))


  /*** MCM_PLAMC - Crossbar switch (AXBS) master configuration; 0x0001800A ***/
  union {
    word Word;
  } MCM_PLAMC_STR;

  #define MCM_PLAMC_AMC0_MASK           0x01U
  #define MCM_PLAMC_AMC1_MASK           0x02U
  #define MCM_PLAMC_AMC2_MASK           0x04U
  #define MCM_PLAMC_AMC3_MASK           0x08U
  #define MCM_PLAMC_AMC4_MASK           0x10U
  #define MCM_PLAMC_AMC5_MASK           0x20U
  #define MCM_PLAMC_AMC6_MASK           0x40U
  #define MCM_PLAMC_AMC7_MASK           0x80U
  #define MCM_PLAMC_AMC_MASK            0xFFU
  #define MCM_PLAMC_AMC_BITNUM          0x00U
  #define MCM_PLAMC                     (*((volatile word *)0x0000C005))


  /*** MCM_CPCR - Core control register; 0x0001800C ***/
  union {
    dword Dword;
  } MCM_CPCR_STR;

  #define MCM_CPCR_SOCCR0_MASK          0x01UL
  #define MCM_CPCR_SOCCR1_MASK          0x02UL
  #define MCM_CPCR_SOCCR2_MASK          0x04UL
  #define MCM_CPCR_SOCCR3_MASK          0x08UL
  #define MCM_CPCR_SOCCR4_MASK          0x10UL
  #define MCM_CPCR_SOCCR5_MASK          0x20UL
  #define MCM_CPCR_SOCCR6_MASK          0x40UL
  #define MCM_CPCR_SOCCR7_MASK          0x80UL
  #define MCM_CPCR_SOCCR8_MASK          0x0100UL
  #define MCM_CPCR_SOCCR9_MASK          0x0200UL
  #define MCM_CPCR_SOCCR10_MASK         0x0400UL
  #define MCM_CPCR_SOCCR11_MASK         0x0800UL
  #define MCM_CPCR_SOCCR12_MASK         0x1000UL
  #define MCM_CPCR_SOCCR13_MASK         0x2000UL
  #define MCM_CPCR_SOCCR14_MASK         0x4000UL
  #define MCM_CPCR_SOCCR15_MASK         0x8000UL
  #define MCM_CPCR_INSDIS_MASK          0x00010000UL
  #define MCM_CPCR_RCDIS_MASK           0x00020000UL
  #define MCM_CPCR_SRDIS_MASK           0x00040000UL
  #define MCM_CPCR_IBDIS_MASK           0x00080000UL
  #define MCM_CPCR_XBARARB_MASK         0x80000000UL
  #define MCM_CPCR_SOCCR_MASK           0xFFFFUL
  #define MCM_CPCR_SOCCR_BITNUM         0x00U
  #define MCM_CPCR                      (*((volatile dword *)0x0000C006))


  /*** MCM_CFADR - Core fault address register; 0x00018010 ***/
  union {
    dword Dword;
  } MCM_CFADR_STR;

  #define MCM_CFADR                     (*((volatile dword *)0x0000C008))


  /*** MCM_CFATR - Core fault attributes register; 0x00018014 ***/
  union {
    byte Byte;
  } MCM_CFATR_STR;

  #define MCM_CFATR_TYPE_MASK           0x01U
  #define MCM_CFATR_BUFFER_MASK         0x04U
  #define MCM_CFATR_SIZE0_MASK          0x10U
  #define MCM_CFATR_SIZE1_MASK          0x20U
  #define MCM_CFATR_SIZE2_MASK          0x40U
  #define MCM_CFATR_DIR_MASK            0x80U
  #define MCM_CFATR_SIZE_MASK           0x70U
  #define MCM_CFATR_SIZE_BITNUM         0x04U
  #define MCM_CFATR                     (*((volatile byte *)0x00018014))


  /*** MCM_CFLOC - Core fault location register; 0x00018015 ***/
  union {
    byte Byte;
  } MCM_CFLOC_STR;

  #define MCM_CFLOC_LOC0_MASK           0x40U
  #define MCM_CFLOC_LOC1_MASK           0x80U
  #define MCM_CFLOC_LOC_MASK            0xC0U
  #define MCM_CFLOC_LOC_BITNUM          0x06U
  #define MCM_CFLOC                     (*((volatile byte *)0x00018015))


  /*** MCM_CFIER - Core fault interrupt enable register; 0x00018016 ***/
  union {
    byte Byte;
  } MCM_CFIER_STR;

  #define MCM_CFIER_ECFEI_MASK          0x80U
  #define MCM_CFIER                     (*((volatile byte *)0x00018016))


  /*** MCM_CFISR - MCM interrupt status register; 0x00018017 ***/
  union {
    byte Byte;
  } MCM_CFISR_STR;

  #define MCM_CFISR_CFEI_MASK           0x80U
  #define MCM_CFISR                     (*((volatile byte *)0x00018017))


  /*** MCM_CFDTR - Core fault data register; 0x00018018 ***/
  union {
    dword Dword;
  } MCM_CFDTR_STR;

  #define MCM_CFDTR                     (*((volatile dword *)0x0000C00C))


  dword Reserved0[1];                  /* Reserved (unused) registers */

  /*** MCM_RPCR - Resource Protection Control Register; 0x00018020 ***/
  union {
    dword Dword;
  } MCM_RPCR_STR;

  #define MCM_RPCR_RPE_MASK             0x01UL
  #define MCM_RPCR_RL_MASK              0x02UL
  #define MCM_RPCR                      (*((volatile dword *)0x0000C010))


  /*** MCM_UFLASHBAR - User Flash Base Address Register; 0x00018024 ***/
  union {
    dword Dword;
  } MCM_UFLASHBAR_STR;

  #define MCM_UFLASHBAR_FBA0_MASK       0x1000UL
  #define MCM_UFLASHBAR_FBA1_MASK       0x2000UL
  #define MCM_UFLASHBAR_FBA2_MASK       0x4000UL
  #define MCM_UFLASHBAR_FBA3_MASK       0x8000UL
  #define MCM_UFLASHBAR_FBA4_MASK       0x00010000UL
  #define MCM_UFLASHBAR_FBA5_MASK       0x00020000UL
  #define MCM_UFLASHBAR_FBA_MASK        0x0003F000UL
  #define MCM_UFLASHBAR_FBA_BITNUM      0x0CU
  #define MCM_UFLASHBAR                 (*((volatile dword *)0x0000C012))


  /*** MCM_UPRAMBAR - User Program RAM Base Address Register; 0x00018028 ***/
  union {
    dword Dword;
  } MCM_UPRAMBAR_STR;

  #define MCM_UPRAMBAR_RBA0_MASK        0x0100UL
  #define MCM_UPRAMBAR_RBA1_MASK        0x0200UL
  #define MCM_UPRAMBAR_RBA2_MASK        0x0400UL
  #define MCM_UPRAMBAR_RBA3_MASK        0x0800UL
  #define MCM_UPRAMBAR_RBA4_MASK        0x1000UL
  #define MCM_UPRAMBAR_RBA5_MASK        0x2000UL
  #define MCM_UPRAMBAR_RBA6_MASK        0x4000UL
  #define MCM_UPRAMBAR_RBA_MASK         0x7F00UL
  #define MCM_UPRAMBAR_RBA_BITNUM       0x08U
  #define MCM_UPRAMBAR                  (*((volatile dword *)0x0000C014))


  dword Reserved1[1];                  /* Reserved (unused) registers */

  /*** MCM_SRPOSP - Resource Protection Other Stack Pointer; 0x00018030 ***/
  union {
    dword Dword;
  } MCM_SRPOSP_STR;

  #define MCM_SRPOSP_SRPOSP0_MASK       0x01UL
  #define MCM_SRPOSP_SRPOSP1_MASK       0x02UL
  #define MCM_SRPOSP_SRPOSP2_MASK       0x04UL
  #define MCM_SRPOSP_SRPOSP3_MASK       0x08UL
  #define MCM_SRPOSP_SRPOSP4_MASK       0x10UL
  #define MCM_SRPOSP_SRPOSP5_MASK       0x20UL
  #define MCM_SRPOSP_SRPOSP6_MASK       0x40UL
  #define MCM_SRPOSP_SRPOSP7_MASK       0x80UL
  #define MCM_SRPOSP_SRPOSP8_MASK       0x0100UL
  #define MCM_SRPOSP_SRPOSP9_MASK       0x0200UL
  #define MCM_SRPOSP_SRPOSP10_MASK      0x0400UL
  #define MCM_SRPOSP_SRPOSP11_MASK      0x0800UL
  #define MCM_SRPOSP_SRPOSP12_MASK      0x1000UL
  #define MCM_SRPOSP_SRPOSP13_MASK      0x2000UL
  #define MCM_SRPOSP_SRPOSP14_MASK      0x4000UL
  #define MCM_SRPOSP_SRPOSP15_MASK      0x8000UL
  #define MCM_SRPOSP_SRPOSP16_MASK      0x00010000UL
  #define MCM_SRPOSP_SRPOSP17_MASK      0x00020000UL
  #define MCM_SRPOSP_SRPOSP18_MASK      0x00040000UL
  #define MCM_SRPOSP_SRPOSP19_MASK      0x00080000UL
  #define MCM_SRPOSP_SRPOSP20_MASK      0x00100000UL
  #define MCM_SRPOSP_SRPOSP21_MASK      0x00200000UL
  #define MCM_SRPOSP_SRPOSP22_MASK      0x00400000UL
  #define MCM_SRPOSP_SRPOSP23_MASK      0x00800000UL
  #define MCM_SRPOSP_SRPOSP_MASK        0x00FFFFFFUL
  #define MCM_SRPOSP_SRPOSP_BITNUM      0x00U
  #define MCM_SRPOSP                    (*((volatile dword *)0x0000C018))


  /*** MCM_SRPIPC - Memory Protection Illegal PC; 0x00018034 ***/
  union {
    dword Dword;
  } MCM_SRPIPC_STR;

  #define MCM_SRPIPC_SRPIFPC0_MASK      0x01UL
  #define MCM_SRPIPC_SRPIFPC1_MASK      0x02UL
  #define MCM_SRPIPC_SRPIFPC2_MASK      0x04UL
  #define MCM_SRPIPC_SRPIFPC3_MASK      0x08UL
  #define MCM_SRPIPC_SRPIFPC4_MASK      0x10UL
  #define MCM_SRPIPC_SRPIFPC5_MASK      0x20UL
  #define MCM_SRPIPC_SRPIFPC6_MASK      0x40UL
  #define MCM_SRPIPC_SRPIFPC7_MASK      0x80UL
  #define MCM_SRPIPC_SRPIFPC8_MASK      0x0100UL
  #define MCM_SRPIPC_SRPIFPC9_MASK      0x0200UL
  #define MCM_SRPIPC_SRPIFPC10_MASK     0x0400UL
  #define MCM_SRPIPC_SRPIFPC11_MASK     0x0800UL
  #define MCM_SRPIPC_SRPIFPC12_MASK     0x1000UL
  #define MCM_SRPIPC_SRPIFPC13_MASK     0x2000UL
  #define MCM_SRPIPC_SRPIFPC14_MASK     0x4000UL
  #define MCM_SRPIPC_SRPIFPC15_MASK     0x8000UL
  #define MCM_SRPIPC_SRPIFPC16_MASK     0x00010000UL
  #define MCM_SRPIPC_SRPIFPC17_MASK     0x00020000UL
  #define MCM_SRPIPC_SRPIFPC18_MASK     0x00040000UL
  #define MCM_SRPIPC_SRPIFPC19_MASK     0x00080000UL
  #define MCM_SRPIPC_SRPIFPC20_MASK     0x00100000UL
  #define MCM_SRPIPC_SRPIFOR_MASK       0x40000000UL
  #define MCM_SRPIPC_SRPIFV_MASK        0x80000000UL
  #define MCM_SRPIPC_SRPIFPC_MASK       0x001FFFFFUL
  #define MCM_SRPIPC_SRPIFPC_BITNUM     0x00U
  #define MCM_SRPIPC                    (*((volatile dword *)0x0000C01A))


  /*** MCM_SRPMPC - Resource Protection Misaligned PC; 0x00018038 ***/
  union {
    dword Dword;
  } MCM_SRPMPC_STR;

  #define MCM_SRPMPC_SRPMFPC0_MASK      0x01UL
  #define MCM_SRPMPC_SRPMFPC1_MASK      0x02UL
  #define MCM_SRPMPC_SRPMFPC2_MASK      0x04UL
  #define MCM_SRPMPC_SRPMFPC3_MASK      0x08UL
  #define MCM_SRPMPC_SRPMFPC4_MASK      0x10UL
  #define MCM_SRPMPC_SRPMFPC5_MASK      0x20UL
  #define MCM_SRPMPC_SRPMFPC6_MASK      0x40UL
  #define MCM_SRPMPC_SRPMFPC7_MASK      0x80UL
  #define MCM_SRPMPC_SRPMFPC8_MASK      0x0100UL
  #define MCM_SRPMPC_SRPMFPC9_MASK      0x0200UL
  #define MCM_SRPMPC_SRPMFPC10_MASK     0x0400UL
  #define MCM_SRPMPC_SRPMFPC11_MASK     0x0800UL
  #define MCM_SRPMPC_SRPMFPC12_MASK     0x1000UL
  #define MCM_SRPMPC_SRPMFPC13_MASK     0x2000UL
  #define MCM_SRPMPC_SRPMFPC14_MASK     0x4000UL
  #define MCM_SRPMPC_SRPMFPC15_MASK     0x8000UL
  #define MCM_SRPMPC_SRPMFPC16_MASK     0x00010000UL
  #define MCM_SRPMPC_SRPMFPC17_MASK     0x00020000UL
  #define MCM_SRPMPC_SRPMFPC18_MASK     0x00040000UL
  #define MCM_SRPMPC_SRPMFPC19_MASK     0x00080000UL
  #define MCM_SRPMPC_SRPMFPC20_MASK     0x00100000UL
  #define MCM_SRPMPC_SRPMFOR_MASK       0x40000000UL
  #define MCM_SRPMPC_SRPMFV_MASK        0x80000000UL
  #define MCM_SRPMPC_SRPMFPC_MASK       0x001FFFFFUL
  #define MCM_SRPMPC_SRPMFPC_BITNUM     0x00U
  #define MCM_SRPMPC                    (*((volatile dword *)0x0000C01C))


} MCM_PRPH;
/******************************************
*** Peripheral DMA
*******************************************/
typedef volatile struct {
  /*** DMA_REQC - DMA Request Control Register; 0x0000C800 ***/
  union {
    dword Dword;
  } DMA_REQC_STR;

  #define DMA_REQC_DMAC30_MASK          0x01UL
  #define DMA_REQC_DMAC31_MASK          0x02UL
  #define DMA_REQC_DMAC32_MASK          0x04UL
  #define DMA_REQC_DMAC33_MASK          0x08UL
  #define DMA_REQC_CFSM3_MASK           0x80UL
  #define DMA_REQC_DMAC20_MASK          0x0100UL
  #define DMA_REQC_DMAC21_MASK          0x0200UL
  #define DMA_REQC_DMAC22_MASK          0x0400UL
  #define DMA_REQC_DMAC23_MASK          0x0800UL
  #define DMA_REQC_CFSM2_MASK           0x8000UL
  #define DMA_REQC_DMAC10_MASK          0x00010000UL
  #define DMA_REQC_DMAC11_MASK          0x00020000UL
  #define DMA_REQC_DMAC12_MASK          0x00040000UL
  #define DMA_REQC_DMAC13_MASK          0x00080000UL
  #define DMA_REQC_CFSM1_MASK           0x00800000UL
  #define DMA_REQC_DMAC00_MASK          0x01000000UL
  #define DMA_REQC_DMAC01_MASK          0x02000000UL
  #define DMA_REQC_DMAC02_MASK          0x04000000UL
  #define DMA_REQC_DMAC03_MASK          0x08000000UL
  #define DMA_REQC_CFSM0_MASK           0x80000000UL
  #define DMA_REQC_DMAC3_MASK           0x0FUL
  #define DMA_REQC_DMAC3_BITNUM         0x00U
  #define DMA_REQC_DMAC2_MASK           0x0F00UL
  #define DMA_REQC_DMAC2_BITNUM         0x08U
  #define DMA_REQC_DMAC1_MASK           0x000F0000UL
  #define DMA_REQC_DMAC1_BITNUM         0x10U
  #define DMA_REQC_DMAC0_MASK           0x0F000000UL
  #define DMA_REQC_DMAC0_BITNUM         0x18U
  #define DMA_REQC                      (*((volatile dword *)0x0000C800))


  dword Reserved0[63];                 /* Reserved (unused) registers */

  /*** DMA_SAR0 - Source Address Register; 0x0000C880 ***/
  union {
    dword Dword;
  } DMA_SAR0_STR;

  #define DMA_SAR0                      (*((volatile dword *)0x0000C880))


  /*** DMA_DAR0 - Destination Address Register; 0x0000C882 ***/
  union {
    dword Dword;
  } DMA_DAR0_STR;

  #define DMA_DAR0                      (*((volatile dword *)0x0000C882))


  /*** DMA_DSR_BCR0 - DMA Status Register / Byte Count Register; 0x0000C884 ***/
  union {
    dword Dword;
  } DMA_DSR_BCR0_STR;

  #define DMA_DSR_BCR0_BCR0_MASK        0x01UL
  #define DMA_DSR_BCR0_BCR1_MASK        0x02UL
  #define DMA_DSR_BCR0_BCR2_MASK        0x04UL
  #define DMA_DSR_BCR0_BCR3_MASK        0x08UL
  #define DMA_DSR_BCR0_BCR4_MASK        0x10UL
  #define DMA_DSR_BCR0_BCR5_MASK        0x20UL
  #define DMA_DSR_BCR0_BCR6_MASK        0x40UL
  #define DMA_DSR_BCR0_BCR7_MASK        0x80UL
  #define DMA_DSR_BCR0_BCR8_MASK        0x0100UL
  #define DMA_DSR_BCR0_BCR9_MASK        0x0200UL
  #define DMA_DSR_BCR0_BCR10_MASK       0x0400UL
  #define DMA_DSR_BCR0_BCR11_MASK       0x0800UL
  #define DMA_DSR_BCR0_BCR12_MASK       0x1000UL
  #define DMA_DSR_BCR0_BCR13_MASK       0x2000UL
  #define DMA_DSR_BCR0_BCR14_MASK       0x4000UL
  #define DMA_DSR_BCR0_BCR15_MASK       0x8000UL
  #define DMA_DSR_BCR0_BCR16_MASK       0x00010000UL
  #define DMA_DSR_BCR0_BCR17_MASK       0x00020000UL
  #define DMA_DSR_BCR0_BCR18_MASK       0x00040000UL
  #define DMA_DSR_BCR0_BCR19_MASK       0x00080000UL
  #define DMA_DSR_BCR0_BCR20_MASK       0x00100000UL
  #define DMA_DSR_BCR0_BCR21_MASK       0x00200000UL
  #define DMA_DSR_BCR0_BCR22_MASK       0x00400000UL
  #define DMA_DSR_BCR0_BCR23_MASK       0x00800000UL
  #define DMA_DSR_BCR0_DONE_MASK        0x01000000UL
  #define DMA_DSR_BCR0_BSY_MASK         0x02000000UL
  #define DMA_DSR_BCR0_REQ_MASK         0x04000000UL
  #define DMA_DSR_BCR0_BED_MASK         0x10000000UL
  #define DMA_DSR_BCR0_BES_MASK         0x20000000UL
  #define DMA_DSR_BCR0_CE_MASK          0x40000000UL
  #define DMA_DSR_BCR0_BCR_MASK         0x00FFFFFFUL
  #define DMA_DSR_BCR0_BCR_BITNUM       0x00U
  #define DMA_DSR_BCR0                  (*((volatile dword *)0x0000C884))


  /*** DMA_DCR0 - DMA Control Register; 0x0000C886 ***/
  union {
    dword Dword;
  } DMA_DCR0_STR;

  #define DMA_DCR0_LCH20_MASK           0x01UL
  #define DMA_DCR0_LCH21_MASK           0x02UL
  #define DMA_DCR0_LCH10_MASK           0x04UL
  #define DMA_DCR0_LCH11_MASK           0x08UL
  #define DMA_DCR0_LINKCC0_MASK         0x10UL
  #define DMA_DCR0_LINKCC1_MASK         0x20UL
  #define DMA_DCR0_D_REQ_MASK           0x80UL
  #define DMA_DCR0_DMOD0_MASK           0x0100UL
  #define DMA_DCR0_DMOD1_MASK           0x0200UL
  #define DMA_DCR0_DMOD2_MASK           0x0400UL
  #define DMA_DCR0_DMOD3_MASK           0x0800UL
  #define DMA_DCR0_SMOD0_MASK           0x1000UL
  #define DMA_DCR0_SMOD1_MASK           0x2000UL
  #define DMA_DCR0_SMOD2_MASK           0x4000UL
  #define DMA_DCR0_SMOD3_MASK           0x8000UL
  #define DMA_DCR0_START_MASK           0x00010000UL
  #define DMA_DCR0_DSIZE0_MASK          0x00020000UL
  #define DMA_DCR0_DSIZE1_MASK          0x00040000UL
  #define DMA_DCR0_DINC_MASK            0x00080000UL
  #define DMA_DCR0_SSIZE0_MASK          0x00100000UL
  #define DMA_DCR0_SSIZE1_MASK          0x00200000UL
  #define DMA_DCR0_SINC_MASK            0x00400000UL
  #define DMA_DCR0_AA_MASK              0x10000000UL
  #define DMA_DCR0_CS_MASK              0x20000000UL
  #define DMA_DCR0_ERQ_MASK             0x40000000UL
  #define DMA_DCR0_EINT_MASK            0x80000000UL
  #define DMA_DCR0_LCH2_MASK            0x03UL
  #define DMA_DCR0_LCH2_BITNUM          0x00U
  #define DMA_DCR0_LCH1_MASK            0x0CUL
  #define DMA_DCR0_LCH1_BITNUM          0x02U
  #define DMA_DCR0_LINKCC_MASK          0x30UL
  #define DMA_DCR0_LINKCC_BITNUM        0x04U
  #define DMA_DCR0_DMOD_MASK            0x0F00UL
  #define DMA_DCR0_DMOD_BITNUM          0x08U
  #define DMA_DCR0_SMOD_MASK            0xF000UL
  #define DMA_DCR0_SMOD_BITNUM          0x0CU
  #define DMA_DCR0_DSIZE_MASK           0x00060000UL
  #define DMA_DCR0_DSIZE_BITNUM         0x11U
  #define DMA_DCR0_SSIZE_MASK           0x00300000UL
  #define DMA_DCR0_SSIZE_BITNUM         0x14U
  #define DMA_DCR0                      (*((volatile dword *)0x0000C886))


  /*** DMA_SAR1 - Source Address Register; 0x0000C888 ***/
  union {
    dword Dword;
  } DMA_SAR1_STR;

  #define DMA_SAR1                      (*((volatile dword *)0x0000C888))


  /*** DMA_DAR1 - Destination Address Register; 0x0000C88A ***/
  union {
    dword Dword;
  } DMA_DAR1_STR;

  #define DMA_DAR1                      (*((volatile dword *)0x0000C88A))


  /*** DMA_DSR_BCR1 - DMA Status Register / Byte Count Register; 0x0000C88C ***/
  union {
    dword Dword;
  } DMA_DSR_BCR1_STR;

  #define DMA_DSR_BCR1_BCR0_MASK        0x01UL
  #define DMA_DSR_BCR1_BCR1_MASK        0x02UL
  #define DMA_DSR_BCR1_BCR2_MASK        0x04UL
  #define DMA_DSR_BCR1_BCR3_MASK        0x08UL
  #define DMA_DSR_BCR1_BCR4_MASK        0x10UL
  #define DMA_DSR_BCR1_BCR5_MASK        0x20UL
  #define DMA_DSR_BCR1_BCR6_MASK        0x40UL
  #define DMA_DSR_BCR1_BCR7_MASK        0x80UL
  #define DMA_DSR_BCR1_BCR8_MASK        0x0100UL
  #define DMA_DSR_BCR1_BCR9_MASK        0x0200UL
  #define DMA_DSR_BCR1_BCR10_MASK       0x0400UL
  #define DMA_DSR_BCR1_BCR11_MASK       0x0800UL
  #define DMA_DSR_BCR1_BCR12_MASK       0x1000UL
  #define DMA_DSR_BCR1_BCR13_MASK       0x2000UL
  #define DMA_DSR_BCR1_BCR14_MASK       0x4000UL
  #define DMA_DSR_BCR1_BCR15_MASK       0x8000UL
  #define DMA_DSR_BCR1_BCR16_MASK       0x00010000UL
  #define DMA_DSR_BCR1_BCR17_MASK       0x00020000UL
  #define DMA_DSR_BCR1_BCR18_MASK       0x00040000UL
  #define DMA_DSR_BCR1_BCR19_MASK       0x00080000UL
  #define DMA_DSR_BCR1_BCR20_MASK       0x00100000UL
  #define DMA_DSR_BCR1_BCR21_MASK       0x00200000UL
  #define DMA_DSR_BCR1_BCR22_MASK       0x00400000UL
  #define DMA_DSR_BCR1_BCR23_MASK       0x00800000UL
  #define DMA_DSR_BCR1_DONE_MASK        0x01000000UL
  #define DMA_DSR_BCR1_BSY_MASK         0x02000000UL
  #define DMA_DSR_BCR1_REQ_MASK         0x04000000UL
  #define DMA_DSR_BCR1_BED_MASK         0x10000000UL
  #define DMA_DSR_BCR1_BES_MASK         0x20000000UL
  #define DMA_DSR_BCR1_CE_MASK          0x40000000UL
  #define DMA_DSR_BCR1_BCR_MASK         0x00FFFFFFUL
  #define DMA_DSR_BCR1_BCR_BITNUM       0x00U
  #define DMA_DSR_BCR1                  (*((volatile dword *)0x0000C88C))


  /*** DMA_DCR1 - DMA Control Register; 0x0000C88E ***/
  union {
    dword Dword;
  } DMA_DCR1_STR;

  #define DMA_DCR1_LCH20_MASK           0x01UL
  #define DMA_DCR1_LCH21_MASK           0x02UL
  #define DMA_DCR1_LCH10_MASK           0x04UL
  #define DMA_DCR1_LCH11_MASK           0x08UL
  #define DMA_DCR1_LINKCC0_MASK         0x10UL
  #define DMA_DCR1_LINKCC1_MASK         0x20UL
  #define DMA_DCR1_D_REQ_MASK           0x80UL
  #define DMA_DCR1_DMOD0_MASK           0x0100UL
  #define DMA_DCR1_DMOD1_MASK           0x0200UL
  #define DMA_DCR1_DMOD2_MASK           0x0400UL
  #define DMA_DCR1_DMOD3_MASK           0x0800UL
  #define DMA_DCR1_SMOD0_MASK           0x1000UL
  #define DMA_DCR1_SMOD1_MASK           0x2000UL
  #define DMA_DCR1_SMOD2_MASK           0x4000UL
  #define DMA_DCR1_SMOD3_MASK           0x8000UL
  #define DMA_DCR1_START_MASK           0x00010000UL
  #define DMA_DCR1_DSIZE0_MASK          0x00020000UL
  #define DMA_DCR1_DSIZE1_MASK          0x00040000UL
  #define DMA_DCR1_DINC_MASK            0x00080000UL
  #define DMA_DCR1_SSIZE0_MASK          0x00100000UL
  #define DMA_DCR1_SSIZE1_MASK          0x00200000UL
  #define DMA_DCR1_SINC_MASK            0x00400000UL
  #define DMA_DCR1_AA_MASK              0x10000000UL
  #define DMA_DCR1_CS_MASK              0x20000000UL
  #define DMA_DCR1_ERQ_MASK             0x40000000UL
  #define DMA_DCR1_EINT_MASK            0x80000000UL
  #define DMA_DCR1_LCH2_MASK            0x03UL
  #define DMA_DCR1_LCH2_BITNUM          0x00U
  #define DMA_DCR1_LCH1_MASK            0x0CUL
  #define DMA_DCR1_LCH1_BITNUM          0x02U
  #define DMA_DCR1_LINKCC_MASK          0x30UL
  #define DMA_DCR1_LINKCC_BITNUM        0x04U
  #define DMA_DCR1_DMOD_MASK            0x0F00UL
  #define DMA_DCR1_DMOD_BITNUM          0x08U
  #define DMA_DCR1_SMOD_MASK            0xF000UL
  #define DMA_DCR1_SMOD_BITNUM          0x0CU
  #define DMA_DCR1_DSIZE_MASK           0x00060000UL
  #define DMA_DCR1_DSIZE_BITNUM         0x11U
  #define DMA_DCR1_SSIZE_MASK           0x00300000UL
  #define DMA_DCR1_SSIZE_BITNUM         0x14U
  #define DMA_DCR1                      (*((volatile dword *)0x0000C88E))


  /*** DMA_SAR2 - Source Address Register; 0x0000C890 ***/
  union {
    dword Dword;
  } DMA_SAR2_STR;

  #define DMA_SAR2                      (*((volatile dword *)0x0000C890))


  /*** DMA_DAR2 - Destination Address Register; 0x0000C892 ***/
  union {
    dword Dword;
  } DMA_DAR2_STR;

  #define DMA_DAR2                      (*((volatile dword *)0x0000C892))


  /*** DMA_DSR_BCR2 - DMA Status Register / Byte Count Register; 0x0000C894 ***/
  union {
    dword Dword;
  } DMA_DSR_BCR2_STR;

  #define DMA_DSR_BCR2_BCR0_MASK        0x01UL
  #define DMA_DSR_BCR2_BCR1_MASK        0x02UL
  #define DMA_DSR_BCR2_BCR2_MASK        0x04UL
  #define DMA_DSR_BCR2_BCR3_MASK        0x08UL
  #define DMA_DSR_BCR2_BCR4_MASK        0x10UL
  #define DMA_DSR_BCR2_BCR5_MASK        0x20UL
  #define DMA_DSR_BCR2_BCR6_MASK        0x40UL
  #define DMA_DSR_BCR2_BCR7_MASK        0x80UL
  #define DMA_DSR_BCR2_BCR8_MASK        0x0100UL
  #define DMA_DSR_BCR2_BCR9_MASK        0x0200UL
  #define DMA_DSR_BCR2_BCR10_MASK       0x0400UL
  #define DMA_DSR_BCR2_BCR11_MASK       0x0800UL
  #define DMA_DSR_BCR2_BCR12_MASK       0x1000UL
  #define DMA_DSR_BCR2_BCR13_MASK       0x2000UL
  #define DMA_DSR_BCR2_BCR14_MASK       0x4000UL
  #define DMA_DSR_BCR2_BCR15_MASK       0x8000UL
  #define DMA_DSR_BCR2_BCR16_MASK       0x00010000UL
  #define DMA_DSR_BCR2_BCR17_MASK       0x00020000UL
  #define DMA_DSR_BCR2_BCR18_MASK       0x00040000UL
  #define DMA_DSR_BCR2_BCR19_MASK       0x00080000UL
  #define DMA_DSR_BCR2_BCR20_MASK       0x00100000UL
  #define DMA_DSR_BCR2_BCR21_MASK       0x00200000UL
  #define DMA_DSR_BCR2_BCR22_MASK       0x00400000UL
  #define DMA_DSR_BCR2_BCR23_MASK       0x00800000UL
  #define DMA_DSR_BCR2_DONE_MASK        0x01000000UL
  #define DMA_DSR_BCR2_BSY_MASK         0x02000000UL
  #define DMA_DSR_BCR2_REQ_MASK         0x04000000UL
  #define DMA_DSR_BCR2_BED_MASK         0x10000000UL
  #define DMA_DSR_BCR2_BES_MASK         0x20000000UL
  #define DMA_DSR_BCR2_CE_MASK          0x40000000UL
  #define DMA_DSR_BCR2_BCR_MASK         0x00FFFFFFUL
  #define DMA_DSR_BCR2_BCR_BITNUM       0x00U
  #define DMA_DSR_BCR2                  (*((volatile dword *)0x0000C894))


  /*** DMA_DCR2 - DMA Control Register; 0x0000C896 ***/
  union {
    dword Dword;
  } DMA_DCR2_STR;

  #define DMA_DCR2_LCH20_MASK           0x01UL
  #define DMA_DCR2_LCH21_MASK           0x02UL
  #define DMA_DCR2_LCH10_MASK           0x04UL
  #define DMA_DCR2_LCH11_MASK           0x08UL
  #define DMA_DCR2_LINKCC0_MASK         0x10UL
  #define DMA_DCR2_LINKCC1_MASK         0x20UL
  #define DMA_DCR2_D_REQ_MASK           0x80UL
  #define DMA_DCR2_DMOD0_MASK           0x0100UL
  #define DMA_DCR2_DMOD1_MASK           0x0200UL
  #define DMA_DCR2_DMOD2_MASK           0x0400UL
  #define DMA_DCR2_DMOD3_MASK           0x0800UL
  #define DMA_DCR2_SMOD0_MASK           0x1000UL
  #define DMA_DCR2_SMOD1_MASK           0x2000UL
  #define DMA_DCR2_SMOD2_MASK           0x4000UL
  #define DMA_DCR2_SMOD3_MASK           0x8000UL
  #define DMA_DCR2_START_MASK           0x00010000UL
  #define DMA_DCR2_DSIZE0_MASK          0x00020000UL
  #define DMA_DCR2_DSIZE1_MASK          0x00040000UL
  #define DMA_DCR2_DINC_MASK            0x00080000UL
  #define DMA_DCR2_SSIZE0_MASK          0x00100000UL
  #define DMA_DCR2_SSIZE1_MASK          0x00200000UL
  #define DMA_DCR2_SINC_MASK            0x00400000UL
  #define DMA_DCR2_AA_MASK              0x10000000UL
  #define DMA_DCR2_CS_MASK              0x20000000UL
  #define DMA_DCR2_ERQ_MASK             0x40000000UL
  #define DMA_DCR2_EINT_MASK            0x80000000UL
  #define DMA_DCR2_LCH2_MASK            0x03UL
  #define DMA_DCR2_LCH2_BITNUM          0x00U
  #define DMA_DCR2_LCH1_MASK            0x0CUL
  #define DMA_DCR2_LCH1_BITNUM          0x02U
  #define DMA_DCR2_LINKCC_MASK          0x30UL
  #define DMA_DCR2_LINKCC_BITNUM        0x04U
  #define DMA_DCR2_DMOD_MASK            0x0F00UL
  #define DMA_DCR2_DMOD_BITNUM          0x08U
  #define DMA_DCR2_SMOD_MASK            0xF000UL
  #define DMA_DCR2_SMOD_BITNUM          0x0CU
  #define DMA_DCR2_DSIZE_MASK           0x00060000UL
  #define DMA_DCR2_DSIZE_BITNUM         0x11U
  #define DMA_DCR2_SSIZE_MASK           0x00300000UL
  #define DMA_DCR2_SSIZE_BITNUM         0x14U
  #define DMA_DCR2                      (*((volatile dword *)0x0000C896))


  /*** DMA_SAR3 - Source Address Register; 0x0000C898 ***/
  union {
    dword Dword;
  } DMA_SAR3_STR;

  #define DMA_SAR3                      (*((volatile dword *)0x0000C898))


  /*** DMA_DAR3 - Destination Address Register; 0x0000C89A ***/
  union {
    dword Dword;
  } DMA_DAR3_STR;

  #define DMA_DAR3                      (*((volatile dword *)0x0000C89A))


  /*** DMA_DSR_BCR3 - DMA Status Register / Byte Count Register; 0x0000C89C ***/
  union {
    dword Dword;
  } DMA_DSR_BCR3_STR;

  #define DMA_DSR_BCR3_BCR0_MASK        0x01UL
  #define DMA_DSR_BCR3_BCR1_MASK        0x02UL
  #define DMA_DSR_BCR3_BCR2_MASK        0x04UL
  #define DMA_DSR_BCR3_BCR3_MASK        0x08UL
  #define DMA_DSR_BCR3_BCR4_MASK        0x10UL
  #define DMA_DSR_BCR3_BCR5_MASK        0x20UL
  #define DMA_DSR_BCR3_BCR6_MASK        0x40UL
  #define DMA_DSR_BCR3_BCR7_MASK        0x80UL
  #define DMA_DSR_BCR3_BCR8_MASK        0x0100UL
  #define DMA_DSR_BCR3_BCR9_MASK        0x0200UL
  #define DMA_DSR_BCR3_BCR10_MASK       0x0400UL
  #define DMA_DSR_BCR3_BCR11_MASK       0x0800UL
  #define DMA_DSR_BCR3_BCR12_MASK       0x1000UL
  #define DMA_DSR_BCR3_BCR13_MASK       0x2000UL
  #define DMA_DSR_BCR3_BCR14_MASK       0x4000UL
  #define DMA_DSR_BCR3_BCR15_MASK       0x8000UL
  #define DMA_DSR_BCR3_BCR16_MASK       0x00010000UL
  #define DMA_DSR_BCR3_BCR17_MASK       0x00020000UL
  #define DMA_DSR_BCR3_BCR18_MASK       0x00040000UL
  #define DMA_DSR_BCR3_BCR19_MASK       0x00080000UL
  #define DMA_DSR_BCR3_BCR20_MASK       0x00100000UL
  #define DMA_DSR_BCR3_BCR21_MASK       0x00200000UL
  #define DMA_DSR_BCR3_BCR22_MASK       0x00400000UL
  #define DMA_DSR_BCR3_BCR23_MASK       0x00800000UL
  #define DMA_DSR_BCR3_DONE_MASK        0x01000000UL
  #define DMA_DSR_BCR3_BSY_MASK         0x02000000UL
  #define DMA_DSR_BCR3_REQ_MASK         0x04000000UL
  #define DMA_DSR_BCR3_BED_MASK         0x10000000UL
  #define DMA_DSR_BCR3_BES_MASK         0x20000000UL
  #define DMA_DSR_BCR3_CE_MASK          0x40000000UL
  #define DMA_DSR_BCR3_BCR_MASK         0x00FFFFFFUL
  #define DMA_DSR_BCR3_BCR_BITNUM       0x00U
  #define DMA_DSR_BCR3                  (*((volatile dword *)0x0000C89C))


  /*** DMA_DCR3 - DMA Control Register; 0x0000C89E ***/
  union {
    dword Dword;
  } DMA_DCR3_STR;

  #define DMA_DCR3_LCH20_MASK           0x01UL
  #define DMA_DCR3_LCH21_MASK           0x02UL
  #define DMA_DCR3_LCH10_MASK           0x04UL
  #define DMA_DCR3_LCH11_MASK           0x08UL
  #define DMA_DCR3_LINKCC0_MASK         0x10UL
  #define DMA_DCR3_LINKCC1_MASK         0x20UL
  #define DMA_DCR3_D_REQ_MASK           0x80UL
  #define DMA_DCR3_DMOD0_MASK           0x0100UL
  #define DMA_DCR3_DMOD1_MASK           0x0200UL
  #define DMA_DCR3_DMOD2_MASK           0x0400UL
  #define DMA_DCR3_DMOD3_MASK           0x0800UL
  #define DMA_DCR3_SMOD0_MASK           0x1000UL
  #define DMA_DCR3_SMOD1_MASK           0x2000UL
  #define DMA_DCR3_SMOD2_MASK           0x4000UL
  #define DMA_DCR3_SMOD3_MASK           0x8000UL
  #define DMA_DCR3_START_MASK           0x00010000UL
  #define DMA_DCR3_DSIZE0_MASK          0x00020000UL
  #define DMA_DCR3_DSIZE1_MASK          0x00040000UL
  #define DMA_DCR3_DINC_MASK            0x00080000UL
  #define DMA_DCR3_SSIZE0_MASK          0x00100000UL
  #define DMA_DCR3_SSIZE1_MASK          0x00200000UL
  #define DMA_DCR3_SINC_MASK            0x00400000UL
  #define DMA_DCR3_AA_MASK              0x10000000UL
  #define DMA_DCR3_CS_MASK              0x20000000UL
  #define DMA_DCR3_ERQ_MASK             0x40000000UL
  #define DMA_DCR3_EINT_MASK            0x80000000UL
  #define DMA_DCR3_LCH2_MASK            0x03UL
  #define DMA_DCR3_LCH2_BITNUM          0x00U
  #define DMA_DCR3_LCH1_MASK            0x0CUL
  #define DMA_DCR3_LCH1_BITNUM          0x02U
  #define DMA_DCR3_LINKCC_MASK          0x30UL
  #define DMA_DCR3_LINKCC_BITNUM        0x04U
  #define DMA_DCR3_DMOD_MASK            0x0F00UL
  #define DMA_DCR3_DMOD_BITNUM          0x08U
  #define DMA_DCR3_SMOD_MASK            0xF000UL
  #define DMA_DCR3_SMOD_BITNUM          0x0CU
  #define DMA_DCR3_DSIZE_MASK           0x00060000UL
  #define DMA_DCR3_DSIZE_BITNUM         0x11U
  #define DMA_DCR3_SSIZE_MASK           0x00300000UL
  #define DMA_DCR3_SSIZE_BITNUM         0x14U
  #define DMA_DCR3                      (*((volatile dword *)0x0000C89E))


} DMA_PRPH;
/******************************************
*** Peripheral FMC
*******************************************/
typedef volatile struct {
  /*** FMC_PFAPR - Flash Access Protection Register; 0x0000DE00 ***/
  union {
    dword Dword;
  } FMC_PFAPR_STR;

  #define FMC_PFAPR_M0AP0_MASK          0x01UL
  #define FMC_PFAPR_M0AP1_MASK          0x02UL
  #define FMC_PFAPR_M1AP0_MASK          0x04UL
  #define FMC_PFAPR_M1AP1_MASK          0x08UL
  #define FMC_PFAPR_M2AP0_MASK          0x10UL
  #define FMC_PFAPR_M2AP1_MASK          0x20UL
  #define FMC_PFAPR_M3AP0_MASK          0x40UL
  #define FMC_PFAPR_M3AP1_MASK          0x80UL
  #define FMC_PFAPR_M0PFD_MASK          0x00010000UL
  #define FMC_PFAPR_M1PFD_MASK          0x00020000UL
  #define FMC_PFAPR_M2PFD_MASK          0x00040000UL
  #define FMC_PFAPR_M3PFD_MASK          0x00080000UL
  #define FMC_PFAPR_M0AP_MASK           0x03UL
  #define FMC_PFAPR_M0AP_BITNUM         0x00U
  #define FMC_PFAPR_M1AP_MASK           0x0CUL
  #define FMC_PFAPR_M1AP_BITNUM         0x02U
  #define FMC_PFAPR_M2AP_MASK           0x30UL
  #define FMC_PFAPR_M2AP_BITNUM         0x04U
  #define FMC_PFAPR_M3AP_MASK           0xC0UL
  #define FMC_PFAPR_M3AP_BITNUM         0x06U
  #define FMC_PFAPR                     (*((volatile dword *)0x0000DE00))


  /*** FMC_PFB0CR - Flash Bank 0 Control Register; 0x0000DE02 ***/
  union {
    dword Dword;
  } FMC_PFB0CR_STR;

  #define FMC_PFB0CR_B0SEBE_MASK        0x01UL
  #define FMC_PFB0CR_B0IPE_MASK         0x02UL
  #define FMC_PFB0CR_B0DPE_MASK         0x04UL
  #define FMC_PFB0CR_B0ICE_MASK         0x08UL
  #define FMC_PFB0CR_B0DCE_MASK         0x10UL
  #define FMC_PFB0CR_CRC0_MASK          0x20UL
  #define FMC_PFB0CR_CRC1_MASK          0x40UL
  #define FMC_PFB0CR_CRC2_MASK          0x80UL
  #define FMC_PFB0CR_B0MW0_MASK         0x00020000UL
  #define FMC_PFB0CR_B0MW1_MASK         0x00040000UL
  #define FMC_PFB0CR_S_B_INV_MASK       0x00080000UL
  #define FMC_PFB0CR_CINV_WAY0_MASK     0x00100000UL
  #define FMC_PFB0CR_CINV_WAY1_MASK     0x00200000UL
  #define FMC_PFB0CR_CINV_WAY2_MASK     0x00400000UL
  #define FMC_PFB0CR_CINV_WAY3_MASK     0x00800000UL
  #define FMC_PFB0CR_CLCK_WAY0_MASK     0x01000000UL
  #define FMC_PFB0CR_CLCK_WAY1_MASK     0x02000000UL
  #define FMC_PFB0CR_CLCK_WAY2_MASK     0x04000000UL
  #define FMC_PFB0CR_CLCK_WAY3_MASK     0x08000000UL
  #define FMC_PFB0CR_B0RWSC0_MASK       0x10000000UL
  #define FMC_PFB0CR_B0RWSC1_MASK       0x20000000UL
  #define FMC_PFB0CR_B0RWSC2_MASK       0x40000000UL
  #define FMC_PFB0CR_B0RWSC3_MASK       0x80000000UL
  #define FMC_PFB0CR_CRC_MASK           0xE0UL
  #define FMC_PFB0CR_CRC_BITNUM         0x05U
  #define FMC_PFB0CR_B0MW_MASK          0x00060000UL
  #define FMC_PFB0CR_B0MW_BITNUM        0x11U
  #define FMC_PFB0CR_CINV_WAY_MASK      0x00F00000UL
  #define FMC_PFB0CR_CINV_WAY_BITNUM    0x14U
  #define FMC_PFB0CR_CLCK_WAY_MASK      0x0F000000UL
  #define FMC_PFB0CR_CLCK_WAY_BITNUM    0x18U
  #define FMC_PFB0CR_B0RWSC_MASK        0xF0000000UL
  #define FMC_PFB0CR_B0RWSC_BITNUM      0x1CU
  #define FMC_PFB0CR                    (*((volatile dword *)0x0000DE02))


  /*** FMC_PFB1CR - Flash Bank 1 Control Register; 0x0000DE04 ***/
  union {
    dword Dword;
  } FMC_PFB1CR_STR;

  #define FMC_PFB1CR_B1MW0_MASK         0x00020000UL
  #define FMC_PFB1CR_B1MW1_MASK         0x00040000UL
  #define FMC_PFB1CR_B1RWSC0_MASK       0x10000000UL
  #define FMC_PFB1CR_B1RWSC1_MASK       0x20000000UL
  #define FMC_PFB1CR_B1RWSC2_MASK       0x40000000UL
  #define FMC_PFB1CR_B1RWSC3_MASK       0x80000000UL
  #define FMC_PFB1CR_B1MW_MASK          0x00060000UL
  #define FMC_PFB1CR_B1MW_BITNUM        0x11U
  #define FMC_PFB1CR_B1RWSC_MASK        0xF0000000UL
  #define FMC_PFB1CR_B1RWSC_BITNUM      0x1CU
  #define FMC_PFB1CR                    (*((volatile dword *)0x0000DE04))


  dword Reserved0[61];                 /* Reserved (unused) registers */

  /*** FMC_TAGVDW0S0 - Cache Tag Storage; 0x0000DE80 ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S0_STR;

  #define FMC_TAGVDW0S0_valid_MASK      0x01UL
  #define FMC_TAGVDW0S0_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S0_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S0_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S0_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S0_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S0_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S0_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S0_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S0_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S0_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S0_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S0_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S0_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S0_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S0_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S0                 (*((volatile dword *)0x0000DE80))


  /*** FMC_TAGVDW0S1 - Cache Tag Storage; 0x0000DE82 ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S1_STR;

  #define FMC_TAGVDW0S1_valid_MASK      0x01UL
  #define FMC_TAGVDW0S1_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S1_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S1_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S1_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S1_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S1_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S1_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S1_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S1_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S1_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S1_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S1_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S1_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S1_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S1_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S1                 (*((volatile dword *)0x0000DE82))


  /*** FMC_TAGVDW0S2 - Cache Tag Storage; 0x0000DE84 ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S2_STR;

  #define FMC_TAGVDW0S2_valid_MASK      0x01UL
  #define FMC_TAGVDW0S2_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S2_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S2_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S2_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S2_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S2_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S2_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S2_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S2_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S2_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S2_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S2_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S2_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S2_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S2_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S2                 (*((volatile dword *)0x0000DE84))


  /*** FMC_TAGVDW0S3 - Cache Tag Storage; 0x0000DE86 ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S3_STR;

  #define FMC_TAGVDW0S3_valid_MASK      0x01UL
  #define FMC_TAGVDW0S3_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S3_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S3_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S3_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S3_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S3_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S3_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S3_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S3_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S3_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S3_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S3_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S3_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S3_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S3_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S3                 (*((volatile dword *)0x0000DE86))


  /*** FMC_TAGVDW0S4 - Cache Tag Storage; 0x0000DE88 ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S4_STR;

  #define FMC_TAGVDW0S4_valid_MASK      0x01UL
  #define FMC_TAGVDW0S4_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S4_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S4_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S4_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S4_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S4_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S4_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S4_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S4_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S4_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S4_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S4_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S4_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S4_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S4_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S4                 (*((volatile dword *)0x0000DE88))


  /*** FMC_TAGVDW0S5 - Cache Tag Storage; 0x0000DE8A ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S5_STR;

  #define FMC_TAGVDW0S5_valid_MASK      0x01UL
  #define FMC_TAGVDW0S5_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S5_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S5_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S5_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S5_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S5_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S5_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S5_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S5_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S5_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S5_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S5_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S5_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S5_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S5_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S5                 (*((volatile dword *)0x0000DE8A))


  /*** FMC_TAGVDW0S6 - Cache Tag Storage; 0x0000DE8C ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S6_STR;

  #define FMC_TAGVDW0S6_valid_MASK      0x01UL
  #define FMC_TAGVDW0S6_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S6_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S6_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S6_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S6_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S6_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S6_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S6_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S6_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S6_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S6_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S6_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S6_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S6_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S6_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S6                 (*((volatile dword *)0x0000DE8C))


  /*** FMC_TAGVDW0S7 - Cache Tag Storage; 0x0000DE8E ***/
  union {
    dword Dword;
  } FMC_TAGVDW0S7_STR;

  #define FMC_TAGVDW0S7_valid_MASK      0x01UL
  #define FMC_TAGVDW0S7_tag0_MASK       0x40UL
  #define FMC_TAGVDW0S7_tag1_MASK       0x80UL
  #define FMC_TAGVDW0S7_tag2_MASK       0x0100UL
  #define FMC_TAGVDW0S7_tag3_MASK       0x0200UL
  #define FMC_TAGVDW0S7_tag4_MASK       0x0400UL
  #define FMC_TAGVDW0S7_tag5_MASK       0x0800UL
  #define FMC_TAGVDW0S7_tag6_MASK       0x1000UL
  #define FMC_TAGVDW0S7_tag7_MASK       0x2000UL
  #define FMC_TAGVDW0S7_tag8_MASK       0x4000UL
  #define FMC_TAGVDW0S7_tag9_MASK       0x8000UL
  #define FMC_TAGVDW0S7_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW0S7_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW0S7_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW0S7_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW0S7_tag_BITNUM      0x06U
  #define FMC_TAGVDW0S7                 (*((volatile dword *)0x0000DE8E))


  /*** FMC_TAGVDW1S0 - Cache Tag Storage; 0x0000DE90 ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S0_STR;

  #define FMC_TAGVDW1S0_valid_MASK      0x01UL
  #define FMC_TAGVDW1S0_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S0_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S0_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S0_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S0_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S0_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S0_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S0_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S0_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S0_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S0_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S0_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S0_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S0_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S0_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S0                 (*((volatile dword *)0x0000DE90))


  /*** FMC_TAGVDW1S1 - Cache Tag Storage; 0x0000DE92 ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S1_STR;

  #define FMC_TAGVDW1S1_valid_MASK      0x01UL
  #define FMC_TAGVDW1S1_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S1_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S1_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S1_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S1_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S1_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S1_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S1_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S1_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S1_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S1_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S1_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S1_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S1_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S1_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S1                 (*((volatile dword *)0x0000DE92))


  /*** FMC_TAGVDW1S2 - Cache Tag Storage; 0x0000DE94 ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S2_STR;

  #define FMC_TAGVDW1S2_valid_MASK      0x01UL
  #define FMC_TAGVDW1S2_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S2_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S2_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S2_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S2_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S2_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S2_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S2_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S2_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S2_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S2_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S2_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S2_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S2_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S2_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S2                 (*((volatile dword *)0x0000DE94))


  /*** FMC_TAGVDW1S3 - Cache Tag Storage; 0x0000DE96 ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S3_STR;

  #define FMC_TAGVDW1S3_valid_MASK      0x01UL
  #define FMC_TAGVDW1S3_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S3_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S3_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S3_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S3_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S3_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S3_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S3_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S3_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S3_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S3_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S3_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S3_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S3_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S3_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S3                 (*((volatile dword *)0x0000DE96))


  /*** FMC_TAGVDW1S4 - Cache Tag Storage; 0x0000DE98 ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S4_STR;

  #define FMC_TAGVDW1S4_valid_MASK      0x01UL
  #define FMC_TAGVDW1S4_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S4_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S4_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S4_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S4_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S4_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S4_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S4_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S4_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S4_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S4_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S4_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S4_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S4_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S4_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S4                 (*((volatile dword *)0x0000DE98))


  /*** FMC_TAGVDW1S5 - Cache Tag Storage; 0x0000DE9A ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S5_STR;

  #define FMC_TAGVDW1S5_valid_MASK      0x01UL
  #define FMC_TAGVDW1S5_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S5_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S5_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S5_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S5_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S5_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S5_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S5_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S5_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S5_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S5_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S5_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S5_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S5_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S5_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S5                 (*((volatile dword *)0x0000DE9A))


  /*** FMC_TAGVDW1S6 - Cache Tag Storage; 0x0000DE9C ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S6_STR;

  #define FMC_TAGVDW1S6_valid_MASK      0x01UL
  #define FMC_TAGVDW1S6_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S6_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S6_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S6_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S6_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S6_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S6_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S6_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S6_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S6_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S6_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S6_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S6_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S6_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S6_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S6                 (*((volatile dword *)0x0000DE9C))


  /*** FMC_TAGVDW1S7 - Cache Tag Storage; 0x0000DE9E ***/
  union {
    dword Dword;
  } FMC_TAGVDW1S7_STR;

  #define FMC_TAGVDW1S7_valid_MASK      0x01UL
  #define FMC_TAGVDW1S7_tag0_MASK       0x40UL
  #define FMC_TAGVDW1S7_tag1_MASK       0x80UL
  #define FMC_TAGVDW1S7_tag2_MASK       0x0100UL
  #define FMC_TAGVDW1S7_tag3_MASK       0x0200UL
  #define FMC_TAGVDW1S7_tag4_MASK       0x0400UL
  #define FMC_TAGVDW1S7_tag5_MASK       0x0800UL
  #define FMC_TAGVDW1S7_tag6_MASK       0x1000UL
  #define FMC_TAGVDW1S7_tag7_MASK       0x2000UL
  #define FMC_TAGVDW1S7_tag8_MASK       0x4000UL
  #define FMC_TAGVDW1S7_tag9_MASK       0x8000UL
  #define FMC_TAGVDW1S7_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW1S7_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW1S7_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW1S7_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW1S7_tag_BITNUM      0x06U
  #define FMC_TAGVDW1S7                 (*((volatile dword *)0x0000DE9E))


  /*** FMC_TAGVDW2S0 - Cache Tag Storage; 0x0000DEA0 ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S0_STR;

  #define FMC_TAGVDW2S0_valid_MASK      0x01UL
  #define FMC_TAGVDW2S0_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S0_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S0_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S0_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S0_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S0_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S0_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S0_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S0_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S0_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S0_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S0_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S0_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S0_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S0_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S0                 (*((volatile dword *)0x0000DEA0))


  /*** FMC_TAGVDW2S1 - Cache Tag Storage; 0x0000DEA2 ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S1_STR;

  #define FMC_TAGVDW2S1_valid_MASK      0x01UL
  #define FMC_TAGVDW2S1_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S1_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S1_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S1_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S1_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S1_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S1_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S1_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S1_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S1_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S1_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S1_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S1_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S1_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S1_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S1                 (*((volatile dword *)0x0000DEA2))


  /*** FMC_TAGVDW2S2 - Cache Tag Storage; 0x0000DEA4 ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S2_STR;

  #define FMC_TAGVDW2S2_valid_MASK      0x01UL
  #define FMC_TAGVDW2S2_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S2_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S2_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S2_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S2_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S2_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S2_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S2_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S2_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S2_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S2_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S2_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S2_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S2_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S2_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S2                 (*((volatile dword *)0x0000DEA4))


  /*** FMC_TAGVDW2S3 - Cache Tag Storage; 0x0000DEA6 ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S3_STR;

  #define FMC_TAGVDW2S3_valid_MASK      0x01UL
  #define FMC_TAGVDW2S3_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S3_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S3_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S3_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S3_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S3_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S3_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S3_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S3_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S3_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S3_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S3_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S3_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S3_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S3_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S3                 (*((volatile dword *)0x0000DEA6))


  /*** FMC_TAGVDW2S4 - Cache Tag Storage; 0x0000DEA8 ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S4_STR;

  #define FMC_TAGVDW2S4_valid_MASK      0x01UL
  #define FMC_TAGVDW2S4_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S4_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S4_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S4_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S4_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S4_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S4_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S4_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S4_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S4_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S4_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S4_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S4_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S4_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S4_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S4                 (*((volatile dword *)0x0000DEA8))


  /*** FMC_TAGVDW2S5 - Cache Tag Storage; 0x0000DEAA ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S5_STR;

  #define FMC_TAGVDW2S5_valid_MASK      0x01UL
  #define FMC_TAGVDW2S5_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S5_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S5_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S5_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S5_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S5_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S5_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S5_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S5_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S5_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S5_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S5_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S5_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S5_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S5_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S5                 (*((volatile dword *)0x0000DEAA))


  /*** FMC_TAGVDW2S6 - Cache Tag Storage; 0x0000DEAC ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S6_STR;

  #define FMC_TAGVDW2S6_valid_MASK      0x01UL
  #define FMC_TAGVDW2S6_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S6_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S6_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S6_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S6_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S6_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S6_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S6_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S6_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S6_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S6_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S6_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S6_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S6_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S6_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S6                 (*((volatile dword *)0x0000DEAC))


  /*** FMC_TAGVDW2S7 - Cache Tag Storage; 0x0000DEAE ***/
  union {
    dword Dword;
  } FMC_TAGVDW2S7_STR;

  #define FMC_TAGVDW2S7_valid_MASK      0x01UL
  #define FMC_TAGVDW2S7_tag0_MASK       0x40UL
  #define FMC_TAGVDW2S7_tag1_MASK       0x80UL
  #define FMC_TAGVDW2S7_tag2_MASK       0x0100UL
  #define FMC_TAGVDW2S7_tag3_MASK       0x0200UL
  #define FMC_TAGVDW2S7_tag4_MASK       0x0400UL
  #define FMC_TAGVDW2S7_tag5_MASK       0x0800UL
  #define FMC_TAGVDW2S7_tag6_MASK       0x1000UL
  #define FMC_TAGVDW2S7_tag7_MASK       0x2000UL
  #define FMC_TAGVDW2S7_tag8_MASK       0x4000UL
  #define FMC_TAGVDW2S7_tag9_MASK       0x8000UL
  #define FMC_TAGVDW2S7_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW2S7_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW2S7_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW2S7_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW2S7_tag_BITNUM      0x06U
  #define FMC_TAGVDW2S7                 (*((volatile dword *)0x0000DEAE))


  /*** FMC_TAGVDW3S0 - Cache Tag Storage; 0x0000DEB0 ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S0_STR;

  #define FMC_TAGVDW3S0_valid_MASK      0x01UL
  #define FMC_TAGVDW3S0_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S0_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S0_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S0_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S0_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S0_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S0_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S0_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S0_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S0_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S0_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S0_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S0_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S0_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S0_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S0                 (*((volatile dword *)0x0000DEB0))


  /*** FMC_TAGVDW3S1 - Cache Tag Storage; 0x0000DEB2 ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S1_STR;

  #define FMC_TAGVDW3S1_valid_MASK      0x01UL
  #define FMC_TAGVDW3S1_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S1_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S1_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S1_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S1_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S1_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S1_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S1_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S1_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S1_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S1_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S1_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S1_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S1_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S1_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S1                 (*((volatile dword *)0x0000DEB2))


  /*** FMC_TAGVDW3S2 - Cache Tag Storage; 0x0000DEB4 ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S2_STR;

  #define FMC_TAGVDW3S2_valid_MASK      0x01UL
  #define FMC_TAGVDW3S2_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S2_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S2_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S2_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S2_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S2_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S2_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S2_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S2_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S2_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S2_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S2_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S2_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S2_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S2_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S2                 (*((volatile dword *)0x0000DEB4))


  /*** FMC_TAGVDW3S3 - Cache Tag Storage; 0x0000DEB6 ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S3_STR;

  #define FMC_TAGVDW3S3_valid_MASK      0x01UL
  #define FMC_TAGVDW3S3_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S3_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S3_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S3_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S3_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S3_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S3_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S3_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S3_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S3_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S3_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S3_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S3_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S3_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S3_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S3                 (*((volatile dword *)0x0000DEB6))


  /*** FMC_TAGVDW3S4 - Cache Tag Storage; 0x0000DEB8 ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S4_STR;

  #define FMC_TAGVDW3S4_valid_MASK      0x01UL
  #define FMC_TAGVDW3S4_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S4_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S4_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S4_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S4_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S4_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S4_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S4_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S4_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S4_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S4_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S4_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S4_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S4_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S4_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S4                 (*((volatile dword *)0x0000DEB8))


  /*** FMC_TAGVDW3S5 - Cache Tag Storage; 0x0000DEBA ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S5_STR;

  #define FMC_TAGVDW3S5_valid_MASK      0x01UL
  #define FMC_TAGVDW3S5_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S5_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S5_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S5_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S5_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S5_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S5_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S5_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S5_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S5_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S5_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S5_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S5_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S5_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S5_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S5                 (*((volatile dword *)0x0000DEBA))


  /*** FMC_TAGVDW3S6 - Cache Tag Storage; 0x0000DEBC ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S6_STR;

  #define FMC_TAGVDW3S6_valid_MASK      0x01UL
  #define FMC_TAGVDW3S6_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S6_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S6_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S6_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S6_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S6_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S6_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S6_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S6_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S6_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S6_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S6_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S6_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S6_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S6_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S6                 (*((volatile dword *)0x0000DEBC))


  /*** FMC_TAGVDW3S7 - Cache Tag Storage; 0x0000DEBE ***/
  union {
    dword Dword;
  } FMC_TAGVDW3S7_STR;

  #define FMC_TAGVDW3S7_valid_MASK      0x01UL
  #define FMC_TAGVDW3S7_tag0_MASK       0x40UL
  #define FMC_TAGVDW3S7_tag1_MASK       0x80UL
  #define FMC_TAGVDW3S7_tag2_MASK       0x0100UL
  #define FMC_TAGVDW3S7_tag3_MASK       0x0200UL
  #define FMC_TAGVDW3S7_tag4_MASK       0x0400UL
  #define FMC_TAGVDW3S7_tag5_MASK       0x0800UL
  #define FMC_TAGVDW3S7_tag6_MASK       0x1000UL
  #define FMC_TAGVDW3S7_tag7_MASK       0x2000UL
  #define FMC_TAGVDW3S7_tag8_MASK       0x4000UL
  #define FMC_TAGVDW3S7_tag9_MASK       0x8000UL
  #define FMC_TAGVDW3S7_tag10_MASK      0x00010000UL
  #define FMC_TAGVDW3S7_tag11_MASK      0x00020000UL
  #define FMC_TAGVDW3S7_tag12_MASK      0x00040000UL
  #define FMC_TAGVDW3S7_tag_MASK        0x0007FFC0UL
  #define FMC_TAGVDW3S7_tag_BITNUM      0x06U
  #define FMC_TAGVDW3S7                 (*((volatile dword *)0x0000DEBE))


  dword Reserved1[32];                 /* Reserved (unused) registers */

  /*** FMC_DATAW0S0U - Cache Data Storage (upper word); 0x0000DF00 ***/
  union {
    dword Dword;
  } FMC_DATAW0S0U_STR;

  #define FMC_DATAW0S0U                 (*((volatile dword *)0x0000DF00))


  /*** FMC_DATAW0S0L - Cache Data Storage (lower word); 0x0000DF02 ***/
  union {
    dword Dword;
  } FMC_DATAW0S0L_STR;

  #define FMC_DATAW0S0L                 (*((volatile dword *)0x0000DF02))


  /*** FMC_DATAW0S1U - Cache Data Storage (upper word); 0x0000DF04 ***/
  union {
    dword Dword;
  } FMC_DATAW0S1U_STR;

  #define FMC_DATAW0S1U                 (*((volatile dword *)0x0000DF04))


  /*** FMC_DATAW0S1L - Cache Data Storage (lower word); 0x0000DF06 ***/
  union {
    dword Dword;
  } FMC_DATAW0S1L_STR;

  #define FMC_DATAW0S1L                 (*((volatile dword *)0x0000DF06))


  /*** FMC_DATAW0S2U - Cache Data Storage (upper word); 0x0000DF08 ***/
  union {
    dword Dword;
  } FMC_DATAW0S2U_STR;

  #define FMC_DATAW0S2U                 (*((volatile dword *)0x0000DF08))


  /*** FMC_DATAW0S2L - Cache Data Storage (lower word); 0x0000DF0A ***/
  union {
    dword Dword;
  } FMC_DATAW0S2L_STR;

  #define FMC_DATAW0S2L                 (*((volatile dword *)0x0000DF0A))


  /*** FMC_DATAW0S3U - Cache Data Storage (upper word); 0x0000DF0C ***/
  union {
    dword Dword;
  } FMC_DATAW0S3U_STR;

  #define FMC_DATAW0S3U                 (*((volatile dword *)0x0000DF0C))


  /*** FMC_DATAW0S3L - Cache Data Storage (lower word); 0x0000DF0E ***/
  union {
    dword Dword;
  } FMC_DATAW0S3L_STR;

  #define FMC_DATAW0S3L                 (*((volatile dword *)0x0000DF0E))


  /*** FMC_DATAW0S4U - Cache Data Storage (upper word); 0x0000DF10 ***/
  union {
    dword Dword;
  } FMC_DATAW0S4U_STR;

  #define FMC_DATAW0S4U                 (*((volatile dword *)0x0000DF10))


  /*** FMC_DATAW0S4L - Cache Data Storage (lower word); 0x0000DF12 ***/
  union {
    dword Dword;
  } FMC_DATAW0S4L_STR;

  #define FMC_DATAW0S4L                 (*((volatile dword *)0x0000DF12))


  /*** FMC_DATAW0S5U - Cache Data Storage (upper word); 0x0000DF14 ***/
  union {
    dword Dword;
  } FMC_DATAW0S5U_STR;

  #define FMC_DATAW0S5U                 (*((volatile dword *)0x0000DF14))


  /*** FMC_DATAW0S5L - Cache Data Storage (lower word); 0x0000DF16 ***/
  union {
    dword Dword;
  } FMC_DATAW0S5L_STR;

  #define FMC_DATAW0S5L                 (*((volatile dword *)0x0000DF16))


  /*** FMC_DATAW0S6U - Cache Data Storage (upper word); 0x0000DF18 ***/
  union {
    dword Dword;
  } FMC_DATAW0S6U_STR;

  #define FMC_DATAW0S6U                 (*((volatile dword *)0x0000DF18))


  /*** FMC_DATAW0S6L - Cache Data Storage (lower word); 0x0000DF1A ***/
  union {
    dword Dword;
  } FMC_DATAW0S6L_STR;

  #define FMC_DATAW0S6L                 (*((volatile dword *)0x0000DF1A))


  /*** FMC_DATAW0S7U - Cache Data Storage (upper word); 0x0000DF1C ***/
  union {
    dword Dword;
  } FMC_DATAW0S7U_STR;

  #define FMC_DATAW0S7U                 (*((volatile dword *)0x0000DF1C))


  /*** FMC_DATAW0S7L - Cache Data Storage (lower word); 0x0000DF1E ***/
  union {
    dword Dword;
  } FMC_DATAW0S7L_STR;

  #define FMC_DATAW0S7L                 (*((volatile dword *)0x0000DF1E))


  /*** FMC_DATAW1S0U - Cache Data Storage (upper word); 0x0000DF20 ***/
  union {
    dword Dword;
  } FMC_DATAW1S0U_STR;

  #define FMC_DATAW1S0U                 (*((volatile dword *)0x0000DF20))


  /*** FMC_DATAW1S0L - Cache Data Storage (lower word); 0x0000DF22 ***/
  union {
    dword Dword;
  } FMC_DATAW1S0L_STR;

  #define FMC_DATAW1S0L                 (*((volatile dword *)0x0000DF22))


  /*** FMC_DATAW1S1U - Cache Data Storage (upper word); 0x0000DF24 ***/
  union {
    dword Dword;
  } FMC_DATAW1S1U_STR;

  #define FMC_DATAW1S1U                 (*((volatile dword *)0x0000DF24))


  /*** FMC_DATAW1S1L - Cache Data Storage (lower word); 0x0000DF26 ***/
  union {
    dword Dword;
  } FMC_DATAW1S1L_STR;

  #define FMC_DATAW1S1L                 (*((volatile dword *)0x0000DF26))


  /*** FMC_DATAW1S2U - Cache Data Storage (upper word); 0x0000DF28 ***/
  union {
    dword Dword;
  } FMC_DATAW1S2U_STR;

  #define FMC_DATAW1S2U                 (*((volatile dword *)0x0000DF28))


  /*** FMC_DATAW1S2L - Cache Data Storage (lower word); 0x0000DF2A ***/
  union {
    dword Dword;
  } FMC_DATAW1S2L_STR;

  #define FMC_DATAW1S2L                 (*((volatile dword *)0x0000DF2A))


  /*** FMC_DATAW1S3U - Cache Data Storage (upper word); 0x0000DF2C ***/
  union {
    dword Dword;
  } FMC_DATAW1S3U_STR;

  #define FMC_DATAW1S3U                 (*((volatile dword *)0x0000DF2C))


  /*** FMC_DATAW1S3L - Cache Data Storage (lower word); 0x0000DF2E ***/
  union {
    dword Dword;
  } FMC_DATAW1S3L_STR;

  #define FMC_DATAW1S3L                 (*((volatile dword *)0x0000DF2E))


  /*** FMC_DATAW1S4U - Cache Data Storage (upper word); 0x0000DF30 ***/
  union {
    dword Dword;
  } FMC_DATAW1S4U_STR;

  #define FMC_DATAW1S4U                 (*((volatile dword *)0x0000DF30))


  /*** FMC_DATAW1S4L - Cache Data Storage (lower word); 0x0000DF32 ***/
  union {
    dword Dword;
  } FMC_DATAW1S4L_STR;

  #define FMC_DATAW1S4L                 (*((volatile dword *)0x0000DF32))


  /*** FMC_DATAW1S5U - Cache Data Storage (upper word); 0x0000DF34 ***/
  union {
    dword Dword;
  } FMC_DATAW1S5U_STR;

  #define FMC_DATAW1S5U                 (*((volatile dword *)0x0000DF34))


  /*** FMC_DATAW1S5L - Cache Data Storage (lower word); 0x0000DF36 ***/
  union {
    dword Dword;
  } FMC_DATAW1S5L_STR;

  #define FMC_DATAW1S5L                 (*((volatile dword *)0x0000DF36))


  /*** FMC_DATAW1S6U - Cache Data Storage (upper word); 0x0000DF38 ***/
  union {
    dword Dword;
  } FMC_DATAW1S6U_STR;

  #define FMC_DATAW1S6U                 (*((volatile dword *)0x0000DF38))


  /*** FMC_DATAW1S6L - Cache Data Storage (lower word); 0x0000DF3A ***/
  union {
    dword Dword;
  } FMC_DATAW1S6L_STR;

  #define FMC_DATAW1S6L                 (*((volatile dword *)0x0000DF3A))


  /*** FMC_DATAW1S7U - Cache Data Storage (upper word); 0x0000DF3C ***/
  union {
    dword Dword;
  } FMC_DATAW1S7U_STR;

  #define FMC_DATAW1S7U                 (*((volatile dword *)0x0000DF3C))


  /*** FMC_DATAW1S7L - Cache Data Storage (lower word); 0x0000DF3E ***/
  union {
    dword Dword;
  } FMC_DATAW1S7L_STR;

  #define FMC_DATAW1S7L                 (*((volatile dword *)0x0000DF3E))


  /*** FMC_DATAW2S0U - Cache Data Storage (upper word); 0x0000DF40 ***/
  union {
    dword Dword;
  } FMC_DATAW2S0U_STR;

  #define FMC_DATAW2S0U                 (*((volatile dword *)0x0000DF40))


  /*** FMC_DATAW2S0L - Cache Data Storage (lower word); 0x0000DF42 ***/
  union {
    dword Dword;
  } FMC_DATAW2S0L_STR;

  #define FMC_DATAW2S0L                 (*((volatile dword *)0x0000DF42))


  /*** FMC_DATAW2S1U - Cache Data Storage (upper word); 0x0000DF44 ***/
  union {
    dword Dword;
  } FMC_DATAW2S1U_STR;

  #define FMC_DATAW2S1U                 (*((volatile dword *)0x0000DF44))


  /*** FMC_DATAW2S1L - Cache Data Storage (lower word); 0x0000DF46 ***/
  union {
    dword Dword;
  } FMC_DATAW2S1L_STR;

  #define FMC_DATAW2S1L                 (*((volatile dword *)0x0000DF46))


  /*** FMC_DATAW2S2U - Cache Data Storage (upper word); 0x0000DF48 ***/
  union {
    dword Dword;
  } FMC_DATAW2S2U_STR;

  #define FMC_DATAW2S2U                 (*((volatile dword *)0x0000DF48))


  /*** FMC_DATAW2S2L - Cache Data Storage (lower word); 0x0000DF4A ***/
  union {
    dword Dword;
  } FMC_DATAW2S2L_STR;

  #define FMC_DATAW2S2L                 (*((volatile dword *)0x0000DF4A))


  /*** FMC_DATAW2S3U - Cache Data Storage (upper word); 0x0000DF4C ***/
  union {
    dword Dword;
  } FMC_DATAW2S3U_STR;

  #define FMC_DATAW2S3U                 (*((volatile dword *)0x0000DF4C))


  /*** FMC_DATAW2S3L - Cache Data Storage (lower word); 0x0000DF4E ***/
  union {
    dword Dword;
  } FMC_DATAW2S3L_STR;

  #define FMC_DATAW2S3L                 (*((volatile dword *)0x0000DF4E))


  /*** FMC_DATAW2S4U - Cache Data Storage (upper word); 0x0000DF50 ***/
  union {
    dword Dword;
  } FMC_DATAW2S4U_STR;

  #define FMC_DATAW2S4U                 (*((volatile dword *)0x0000DF50))


  /*** FMC_DATAW2S4L - Cache Data Storage (lower word); 0x0000DF52 ***/
  union {
    dword Dword;
  } FMC_DATAW2S4L_STR;

  #define FMC_DATAW2S4L                 (*((volatile dword *)0x0000DF52))


  /*** FMC_DATAW2S5U - Cache Data Storage (upper word); 0x0000DF54 ***/
  union {
    dword Dword;
  } FMC_DATAW2S5U_STR;

  #define FMC_DATAW2S5U                 (*((volatile dword *)0x0000DF54))


  /*** FMC_DATAW2S5L - Cache Data Storage (lower word); 0x0000DF56 ***/
  union {
    dword Dword;
  } FMC_DATAW2S5L_STR;

  #define FMC_DATAW2S5L                 (*((volatile dword *)0x0000DF56))


  /*** FMC_DATAW2S6U - Cache Data Storage (upper word); 0x0000DF58 ***/
  union {
    dword Dword;
  } FMC_DATAW2S6U_STR;

  #define FMC_DATAW2S6U                 (*((volatile dword *)0x0000DF58))


  /*** FMC_DATAW2S6L - Cache Data Storage (lower word); 0x0000DF5A ***/
  union {
    dword Dword;
  } FMC_DATAW2S6L_STR;

  #define FMC_DATAW2S6L                 (*((volatile dword *)0x0000DF5A))


  /*** FMC_DATAW2S7U - Cache Data Storage (upper word); 0x0000DF5C ***/
  union {
    dword Dword;
  } FMC_DATAW2S7U_STR;

  #define FMC_DATAW2S7U                 (*((volatile dword *)0x0000DF5C))


  /*** FMC_DATAW2S7L - Cache Data Storage (lower word); 0x0000DF5E ***/
  union {
    dword Dword;
  } FMC_DATAW2S7L_STR;

  #define FMC_DATAW2S7L                 (*((volatile dword *)0x0000DF5E))


  /*** FMC_DATAW3S0U - Cache Data Storage (upper word); 0x0000DF60 ***/
  union {
    dword Dword;
  } FMC_DATAW3S0U_STR;

  #define FMC_DATAW3S0U                 (*((volatile dword *)0x0000DF60))


  /*** FMC_DATAW3S0L - Cache Data Storage (lower word); 0x0000DF62 ***/
  union {
    dword Dword;
  } FMC_DATAW3S0L_STR;

  #define FMC_DATAW3S0L                 (*((volatile dword *)0x0000DF62))


  /*** FMC_DATAW3S1U - Cache Data Storage (upper word); 0x0000DF64 ***/
  union {
    dword Dword;
  } FMC_DATAW3S1U_STR;

  #define FMC_DATAW3S1U                 (*((volatile dword *)0x0000DF64))


  /*** FMC_DATAW3S1L - Cache Data Storage (lower word); 0x0000DF66 ***/
  union {
    dword Dword;
  } FMC_DATAW3S1L_STR;

  #define FMC_DATAW3S1L                 (*((volatile dword *)0x0000DF66))


  /*** FMC_DATAW3S2U - Cache Data Storage (upper word); 0x0000DF68 ***/
  union {
    dword Dword;
  } FMC_DATAW3S2U_STR;

  #define FMC_DATAW3S2U                 (*((volatile dword *)0x0000DF68))


  /*** FMC_DATAW3S2L - Cache Data Storage (lower word); 0x0000DF6A ***/
  union {
    dword Dword;
  } FMC_DATAW3S2L_STR;

  #define FMC_DATAW3S2L                 (*((volatile dword *)0x0000DF6A))


  /*** FMC_DATAW3S3U - Cache Data Storage (upper word); 0x0000DF6C ***/
  union {
    dword Dword;
  } FMC_DATAW3S3U_STR;

  #define FMC_DATAW3S3U                 (*((volatile dword *)0x0000DF6C))


  /*** FMC_DATAW3S3L - Cache Data Storage (lower word); 0x0000DF6E ***/
  union {
    dword Dword;
  } FMC_DATAW3S3L_STR;

  #define FMC_DATAW3S3L                 (*((volatile dword *)0x0000DF6E))


  /*** FMC_DATAW3S4U - Cache Data Storage (upper word); 0x0000DF70 ***/
  union {
    dword Dword;
  } FMC_DATAW3S4U_STR;

  #define FMC_DATAW3S4U                 (*((volatile dword *)0x0000DF70))


  /*** FMC_DATAW3S4L - Cache Data Storage (lower word); 0x0000DF72 ***/
  union {
    dword Dword;
  } FMC_DATAW3S4L_STR;

  #define FMC_DATAW3S4L                 (*((volatile dword *)0x0000DF72))


  /*** FMC_DATAW3S5U - Cache Data Storage (upper word); 0x0000DF74 ***/
  union {
    dword Dword;
  } FMC_DATAW3S5U_STR;

  #define FMC_DATAW3S5U                 (*((volatile dword *)0x0000DF74))


  /*** FMC_DATAW3S5L - Cache Data Storage (lower word); 0x0000DF76 ***/
  union {
    dword Dword;
  } FMC_DATAW3S5L_STR;

  #define FMC_DATAW3S5L                 (*((volatile dword *)0x0000DF76))


  /*** FMC_DATAW3S6U - Cache Data Storage (upper word); 0x0000DF78 ***/
  union {
    dword Dword;
  } FMC_DATAW3S6U_STR;

  #define FMC_DATAW3S6U                 (*((volatile dword *)0x0000DF78))


  /*** FMC_DATAW3S6L - Cache Data Storage (lower word); 0x0000DF7A ***/
  union {
    dword Dword;
  } FMC_DATAW3S6L_STR;

  #define FMC_DATAW3S6L                 (*((volatile dword *)0x0000DF7A))


  /*** FMC_DATAW3S7U - Cache Data Storage (upper word); 0x0000DF7C ***/
  union {
    dword Dword;
  } FMC_DATAW3S7U_STR;

  #define FMC_DATAW3S7U                 (*((volatile dword *)0x0000DF7C))


  /*** FMC_DATAW3S7L - Cache Data Storage (lower word); 0x0000DF7E ***/
  union {
    dword Dword;
  } FMC_DATAW3S7L_STR;

  #define FMC_DATAW3S7L                 (*((volatile dword *)0x0000DF7E))


} FMC_PRPH;
/******************************************
*** Peripheral DAC
*******************************************/
typedef volatile struct {
  /*** DAC_CTRL0 - Control Register 0; 0x0000E000 ***/
  union {
    word Word;
  } DAC_CTRL0_STR;

  #define DAC_CTRL0_PDN_MASK            0x01U
  #define DAC_CTRL0_FORMAT_MASK         0x02U
  #define DAC_CTRL0_SYNC_EN_MASK        0x04U
  #define DAC_CTRL0_AUTO_MASK           0x08U
  #define DAC_CTRL0_DOWN_MASK           0x10U
  #define DAC_CTRL0_UP_MASK             0x20U
  #define DAC_CTRL0_HSLS_MASK           0x40U
  #define DAC_CTRL0_DMA_EN_MASK         0x80U
  #define DAC_CTRL0_WTMK_LVL0_MASK      0x0100U
  #define DAC_CTRL0_WTMK_LVL1_MASK      0x0200U
  #define DAC_CTRL0_FILT_EN_MASK        0x1000U
  #define DAC_CTRL0_WTMK_LVL_MASK       0x0300U
  #define DAC_CTRL0_WTMK_LVL_BITNUM     0x08U
  #define DAC_CTRL0                     (*((volatile word *)0x0000E000))


  /*** DAC_DATAREG - Buffered Data Register; 0x0000E001 ***/
  union {
    word Word;
  } DAC_DATAREG_STR;

  #define DAC_DATAREG                   (*((volatile word *)0x0000E001))


  /*** DAC_STEPVAL - Step Size Register; 0x0000E002 ***/
  union {
    word Word;
  } DAC_STEPVAL_STR;

  #define DAC_STEPVAL                   (*((volatile word *)0x0000E002))


  /*** DAC_MINVAL - Minimum Value Register; 0x0000E003 ***/
  union {
    word Word;
  } DAC_MINVAL_STR;

  #define DAC_MINVAL                    (*((volatile word *)0x0000E003))


  /*** DAC_MAXVAL - Maximum Value Register; 0x0000E004 ***/
  union {
    word Word;
  } DAC_MAXVAL_STR;

  #define DAC_MAXVAL                    (*((volatile word *)0x0000E004))


  /*** DAC_STATUS - Status Register; 0x0000E005 ***/
  union {
    word Word;
  } DAC_STATUS_STR;

  #define DAC_STATUS_EMPTY_MASK         0x01U
  #define DAC_STATUS_FULL_MASK          0x02U
  #define DAC_STATUS                    (*((volatile word *)0x0000E005))


  /*** DAC_CTRL1 - Control Register 1; 0x0000E006 ***/
  union {
    word Word;
  } DAC_CTRL1_STR;

  #define DAC_CTRL1_FILT_CNT0_MASK      0x01U
  #define DAC_CTRL1_FILT_CNT1_MASK      0x02U
  #define DAC_CTRL1_FILT_CNT2_MASK      0x04U
  #define DAC_CTRL1_FILT_CNT3_MASK      0x08U
  #define DAC_CTRL1_FILT_CNT4_MASK      0x10U
  #define DAC_CTRL1_FILT_CNT5_MASK      0x20U
  #define DAC_CTRL1_FILT_CNT_MASK       0x3FU
  #define DAC_CTRL1_FILT_CNT_BITNUM     0x00U
  #define DAC_CTRL1                     (*((volatile word *)0x0000E006))


} DAC_PRPH;
/******************************************
*** Peripheral CMPA
*******************************************/
typedef volatile struct {
  /*** CMPA_CR0 - CMP Control Register 0; 0x0000E020 ***/
  union {
    word Word;
  } CMPA_CR0_STR;

  #define CMPA_CR0_HYSTCTR0_MASK        0x01U
  #define CMPA_CR0_HYSTCTR1_MASK        0x02U
  #define CMPA_CR0_FILTER_CNT0_MASK     0x10U
  #define CMPA_CR0_FILTER_CNT1_MASK     0x20U
  #define CMPA_CR0_FILTER_CNT2_MASK     0x40U
  #define CMPA_CR0_HYSTCTR_MASK         0x03U
  #define CMPA_CR0_HYSTCTR_BITNUM       0x00U
  #define CMPA_CR0_FILTER_CNT_MASK      0x70U
  #define CMPA_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMPA_CR0                      (*((volatile word *)0x0000E020))


  /*** CMPA_CR1 - CMP Control Register 1; 0x0000E021 ***/
  union {
    word Word;
  } CMPA_CR1_STR;

  #define CMPA_CR1_EN_MASK              0x01U
  #define CMPA_CR1_OPE_MASK             0x02U
  #define CMPA_CR1_COS_MASK             0x04U
  #define CMPA_CR1_INV_MASK             0x08U
  #define CMPA_CR1_PMODE_MASK           0x10U
  #define CMPA_CR1_WE_MASK              0x40U
  #define CMPA_CR1_SE_MASK              0x80U
  #define CMPA_CR1                      (*((volatile word *)0x0000E021))


  /*** CMPA_FPR - CMP Filter Period Register; 0x0000E022 ***/
  union {
    word Word;
  } CMPA_FPR_STR;

  #define CMPA_FPR_FILT_PER0_MASK       0x01U
  #define CMPA_FPR_FILT_PER1_MASK       0x02U
  #define CMPA_FPR_FILT_PER2_MASK       0x04U
  #define CMPA_FPR_FILT_PER3_MASK       0x08U
  #define CMPA_FPR_FILT_PER4_MASK       0x10U
  #define CMPA_FPR_FILT_PER5_MASK       0x20U
  #define CMPA_FPR_FILT_PER6_MASK       0x40U
  #define CMPA_FPR_FILT_PER7_MASK       0x80U
  #define CMPA_FPR_FILT_PER_MASK        0xFFU
  #define CMPA_FPR_FILT_PER_BITNUM      0x00U
  #define CMPA_FPR                      (*((volatile word *)0x0000E022))


  /*** CMPA_SCR - CMP Status and Control Register; 0x0000E023 ***/
  union {
    word Word;
  } CMPA_SCR_STR;

  #define CMPA_SCR_COUT_MASK            0x01U
  #define CMPA_SCR_CFF_MASK             0x02U
  #define CMPA_SCR_CFR_MASK             0x04U
  #define CMPA_SCR_IEF_MASK             0x08U
  #define CMPA_SCR_IER_MASK             0x10U
  #define CMPA_SCR                      (*((volatile word *)0x0000E023))


  /*** CMPA_DACCR - DAC Control Register; 0x0000E024 ***/
  union {
    word Word;
  } CMPA_DACCR_STR;

  #define CMPA_DACCR_VOSEL0_MASK        0x01U
  #define CMPA_DACCR_VOSEL1_MASK        0x02U
  #define CMPA_DACCR_VOSEL2_MASK        0x04U
  #define CMPA_DACCR_VOSEL3_MASK        0x08U
  #define CMPA_DACCR_VOSEL4_MASK        0x10U
  #define CMPA_DACCR_VOSEL5_MASK        0x20U
  #define CMPA_DACCR_VRSEL_MASK         0x40U
  #define CMPA_DACCR_DACEN_MASK         0x80U
  #define CMPA_DACCR_VOSEL_MASK         0x3FU
  #define CMPA_DACCR_VOSEL_BITNUM       0x00U
  #define CMPA_DACCR                    (*((volatile word *)0x0000E024))


  /*** CMPA_MUXCR - MUX Control Register; 0x0000E025 ***/
  union {
    word Word;
  } CMPA_MUXCR_STR;

  #define CMPA_MUXCR_MSEL0_MASK         0x01U
  #define CMPA_MUXCR_MSEL1_MASK         0x02U
  #define CMPA_MUXCR_MSEL2_MASK         0x04U
  #define CMPA_MUXCR_PSEL0_MASK         0x08U
  #define CMPA_MUXCR_PSEL1_MASK         0x10U
  #define CMPA_MUXCR_PSEL2_MASK         0x20U
  #define CMPA_MUXCR_MSEL_MASK          0x07U
  #define CMPA_MUXCR_MSEL_BITNUM        0x00U
  #define CMPA_MUXCR_PSEL_MASK          0x38U
  #define CMPA_MUXCR_PSEL_BITNUM        0x03U
  #define CMPA_MUXCR                    (*((volatile word *)0x0000E025))


} CMPA_PRPH;
/******************************************
*** Peripheral CMPB
*******************************************/
typedef volatile struct {
  /*** CMPB_CR0 - CMP Control Register 0; 0x0000E028 ***/
  union {
    word Word;
  } CMPB_CR0_STR;

  #define CMPB_CR0_HYSTCTR0_MASK        0x01U
  #define CMPB_CR0_HYSTCTR1_MASK        0x02U
  #define CMPB_CR0_FILTER_CNT0_MASK     0x10U
  #define CMPB_CR0_FILTER_CNT1_MASK     0x20U
  #define CMPB_CR0_FILTER_CNT2_MASK     0x40U
  #define CMPB_CR0_HYSTCTR_MASK         0x03U
  #define CMPB_CR0_HYSTCTR_BITNUM       0x00U
  #define CMPB_CR0_FILTER_CNT_MASK      0x70U
  #define CMPB_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMPB_CR0                      (*((volatile word *)0x0000E028))


  /*** CMPB_CR1 - CMP Control Register 1; 0x0000E029 ***/
  union {
    word Word;
  } CMPB_CR1_STR;

  #define CMPB_CR1_EN_MASK              0x01U
  #define CMPB_CR1_OPE_MASK             0x02U
  #define CMPB_CR1_COS_MASK             0x04U
  #define CMPB_CR1_INV_MASK             0x08U
  #define CMPB_CR1_PMODE_MASK           0x10U
  #define CMPB_CR1_WE_MASK              0x40U
  #define CMPB_CR1_SE_MASK              0x80U
  #define CMPB_CR1                      (*((volatile word *)0x0000E029))


  /*** CMPB_FPR - CMP Filter Period Register; 0x0000E02A ***/
  union {
    word Word;
  } CMPB_FPR_STR;

  #define CMPB_FPR_FILT_PER0_MASK       0x01U
  #define CMPB_FPR_FILT_PER1_MASK       0x02U
  #define CMPB_FPR_FILT_PER2_MASK       0x04U
  #define CMPB_FPR_FILT_PER3_MASK       0x08U
  #define CMPB_FPR_FILT_PER4_MASK       0x10U
  #define CMPB_FPR_FILT_PER5_MASK       0x20U
  #define CMPB_FPR_FILT_PER6_MASK       0x40U
  #define CMPB_FPR_FILT_PER7_MASK       0x80U
  #define CMPB_FPR_FILT_PER_MASK        0xFFU
  #define CMPB_FPR_FILT_PER_BITNUM      0x00U
  #define CMPB_FPR                      (*((volatile word *)0x0000E02A))


  /*** CMPB_SCR - CMP Status and Control Register; 0x0000E02B ***/
  union {
    word Word;
  } CMPB_SCR_STR;

  #define CMPB_SCR_COUT_MASK            0x01U
  #define CMPB_SCR_CFF_MASK             0x02U
  #define CMPB_SCR_CFR_MASK             0x04U
  #define CMPB_SCR_IEF_MASK             0x08U
  #define CMPB_SCR_IER_MASK             0x10U
  #define CMPB_SCR                      (*((volatile word *)0x0000E02B))


  /*** CMPB_DACCR - DAC Control Register; 0x0000E02C ***/
  union {
    word Word;
  } CMPB_DACCR_STR;

  #define CMPB_DACCR_VOSEL0_MASK        0x01U
  #define CMPB_DACCR_VOSEL1_MASK        0x02U
  #define CMPB_DACCR_VOSEL2_MASK        0x04U
  #define CMPB_DACCR_VOSEL3_MASK        0x08U
  #define CMPB_DACCR_VOSEL4_MASK        0x10U
  #define CMPB_DACCR_VOSEL5_MASK        0x20U
  #define CMPB_DACCR_VRSEL_MASK         0x40U
  #define CMPB_DACCR_DACEN_MASK         0x80U
  #define CMPB_DACCR_VOSEL_MASK         0x3FU
  #define CMPB_DACCR_VOSEL_BITNUM       0x00U
  #define CMPB_DACCR                    (*((volatile word *)0x0000E02C))


  /*** CMPB_MUXCR - MUX Control Register; 0x0000E02D ***/
  union {
    word Word;
  } CMPB_MUXCR_STR;

  #define CMPB_MUXCR_MSEL0_MASK         0x01U
  #define CMPB_MUXCR_MSEL1_MASK         0x02U
  #define CMPB_MUXCR_MSEL2_MASK         0x04U
  #define CMPB_MUXCR_PSEL0_MASK         0x08U
  #define CMPB_MUXCR_PSEL1_MASK         0x10U
  #define CMPB_MUXCR_PSEL2_MASK         0x20U
  #define CMPB_MUXCR_MSEL_MASK          0x07U
  #define CMPB_MUXCR_MSEL_BITNUM        0x00U
  #define CMPB_MUXCR_PSEL_MASK          0x38U
  #define CMPB_MUXCR_PSEL_BITNUM        0x03U
  #define CMPB_MUXCR                    (*((volatile word *)0x0000E02D))


} CMPB_PRPH;
/******************************************
*** Peripheral CMPC
*******************************************/
typedef volatile struct {
  /*** CMPC_CR0 - CMP Control Register 0; 0x0000E030 ***/
  union {
    word Word;
  } CMPC_CR0_STR;

  #define CMPC_CR0_HYSTCTR0_MASK        0x01U
  #define CMPC_CR0_HYSTCTR1_MASK        0x02U
  #define CMPC_CR0_FILTER_CNT0_MASK     0x10U
  #define CMPC_CR0_FILTER_CNT1_MASK     0x20U
  #define CMPC_CR0_FILTER_CNT2_MASK     0x40U
  #define CMPC_CR0_HYSTCTR_MASK         0x03U
  #define CMPC_CR0_HYSTCTR_BITNUM       0x00U
  #define CMPC_CR0_FILTER_CNT_MASK      0x70U
  #define CMPC_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMPC_CR0                      (*((volatile word *)0x0000E030))


  /*** CMPC_CR1 - CMP Control Register 1; 0x0000E031 ***/
  union {
    word Word;
  } CMPC_CR1_STR;

  #define CMPC_CR1_EN_MASK              0x01U
  #define CMPC_CR1_OPE_MASK             0x02U
  #define CMPC_CR1_COS_MASK             0x04U
  #define CMPC_CR1_INV_MASK             0x08U
  #define CMPC_CR1_PMODE_MASK           0x10U
  #define CMPC_CR1_WE_MASK              0x40U
  #define CMPC_CR1_SE_MASK              0x80U
  #define CMPC_CR1                      (*((volatile word *)0x0000E031))


  /*** CMPC_FPR - CMP Filter Period Register; 0x0000E032 ***/
  union {
    word Word;
  } CMPC_FPR_STR;

  #define CMPC_FPR_FILT_PER0_MASK       0x01U
  #define CMPC_FPR_FILT_PER1_MASK       0x02U
  #define CMPC_FPR_FILT_PER2_MASK       0x04U
  #define CMPC_FPR_FILT_PER3_MASK       0x08U
  #define CMPC_FPR_FILT_PER4_MASK       0x10U
  #define CMPC_FPR_FILT_PER5_MASK       0x20U
  #define CMPC_FPR_FILT_PER6_MASK       0x40U
  #define CMPC_FPR_FILT_PER7_MASK       0x80U
  #define CMPC_FPR_FILT_PER_MASK        0xFFU
  #define CMPC_FPR_FILT_PER_BITNUM      0x00U
  #define CMPC_FPR                      (*((volatile word *)0x0000E032))


  /*** CMPC_SCR - CMP Status and Control Register; 0x0000E033 ***/
  union {
    word Word;
  } CMPC_SCR_STR;

  #define CMPC_SCR_COUT_MASK            0x01U
  #define CMPC_SCR_CFF_MASK             0x02U
  #define CMPC_SCR_CFR_MASK             0x04U
  #define CMPC_SCR_IEF_MASK             0x08U
  #define CMPC_SCR_IER_MASK             0x10U
  #define CMPC_SCR                      (*((volatile word *)0x0000E033))


  /*** CMPC_DACCR - DAC Control Register; 0x0000E034 ***/
  union {
    word Word;
  } CMPC_DACCR_STR;

  #define CMPC_DACCR_VOSEL0_MASK        0x01U
  #define CMPC_DACCR_VOSEL1_MASK        0x02U
  #define CMPC_DACCR_VOSEL2_MASK        0x04U
  #define CMPC_DACCR_VOSEL3_MASK        0x08U
  #define CMPC_DACCR_VOSEL4_MASK        0x10U
  #define CMPC_DACCR_VOSEL5_MASK        0x20U
  #define CMPC_DACCR_VRSEL_MASK         0x40U
  #define CMPC_DACCR_DACEN_MASK         0x80U
  #define CMPC_DACCR_VOSEL_MASK         0x3FU
  #define CMPC_DACCR_VOSEL_BITNUM       0x00U
  #define CMPC_DACCR                    (*((volatile word *)0x0000E034))


  /*** CMPC_MUXCR - MUX Control Register; 0x0000E035 ***/
  union {
    word Word;
  } CMPC_MUXCR_STR;

  #define CMPC_MUXCR_MSEL0_MASK         0x01U
  #define CMPC_MUXCR_MSEL1_MASK         0x02U
  #define CMPC_MUXCR_MSEL2_MASK         0x04U
  #define CMPC_MUXCR_PSEL0_MASK         0x08U
  #define CMPC_MUXCR_PSEL1_MASK         0x10U
  #define CMPC_MUXCR_PSEL2_MASK         0x20U
  #define CMPC_MUXCR_MSEL_MASK          0x07U
  #define CMPC_MUXCR_MSEL_BITNUM        0x00U
  #define CMPC_MUXCR_PSEL_MASK          0x38U
  #define CMPC_MUXCR_PSEL_BITNUM        0x03U
  #define CMPC_MUXCR                    (*((volatile word *)0x0000E035))


} CMPC_PRPH;
/******************************************
*** Peripheral CMPD
*******************************************/
typedef volatile struct {
  /*** CMPD_CR0 - CMP Control Register 0; 0x0000E038 ***/
  union {
    word Word;
  } CMPD_CR0_STR;

  #define CMPD_CR0_HYSTCTR0_MASK        0x01U
  #define CMPD_CR0_HYSTCTR1_MASK        0x02U
  #define CMPD_CR0_FILTER_CNT0_MASK     0x10U
  #define CMPD_CR0_FILTER_CNT1_MASK     0x20U
  #define CMPD_CR0_FILTER_CNT2_MASK     0x40U
  #define CMPD_CR0_HYSTCTR_MASK         0x03U
  #define CMPD_CR0_HYSTCTR_BITNUM       0x00U
  #define CMPD_CR0_FILTER_CNT_MASK      0x70U
  #define CMPD_CR0_FILTER_CNT_BITNUM    0x04U
  #define CMPD_CR0                      (*((volatile word *)0x0000E038))


  /*** CMPD_CR1 - CMP Control Register 1; 0x0000E039 ***/
  union {
    word Word;
  } CMPD_CR1_STR;

  #define CMPD_CR1_EN_MASK              0x01U
  #define CMPD_CR1_OPE_MASK             0x02U
  #define CMPD_CR1_COS_MASK             0x04U
  #define CMPD_CR1_INV_MASK             0x08U
  #define CMPD_CR1_PMODE_MASK           0x10U
  #define CMPD_CR1_WE_MASK              0x40U
  #define CMPD_CR1_SE_MASK              0x80U
  #define CMPD_CR1                      (*((volatile word *)0x0000E039))


  /*** CMPD_FPR - CMP Filter Period Register; 0x0000E03A ***/
  union {
    word Word;
  } CMPD_FPR_STR;

  #define CMPD_FPR_FILT_PER0_MASK       0x01U
  #define CMPD_FPR_FILT_PER1_MASK       0x02U
  #define CMPD_FPR_FILT_PER2_MASK       0x04U
  #define CMPD_FPR_FILT_PER3_MASK       0x08U
  #define CMPD_FPR_FILT_PER4_MASK       0x10U
  #define CMPD_FPR_FILT_PER5_MASK       0x20U
  #define CMPD_FPR_FILT_PER6_MASK       0x40U
  #define CMPD_FPR_FILT_PER7_MASK       0x80U
  #define CMPD_FPR_FILT_PER_MASK        0xFFU
  #define CMPD_FPR_FILT_PER_BITNUM      0x00U
  #define CMPD_FPR                      (*((volatile word *)0x0000E03A))


  /*** CMPD_SCR - CMP Status and Control Register; 0x0000E03B ***/
  union {
    word Word;
  } CMPD_SCR_STR;

  #define CMPD_SCR_COUT_MASK            0x01U
  #define CMPD_SCR_CFF_MASK             0x02U
  #define CMPD_SCR_CFR_MASK             0x04U
  #define CMPD_SCR_IEF_MASK             0x08U
  #define CMPD_SCR_IER_MASK             0x10U
  #define CMPD_SCR                      (*((volatile word *)0x0000E03B))


  /*** CMPD_DACCR - DAC Control Register; 0x0000E03C ***/
  union {
    word Word;
  } CMPD_DACCR_STR;

  #define CMPD_DACCR_VOSEL0_MASK        0x01U
  #define CMPD_DACCR_VOSEL1_MASK        0x02U
  #define CMPD_DACCR_VOSEL2_MASK        0x04U
  #define CMPD_DACCR_VOSEL3_MASK        0x08U
  #define CMPD_DACCR_VOSEL4_MASK        0x10U
  #define CMPD_DACCR_VOSEL5_MASK        0x20U
  #define CMPD_DACCR_VRSEL_MASK         0x40U
  #define CMPD_DACCR_DACEN_MASK         0x80U
  #define CMPD_DACCR_VOSEL_MASK         0x3FU
  #define CMPD_DACCR_VOSEL_BITNUM       0x00U
  #define CMPD_DACCR                    (*((volatile word *)0x0000E03C))


  /*** CMPD_MUXCR - MUX Control Register; 0x0000E03D ***/
  union {
    word Word;
  } CMPD_MUXCR_STR;

  #define CMPD_MUXCR_MSEL0_MASK         0x01U
  #define CMPD_MUXCR_MSEL1_MASK         0x02U
  #define CMPD_MUXCR_MSEL2_MASK         0x04U
  #define CMPD_MUXCR_PSEL0_MASK         0x08U
  #define CMPD_MUXCR_PSEL1_MASK         0x10U
  #define CMPD_MUXCR_PSEL2_MASK         0x20U
  #define CMPD_MUXCR_MSEL_MASK          0x07U
  #define CMPD_MUXCR_MSEL_BITNUM        0x00U
  #define CMPD_MUXCR_PSEL_MASK          0x38U
  #define CMPD_MUXCR_PSEL_BITNUM        0x03U
  #define CMPD_MUXCR                    (*((volatile word *)0x0000E03D))


} CMPD_PRPH;
/******************************************
*** Peripheral QSCI0
*******************************************/
typedef volatile struct {
  /*** QSCI0_RATE - QSCI Baud Rate Register; 0x0000E080 ***/
  union {
    word Word;
  } QSCI0_RATE_STR;

  #define QSCI0_RATE_FRAC_SBR0_MASK     0x01U
  #define QSCI0_RATE_FRAC_SBR1_MASK     0x02U
  #define QSCI0_RATE_FRAC_SBR2_MASK     0x04U
  #define QSCI0_RATE_SBR0_MASK          0x08U
  #define QSCI0_RATE_SBR1_MASK          0x10U
  #define QSCI0_RATE_SBR2_MASK          0x20U
  #define QSCI0_RATE_SBR3_MASK          0x40U
  #define QSCI0_RATE_SBR4_MASK          0x80U
  #define QSCI0_RATE_SBR5_MASK          0x0100U
  #define QSCI0_RATE_SBR6_MASK          0x0200U
  #define QSCI0_RATE_SBR7_MASK          0x0400U
  #define QSCI0_RATE_SBR8_MASK          0x0800U
  #define QSCI0_RATE_SBR9_MASK          0x1000U
  #define QSCI0_RATE_SBR10_MASK         0x2000U
  #define QSCI0_RATE_SBR11_MASK         0x4000U
  #define QSCI0_RATE_SBR12_MASK         0x8000U
  #define QSCI0_RATE_FRAC_SBR_MASK      0x07U
  #define QSCI0_RATE_FRAC_SBR_BITNUM    0x00U
  #define QSCI0_RATE_SBR_MASK           0xFFF8U
  #define QSCI0_RATE_SBR_BITNUM         0x03U
  #define QSCI0_RATE                    (*((volatile word *)0x0000E080))


  /*** QSCI0_CTRL1 - QSCI Control Register 1; 0x0000E081 ***/
  union {
    word Word;
  } QSCI0_CTRL1_STR;

  #define QSCI0_CTRL1_SBK_MASK          0x01U
  #define QSCI0_CTRL1_RWU_MASK          0x02U
  #define QSCI0_CTRL1_RE_MASK           0x04U
  #define QSCI0_CTRL1_TE_MASK           0x08U
  #define QSCI0_CTRL1_REIE_MASK         0x10U
  #define QSCI0_CTRL1_RFIE_MASK         0x20U
  #define QSCI0_CTRL1_TIIE_MASK         0x40U
  #define QSCI0_CTRL1_TEIE_MASK         0x80U
  #define QSCI0_CTRL1_PT_MASK           0x0100U
  #define QSCI0_CTRL1_PE_MASK           0x0200U
  #define QSCI0_CTRL1_POL_MASK          0x0400U
  #define QSCI0_CTRL1_WAKE_MASK         0x0800U
  #define QSCI0_CTRL1_M_MASK            0x1000U
  #define QSCI0_CTRL1_RSRC_MASK         0x2000U
  #define QSCI0_CTRL1_SWAI_MASK         0x4000U
  #define QSCI0_CTRL1_LOOP_MASK         0x8000U
  #define QSCI0_CTRL1                   (*((volatile word *)0x0000E081))


  /*** QSCI0_CTRL2 - QSCI Control Register 2; 0x0000E082 ***/
  union {
    word Word;
  } QSCI0_CTRL2_STR;

  #define QSCI0_CTRL2_RDE_MASK          0x01U
  #define QSCI0_CTRL2_TDE_MASK          0x02U
  #define QSCI0_CTRL2_RIIE_MASK         0x04U
  #define QSCI0_CTRL2_LINMODE_MASK      0x08U
  #define QSCI0_CTRL2_RIEIE_MASK        0x10U
  #define QSCI0_CTRL2_FIFO_EN_MASK      0x20U
  #define QSCI0_CTRL2_RFWM0_MASK        0x40U
  #define QSCI0_CTRL2_RFWM1_MASK        0x80U
  #define QSCI0_CTRL2_RFCNT0_MASK       0x0100U
  #define QSCI0_CTRL2_RFCNT1_MASK       0x0200U
  #define QSCI0_CTRL2_RFCNT2_MASK       0x0400U
  #define QSCI0_CTRL2_TFWM0_MASK        0x0800U
  #define QSCI0_CTRL2_TFWM1_MASK        0x1000U
  #define QSCI0_CTRL2_TFCNT0_MASK       0x2000U
  #define QSCI0_CTRL2_TFCNT1_MASK       0x4000U
  #define QSCI0_CTRL2_TFCNT2_MASK       0x8000U
  #define QSCI0_CTRL2_RFWM_MASK         0xC0U
  #define QSCI0_CTRL2_RFWM_BITNUM       0x06U
  #define QSCI0_CTRL2_RFCNT_MASK        0x0700U
  #define QSCI0_CTRL2_RFCNT_BITNUM      0x08U
  #define QSCI0_CTRL2_TFWM_MASK         0x1800U
  #define QSCI0_CTRL2_TFWM_BITNUM       0x0BU
  #define QSCI0_CTRL2_TFCNT_MASK        0xE000U
  #define QSCI0_CTRL2_TFCNT_BITNUM      0x0DU
  #define QSCI0_CTRL2                   (*((volatile word *)0x0000E082))


  /*** QSCI0_STAT - QSCI Status Register; 0x0000E083 ***/
  union {
    word Word;
  } QSCI0_STAT_STR;

  #define QSCI0_STAT_RAF_MASK           0x01U
  #define QSCI0_STAT_RDMA_MASK          0x02U
  #define QSCI0_STAT_TDMA_MASK          0x04U
  #define QSCI0_STAT_LSE_MASK           0x08U
  #define QSCI0_STAT_RIEF_MASK          0x10U
  #define QSCI0_STAT_PF_MASK            0x0100U
  #define QSCI0_STAT_FE_MASK            0x0200U
  #define QSCI0_STAT_NF_MASK            0x0400U
  #define QSCI0_STAT_OR_MASK            0x0800U
  #define QSCI0_STAT_RIDLE_MASK         0x1000U
  #define QSCI0_STAT_RDRF_MASK          0x2000U
  #define QSCI0_STAT_TIDLE_MASK         0x4000U
  #define QSCI0_STAT_TDRE_MASK          0x8000U
  #define QSCI0_STAT                    (*((volatile word *)0x0000E083))


  /*** QSCI0_DATA - QSCI Data Register; 0x0000E084 ***/
  union {
    word Word;
  } QSCI0_DATA_STR;

  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA0_MASK 0x01U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA1_MASK 0x02U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA2_MASK 0x04U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA3_MASK 0x08U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA4_MASK 0x10U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA5_MASK 0x20U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA6_MASK 0x40U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA7_MASK 0x80U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA8_MASK 0x0100U
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA_MASK 0x01FFU
  #define QSCI0_DATA_RECEIVE_TRANSMIT_DATA_BITNUM 0x00U
  #define QSCI0_DATA                    (*((volatile word *)0x0000E084))


  /*** QSCI0_CTRL3 - QSCI Control Register 3; 0x0000E085 ***/
  union {
    word Word;
  } QSCI0_CTRL3_STR;

  #define QSCI0_CTRL3_SHEN_MASK         0x01U
  #define QSCI0_CTRL3                   (*((volatile word *)0x0000E085))


} QSCI0_PRPH;
/******************************************
*** Peripheral QSCI1
*******************************************/
typedef volatile struct {
  /*** QSCI1_RATE - QSCI Baud Rate Register; 0x0000E090 ***/
  union {
    word Word;
  } QSCI1_RATE_STR;

  #define QSCI1_RATE_FRAC_SBR0_MASK     0x01U
  #define QSCI1_RATE_FRAC_SBR1_MASK     0x02U
  #define QSCI1_RATE_FRAC_SBR2_MASK     0x04U
  #define QSCI1_RATE_SBR0_MASK          0x08U
  #define QSCI1_RATE_SBR1_MASK          0x10U
  #define QSCI1_RATE_SBR2_MASK          0x20U
  #define QSCI1_RATE_SBR3_MASK          0x40U
  #define QSCI1_RATE_SBR4_MASK          0x80U
  #define QSCI1_RATE_SBR5_MASK          0x0100U
  #define QSCI1_RATE_SBR6_MASK          0x0200U
  #define QSCI1_RATE_SBR7_MASK          0x0400U
  #define QSCI1_RATE_SBR8_MASK          0x0800U
  #define QSCI1_RATE_SBR9_MASK          0x1000U
  #define QSCI1_RATE_SBR10_MASK         0x2000U
  #define QSCI1_RATE_SBR11_MASK         0x4000U
  #define QSCI1_RATE_SBR12_MASK         0x8000U
  #define QSCI1_RATE_FRAC_SBR_MASK      0x07U
  #define QSCI1_RATE_FRAC_SBR_BITNUM    0x00U
  #define QSCI1_RATE_SBR_MASK           0xFFF8U
  #define QSCI1_RATE_SBR_BITNUM         0x03U
  #define QSCI1_RATE                    (*((volatile word *)0x0000E090))


  /*** QSCI1_CTRL1 - QSCI Control Register 1; 0x0000E091 ***/
  union {
    word Word;
  } QSCI1_CTRL1_STR;

  #define QSCI1_CTRL1_SBK_MASK          0x01U
  #define QSCI1_CTRL1_RWU_MASK          0x02U
  #define QSCI1_CTRL1_RE_MASK           0x04U
  #define QSCI1_CTRL1_TE_MASK           0x08U
  #define QSCI1_CTRL1_REIE_MASK         0x10U
  #define QSCI1_CTRL1_RFIE_MASK         0x20U
  #define QSCI1_CTRL1_TIIE_MASK         0x40U
  #define QSCI1_CTRL1_TEIE_MASK         0x80U
  #define QSCI1_CTRL1_PT_MASK           0x0100U
  #define QSCI1_CTRL1_PE_MASK           0x0200U
  #define QSCI1_CTRL1_POL_MASK          0x0400U
  #define QSCI1_CTRL1_WAKE_MASK         0x0800U
  #define QSCI1_CTRL1_M_MASK            0x1000U
  #define QSCI1_CTRL1_RSRC_MASK         0x2000U
  #define QSCI1_CTRL1_SWAI_MASK         0x4000U
  #define QSCI1_CTRL1_LOOP_MASK         0x8000U
  #define QSCI1_CTRL1                   (*((volatile word *)0x0000E091))


  /*** QSCI1_CTRL2 - QSCI Control Register 2; 0x0000E092 ***/
  union {
    word Word;
  } QSCI1_CTRL2_STR;

  #define QSCI1_CTRL2_RDE_MASK          0x01U
  #define QSCI1_CTRL2_TDE_MASK          0x02U
  #define QSCI1_CTRL2_RIIE_MASK         0x04U
  #define QSCI1_CTRL2_LINMODE_MASK      0x08U
  #define QSCI1_CTRL2_RIEIE_MASK        0x10U
  #define QSCI1_CTRL2_FIFO_EN_MASK      0x20U
  #define QSCI1_CTRL2_RFWM0_MASK        0x40U
  #define QSCI1_CTRL2_RFWM1_MASK        0x80U
  #define QSCI1_CTRL2_RFCNT0_MASK       0x0100U
  #define QSCI1_CTRL2_RFCNT1_MASK       0x0200U
  #define QSCI1_CTRL2_RFCNT2_MASK       0x0400U
  #define QSCI1_CTRL2_TFWM0_MASK        0x0800U
  #define QSCI1_CTRL2_TFWM1_MASK        0x1000U
  #define QSCI1_CTRL2_TFCNT0_MASK       0x2000U
  #define QSCI1_CTRL2_TFCNT1_MASK       0x4000U
  #define QSCI1_CTRL2_TFCNT2_MASK       0x8000U
  #define QSCI1_CTRL2_RFWM_MASK         0xC0U
  #define QSCI1_CTRL2_RFWM_BITNUM       0x06U
  #define QSCI1_CTRL2_RFCNT_MASK        0x0700U
  #define QSCI1_CTRL2_RFCNT_BITNUM      0x08U
  #define QSCI1_CTRL2_TFWM_MASK         0x1800U
  #define QSCI1_CTRL2_TFWM_BITNUM       0x0BU
  #define QSCI1_CTRL2_TFCNT_MASK        0xE000U
  #define QSCI1_CTRL2_TFCNT_BITNUM      0x0DU
  #define QSCI1_CTRL2                   (*((volatile word *)0x0000E092))


  /*** QSCI1_STAT - QSCI Status Register; 0x0000E093 ***/
  union {
    word Word;
  } QSCI1_STAT_STR;

  #define QSCI1_STAT_RAF_MASK           0x01U
  #define QSCI1_STAT_RDMA_MASK          0x02U
  #define QSCI1_STAT_TDMA_MASK          0x04U
  #define QSCI1_STAT_LSE_MASK           0x08U
  #define QSCI1_STAT_RIEF_MASK          0x10U
  #define QSCI1_STAT_PF_MASK            0x0100U
  #define QSCI1_STAT_FE_MASK            0x0200U
  #define QSCI1_STAT_NF_MASK            0x0400U
  #define QSCI1_STAT_OR_MASK            0x0800U
  #define QSCI1_STAT_RIDLE_MASK         0x1000U
  #define QSCI1_STAT_RDRF_MASK          0x2000U
  #define QSCI1_STAT_TIDLE_MASK         0x4000U
  #define QSCI1_STAT_TDRE_MASK          0x8000U
  #define QSCI1_STAT                    (*((volatile word *)0x0000E093))


  /*** QSCI1_DATA - QSCI Data Register; 0x0000E094 ***/
  union {
    word Word;
  } QSCI1_DATA_STR;

  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA0_MASK 0x01U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA1_MASK 0x02U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA2_MASK 0x04U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA3_MASK 0x08U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA4_MASK 0x10U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA5_MASK 0x20U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA6_MASK 0x40U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA7_MASK 0x80U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA8_MASK 0x0100U
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA_MASK 0x01FFU
  #define QSCI1_DATA_RECEIVE_TRANSMIT_DATA_BITNUM 0x00U
  #define QSCI1_DATA                    (*((volatile word *)0x0000E094))


  /*** QSCI1_CTRL3 - QSCI Control Register 3; 0x0000E095 ***/
  union {
    word Word;
  } QSCI1_CTRL3_STR;

  #define QSCI1_CTRL3_SHEN_MASK         0x01U
  #define QSCI1_CTRL3                   (*((volatile word *)0x0000E095))


} QSCI1_PRPH;
/******************************************
*** Peripheral QSCI2
*******************************************/
typedef volatile struct {
  /*** QSCI2_RATE - QSCI Baud Rate Register; 0x0000E0A0 ***/
  union {
    word Word;
  } QSCI2_RATE_STR;

  #define QSCI2_RATE_FRAC_SBR0_MASK     0x01U
  #define QSCI2_RATE_FRAC_SBR1_MASK     0x02U
  #define QSCI2_RATE_FRAC_SBR2_MASK     0x04U
  #define QSCI2_RATE_SBR0_MASK          0x08U
  #define QSCI2_RATE_SBR1_MASK          0x10U
  #define QSCI2_RATE_SBR2_MASK          0x20U
  #define QSCI2_RATE_SBR3_MASK          0x40U
  #define QSCI2_RATE_SBR4_MASK          0x80U
  #define QSCI2_RATE_SBR5_MASK          0x0100U
  #define QSCI2_RATE_SBR6_MASK          0x0200U
  #define QSCI2_RATE_SBR7_MASK          0x0400U
  #define QSCI2_RATE_SBR8_MASK          0x0800U
  #define QSCI2_RATE_SBR9_MASK          0x1000U
  #define QSCI2_RATE_SBR10_MASK         0x2000U
  #define QSCI2_RATE_SBR11_MASK         0x4000U
  #define QSCI2_RATE_SBR12_MASK         0x8000U
  #define QSCI2_RATE_FRAC_SBR_MASK      0x07U
  #define QSCI2_RATE_FRAC_SBR_BITNUM    0x00U
  #define QSCI2_RATE_SBR_MASK           0xFFF8U
  #define QSCI2_RATE_SBR_BITNUM         0x03U
  #define QSCI2_RATE                    (*((volatile word *)0x0000E0A0))


  /*** QSCI2_CTRL1 - QSCI Control Register 1; 0x0000E0A1 ***/
  union {
    word Word;
  } QSCI2_CTRL1_STR;

  #define QSCI2_CTRL1_SBK_MASK          0x01U
  #define QSCI2_CTRL1_RWU_MASK          0x02U
  #define QSCI2_CTRL1_RE_MASK           0x04U
  #define QSCI2_CTRL1_TE_MASK           0x08U
  #define QSCI2_CTRL1_REIE_MASK         0x10U
  #define QSCI2_CTRL1_RFIE_MASK         0x20U
  #define QSCI2_CTRL1_TIIE_MASK         0x40U
  #define QSCI2_CTRL1_TEIE_MASK         0x80U
  #define QSCI2_CTRL1_PT_MASK           0x0100U
  #define QSCI2_CTRL1_PE_MASK           0x0200U
  #define QSCI2_CTRL1_POL_MASK          0x0400U
  #define QSCI2_CTRL1_WAKE_MASK         0x0800U
  #define QSCI2_CTRL1_M_MASK            0x1000U
  #define QSCI2_CTRL1_RSRC_MASK         0x2000U
  #define QSCI2_CTRL1_SWAI_MASK         0x4000U
  #define QSCI2_CTRL1_LOOP_MASK         0x8000U
  #define QSCI2_CTRL1                   (*((volatile word *)0x0000E0A1))


  /*** QSCI2_CTRL2 - QSCI Control Register 2; 0x0000E0A2 ***/
  union {
    word Word;
  } QSCI2_CTRL2_STR;

  #define QSCI2_CTRL2_RDE_MASK          0x01U
  #define QSCI2_CTRL2_TDE_MASK          0x02U
  #define QSCI2_CTRL2_RIIE_MASK         0x04U
  #define QSCI2_CTRL2_LINMODE_MASK      0x08U
  #define QSCI2_CTRL2_RIEIE_MASK        0x10U
  #define QSCI2_CTRL2_FIFO_EN_MASK      0x20U
  #define QSCI2_CTRL2_RFWM0_MASK        0x40U
  #define QSCI2_CTRL2_RFWM1_MASK        0x80U
  #define QSCI2_CTRL2_RFCNT0_MASK       0x0100U
  #define QSCI2_CTRL2_RFCNT1_MASK       0x0200U
  #define QSCI2_CTRL2_RFCNT2_MASK       0x0400U
  #define QSCI2_CTRL2_TFWM0_MASK        0x0800U
  #define QSCI2_CTRL2_TFWM1_MASK        0x1000U
  #define QSCI2_CTRL2_TFCNT0_MASK       0x2000U
  #define QSCI2_CTRL2_TFCNT1_MASK       0x4000U
  #define QSCI2_CTRL2_TFCNT2_MASK       0x8000U
  #define QSCI2_CTRL2_RFWM_MASK         0xC0U
  #define QSCI2_CTRL2_RFWM_BITNUM       0x06U
  #define QSCI2_CTRL2_RFCNT_MASK        0x0700U
  #define QSCI2_CTRL2_RFCNT_BITNUM      0x08U
  #define QSCI2_CTRL2_TFWM_MASK         0x1800U
  #define QSCI2_CTRL2_TFWM_BITNUM       0x0BU
  #define QSCI2_CTRL2_TFCNT_MASK        0xE000U
  #define QSCI2_CTRL2_TFCNT_BITNUM      0x0DU
  #define QSCI2_CTRL2                   (*((volatile word *)0x0000E0A2))


  /*** QSCI2_STAT - QSCI Status Register; 0x0000E0A3 ***/
  union {
    word Word;
  } QSCI2_STAT_STR;

  #define QSCI2_STAT_RAF_MASK           0x01U
  #define QSCI2_STAT_RDMA_MASK          0x02U
  #define QSCI2_STAT_TDMA_MASK          0x04U
  #define QSCI2_STAT_LSE_MASK           0x08U
  #define QSCI2_STAT_RIEF_MASK          0x10U
  #define QSCI2_STAT_PF_MASK            0x0100U
  #define QSCI2_STAT_FE_MASK            0x0200U
  #define QSCI2_STAT_NF_MASK            0x0400U
  #define QSCI2_STAT_OR_MASK            0x0800U
  #define QSCI2_STAT_RIDLE_MASK         0x1000U
  #define QSCI2_STAT_RDRF_MASK          0x2000U
  #define QSCI2_STAT_TIDLE_MASK         0x4000U
  #define QSCI2_STAT_TDRE_MASK          0x8000U
  #define QSCI2_STAT                    (*((volatile word *)0x0000E0A3))


  /*** QSCI2_DATA - QSCI Data Register; 0x0000E0A4 ***/
  union {
    word Word;
  } QSCI2_DATA_STR;

  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA0_MASK 0x01U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA1_MASK 0x02U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA2_MASK 0x04U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA3_MASK 0x08U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA4_MASK 0x10U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA5_MASK 0x20U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA6_MASK 0x40U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA7_MASK 0x80U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA8_MASK 0x0100U
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA_MASK 0x01FFU
  #define QSCI2_DATA_RECEIVE_TRANSMIT_DATA_BITNUM 0x00U
  #define QSCI2_DATA                    (*((volatile word *)0x0000E0A4))


  /*** QSCI2_CTRL3 - QSCI Control Register 3; 0x0000E0A5 ***/
  union {
    word Word;
  } QSCI2_CTRL3_STR;

  #define QSCI2_CTRL3_SHEN_MASK         0x01U
  #define QSCI2_CTRL3                   (*((volatile word *)0x0000E0A5))


} QSCI2_PRPH;
/******************************************
*** Peripheral QSPI0
*******************************************/
typedef volatile struct {
  /*** QSPI0_SPSCR - SPI Status and Control Register; 0x0000E0B0 ***/
  union {
    word Word;
  } QSPI0_SPSCR_STR;

  #define QSPI0_SPSCR_SPTE_MASK         0x01U
  #define QSPI0_SPSCR_MODF_MASK         0x02U
  #define QSPI0_SPSCR_OVRF_MASK         0x04U
  #define QSPI0_SPSCR_SPRF_MASK         0x08U
  #define QSPI0_SPSCR_SPTIE_MASK        0x10U
  #define QSPI0_SPSCR_SPE_MASK          0x20U
  #define QSPI0_SPSCR_CPHA_MASK         0x40U
  #define QSPI0_SPSCR_CPOL_MASK         0x80U
  #define QSPI0_SPSCR_SPMSTR_MASK       0x0100U
  #define QSPI0_SPSCR_SPRIE_MASK        0x0200U
  #define QSPI0_SPSCR_MODFEN_MASK       0x0400U
  #define QSPI0_SPSCR_ERRIE_MASK        0x0800U
  #define QSPI0_SPSCR_DSO_MASK          0x1000U
  #define QSPI0_SPSCR_SPR0_MASK         0x2000U
  #define QSPI0_SPSCR_SPR1_MASK         0x4000U
  #define QSPI0_SPSCR_SPR2_MASK         0x8000U
  #define QSPI0_SPSCR_SPR_MASK          0xE000U
  #define QSPI0_SPSCR_SPR_BITNUM        0x0DU
  #define QSPI0_SPSCR                   (*((volatile word *)0x0000E0B0))


  /*** QSPI0_SPDSR - SPI Data Size and Control Register; 0x0000E0B1 ***/
  union {
    word Word;
  } QSPI0_SPDSR_STR;

  #define QSPI0_SPDSR_DS0_MASK          0x01U
  #define QSPI0_SPDSR_DS1_MASK          0x02U
  #define QSPI0_SPDSR_DS2_MASK          0x04U
  #define QSPI0_SPDSR_DS3_MASK          0x08U
  #define QSPI0_SPDSR_SPR3_MASK         0x10U
  #define QSPI0_SPDSR_SSB_OVER_MASK     0x20U
  #define QSPI0_SPDSR_SSB_STRB_MASK     0x40U
  #define QSPI0_SPDSR_SSB_DDR_MASK      0x80U
  #define QSPI0_SPDSR_SSB_AUTO_MASK     0x0100U
  #define QSPI0_SPDSR_SSB_ODM_MASK      0x0200U
  #define QSPI0_SPDSR_SSB_DATA_MASK     0x0400U
  #define QSPI0_SPDSR_SSB_IN_MASK       0x0800U
  #define QSPI0_SPDSR_BD2X_MASK         0x1000U
  #define QSPI0_SPDSR_RDMAEN_MASK       0x2000U
  #define QSPI0_SPDSR_TDMAEN_MASK       0x4000U
  #define QSPI0_SPDSR_WOM_MASK          0x8000U
  #define QSPI0_SPDSR_DS_MASK           0x0FU
  #define QSPI0_SPDSR_DS_BITNUM         0x00U
  #define QSPI0_SPDSR                   (*((volatile word *)0x0000E0B1))


  /*** QSPI0_SPDRR - SPI Data Receive Register; 0x0000E0B2 ***/
  union {
    word Word;
  } QSPI0_SPDRR_STR;

  #define QSPI0_SPDRR_R0_MASK           0x01U
  #define QSPI0_SPDRR_R1_MASK           0x02U
  #define QSPI0_SPDRR_R2_MASK           0x04U
  #define QSPI0_SPDRR_R3_MASK           0x08U
  #define QSPI0_SPDRR_R4_MASK           0x10U
  #define QSPI0_SPDRR_R5_MASK           0x20U
  #define QSPI0_SPDRR_R6_MASK           0x40U
  #define QSPI0_SPDRR_R7_MASK           0x80U
  #define QSPI0_SPDRR_R8_MASK           0x0100U
  #define QSPI0_SPDRR_R9_MASK           0x0200U
  #define QSPI0_SPDRR_R10_MASK          0x0400U
  #define QSPI0_SPDRR_R11_MASK          0x0800U
  #define QSPI0_SPDRR_R12_MASK          0x1000U
  #define QSPI0_SPDRR_R13_MASK          0x2000U
  #define QSPI0_SPDRR_R14_MASK          0x4000U
  #define QSPI0_SPDRR_R15_MASK          0x8000U
  #define QSPI0_SPDRR                   (*((volatile word *)0x0000E0B2))


  /*** QSPI0_SPDTR - SPI Data Transmit Register; 0x0000E0B3 ***/
  union {
    word Word;
  } QSPI0_SPDTR_STR;

  #define QSPI0_SPDTR_T0_MASK           0x01U
  #define QSPI0_SPDTR_T1_MASK           0x02U
  #define QSPI0_SPDTR_T2_MASK           0x04U
  #define QSPI0_SPDTR_T3_MASK           0x08U
  #define QSPI0_SPDTR_T4_MASK           0x10U
  #define QSPI0_SPDTR_T5_MASK           0x20U
  #define QSPI0_SPDTR_T6_MASK           0x40U
  #define QSPI0_SPDTR_T7_MASK           0x80U
  #define QSPI0_SPDTR_T8_MASK           0x0100U
  #define QSPI0_SPDTR_T9_MASK           0x0200U
  #define QSPI0_SPDTR_T10_MASK          0x0400U
  #define QSPI0_SPDTR_T11_MASK          0x0800U
  #define QSPI0_SPDTR_T12_MASK          0x1000U
  #define QSPI0_SPDTR_T13_MASK          0x2000U
  #define QSPI0_SPDTR_T14_MASK          0x4000U
  #define QSPI0_SPDTR_T15_MASK          0x8000U
  #define QSPI0_SPDTR                   (*((volatile word *)0x0000E0B3))


  /*** QSPI0_SPFIFO - SPI FIFO Control Register; 0x0000E0B4 ***/
  union {
    word Word;
  } QSPI0_SPFIFO_STR;

  #define QSPI0_SPFIFO_FIFO_ENA_MASK    0x01U
  #define QSPI0_SPFIFO_RFWM0_MASK       0x04U
  #define QSPI0_SPFIFO_RFWM1_MASK       0x08U
  #define QSPI0_SPFIFO_TFWM0_MASK       0x20U
  #define QSPI0_SPFIFO_TFWM1_MASK       0x40U
  #define QSPI0_SPFIFO_RFCNT0_MASK      0x0100U
  #define QSPI0_SPFIFO_RFCNT1_MASK      0x0200U
  #define QSPI0_SPFIFO_RFCNT2_MASK      0x0400U
  #define QSPI0_SPFIFO_TFCNT0_MASK      0x1000U
  #define QSPI0_SPFIFO_TFCNT1_MASK      0x2000U
  #define QSPI0_SPFIFO_TFCNT2_MASK      0x4000U
  #define QSPI0_SPFIFO_RFWM_MASK        0x0CU
  #define QSPI0_SPFIFO_RFWM_BITNUM      0x02U
  #define QSPI0_SPFIFO_TFWM_MASK        0x60U
  #define QSPI0_SPFIFO_TFWM_BITNUM      0x05U
  #define QSPI0_SPFIFO_RFCNT_MASK       0x0700U
  #define QSPI0_SPFIFO_RFCNT_BITNUM     0x08U
  #define QSPI0_SPFIFO_TFCNT_MASK       0x7000U
  #define QSPI0_SPFIFO_TFCNT_BITNUM     0x0CU
  #define QSPI0_SPFIFO                  (*((volatile word *)0x0000E0B4))


  /*** QSPI0_SPWAIT - SPI Word Delay Register; 0x0000E0B5 ***/
  union {
    word Word;
  } QSPI0_SPWAIT_STR;

  #define QSPI0_SPWAIT_WAIT0_MASK       0x01U
  #define QSPI0_SPWAIT_WAIT1_MASK       0x02U
  #define QSPI0_SPWAIT_WAIT2_MASK       0x04U
  #define QSPI0_SPWAIT_WAIT3_MASK       0x08U
  #define QSPI0_SPWAIT_WAIT4_MASK       0x10U
  #define QSPI0_SPWAIT_WAIT5_MASK       0x20U
  #define QSPI0_SPWAIT_WAIT6_MASK       0x40U
  #define QSPI0_SPWAIT_WAIT7_MASK       0x80U
  #define QSPI0_SPWAIT_WAIT8_MASK       0x0100U
  #define QSPI0_SPWAIT_WAIT9_MASK       0x0200U
  #define QSPI0_SPWAIT_WAIT10_MASK      0x0400U
  #define QSPI0_SPWAIT_WAIT11_MASK      0x0800U
  #define QSPI0_SPWAIT_WAIT12_MASK      0x1000U
  #define QSPI0_SPWAIT_WAIT_MASK        0x1FFFU
  #define QSPI0_SPWAIT_WAIT_BITNUM      0x00U
  #define QSPI0_SPWAIT                  (*((volatile word *)0x0000E0B5))


  /*** QSPI0_SPCTL2 - SPI Control Register 2; 0x0000E0B6 ***/
  union {
    word Word;
  } QSPI0_SPCTL2_STR;

  #define QSPI0_SPCTL2_SHEN_MASK        0x01U
  #define QSPI0_SPCTL2                  (*((volatile word *)0x0000E0B6))


} QSPI0_PRPH;
/******************************************
*** Peripheral QSPI1
*******************************************/
typedef volatile struct {
  /*** QSPI1_SPSCR - SPI Status and Control Register; 0x0000E0C0 ***/
  union {
    word Word;
  } QSPI1_SPSCR_STR;

  #define QSPI1_SPSCR_SPTE_MASK         0x01U
  #define QSPI1_SPSCR_MODF_MASK         0x02U
  #define QSPI1_SPSCR_OVRF_MASK         0x04U
  #define QSPI1_SPSCR_SPRF_MASK         0x08U
  #define QSPI1_SPSCR_SPTIE_MASK        0x10U
  #define QSPI1_SPSCR_SPE_MASK          0x20U
  #define QSPI1_SPSCR_CPHA_MASK         0x40U
  #define QSPI1_SPSCR_CPOL_MASK         0x80U
  #define QSPI1_SPSCR_SPMSTR_MASK       0x0100U
  #define QSPI1_SPSCR_SPRIE_MASK        0x0200U
  #define QSPI1_SPSCR_MODFEN_MASK       0x0400U
  #define QSPI1_SPSCR_ERRIE_MASK        0x0800U
  #define QSPI1_SPSCR_DSO_MASK          0x1000U
  #define QSPI1_SPSCR_SPR0_MASK         0x2000U
  #define QSPI1_SPSCR_SPR1_MASK         0x4000U
  #define QSPI1_SPSCR_SPR2_MASK         0x8000U
  #define QSPI1_SPSCR_SPR_MASK          0xE000U
  #define QSPI1_SPSCR_SPR_BITNUM        0x0DU
  #define QSPI1_SPSCR                   (*((volatile word *)0x0000E0C0))


  /*** QSPI1_SPDSR - SPI Data Size and Control Register; 0x0000E0C1 ***/
  union {
    word Word;
  } QSPI1_SPDSR_STR;

  #define QSPI1_SPDSR_DS0_MASK          0x01U
  #define QSPI1_SPDSR_DS1_MASK          0x02U
  #define QSPI1_SPDSR_DS2_MASK          0x04U
  #define QSPI1_SPDSR_DS3_MASK          0x08U
  #define QSPI1_SPDSR_SPR3_MASK         0x10U
  #define QSPI1_SPDSR_SSB_OVER_MASK     0x20U
  #define QSPI1_SPDSR_SSB_STRB_MASK     0x40U
  #define QSPI1_SPDSR_SSB_DDR_MASK      0x80U
  #define QSPI1_SPDSR_SSB_AUTO_MASK     0x0100U
  #define QSPI1_SPDSR_SSB_ODM_MASK      0x0200U
  #define QSPI1_SPDSR_SSB_DATA_MASK     0x0400U
  #define QSPI1_SPDSR_SSB_IN_MASK       0x0800U
  #define QSPI1_SPDSR_BD2X_MASK         0x1000U
  #define QSPI1_SPDSR_RDMAEN_MASK       0x2000U
  #define QSPI1_SPDSR_TDMAEN_MASK       0x4000U
  #define QSPI1_SPDSR_WOM_MASK          0x8000U
  #define QSPI1_SPDSR_DS_MASK           0x0FU
  #define QSPI1_SPDSR_DS_BITNUM         0x00U
  #define QSPI1_SPDSR                   (*((volatile word *)0x0000E0C1))


  /*** QSPI1_SPDRR - SPI Data Receive Register; 0x0000E0C2 ***/
  union {
    word Word;
  } QSPI1_SPDRR_STR;

  #define QSPI1_SPDRR_R0_MASK           0x01U
  #define QSPI1_SPDRR_R1_MASK           0x02U
  #define QSPI1_SPDRR_R2_MASK           0x04U
  #define QSPI1_SPDRR_R3_MASK           0x08U
  #define QSPI1_SPDRR_R4_MASK           0x10U
  #define QSPI1_SPDRR_R5_MASK           0x20U
  #define QSPI1_SPDRR_R6_MASK           0x40U
  #define QSPI1_SPDRR_R7_MASK           0x80U
  #define QSPI1_SPDRR_R8_MASK           0x0100U
  #define QSPI1_SPDRR_R9_MASK           0x0200U
  #define QSPI1_SPDRR_R10_MASK          0x0400U
  #define QSPI1_SPDRR_R11_MASK          0x0800U
  #define QSPI1_SPDRR_R12_MASK          0x1000U
  #define QSPI1_SPDRR_R13_MASK          0x2000U
  #define QSPI1_SPDRR_R14_MASK          0x4000U
  #define QSPI1_SPDRR_R15_MASK          0x8000U
  #define QSPI1_SPDRR                   (*((volatile word *)0x0000E0C2))


  /*** QSPI1_SPDTR - SPI Data Transmit Register; 0x0000E0C3 ***/
  union {
    word Word;
  } QSPI1_SPDTR_STR;

  #define QSPI1_SPDTR_T0_MASK           0x01U
  #define QSPI1_SPDTR_T1_MASK           0x02U
  #define QSPI1_SPDTR_T2_MASK           0x04U
  #define QSPI1_SPDTR_T3_MASK           0x08U
  #define QSPI1_SPDTR_T4_MASK           0x10U
  #define QSPI1_SPDTR_T5_MASK           0x20U
  #define QSPI1_SPDTR_T6_MASK           0x40U
  #define QSPI1_SPDTR_T7_MASK           0x80U
  #define QSPI1_SPDTR_T8_MASK           0x0100U
  #define QSPI1_SPDTR_T9_MASK           0x0200U
  #define QSPI1_SPDTR_T10_MASK          0x0400U
  #define QSPI1_SPDTR_T11_MASK          0x0800U
  #define QSPI1_SPDTR_T12_MASK          0x1000U
  #define QSPI1_SPDTR_T13_MASK          0x2000U
  #define QSPI1_SPDTR_T14_MASK          0x4000U
  #define QSPI1_SPDTR_T15_MASK          0x8000U
  #define QSPI1_SPDTR                   (*((volatile word *)0x0000E0C3))


  /*** QSPI1_SPFIFO - SPI FIFO Control Register; 0x0000E0C4 ***/
  union {
    word Word;
  } QSPI1_SPFIFO_STR;

  #define QSPI1_SPFIFO_FIFO_ENA_MASK    0x01U
  #define QSPI1_SPFIFO_RFWM0_MASK       0x04U
  #define QSPI1_SPFIFO_RFWM1_MASK       0x08U
  #define QSPI1_SPFIFO_TFWM0_MASK       0x20U
  #define QSPI1_SPFIFO_TFWM1_MASK       0x40U
  #define QSPI1_SPFIFO_RFCNT0_MASK      0x0100U
  #define QSPI1_SPFIFO_RFCNT1_MASK      0x0200U
  #define QSPI1_SPFIFO_RFCNT2_MASK      0x0400U
  #define QSPI1_SPFIFO_TFCNT0_MASK      0x1000U
  #define QSPI1_SPFIFO_TFCNT1_MASK      0x2000U
  #define QSPI1_SPFIFO_TFCNT2_MASK      0x4000U
  #define QSPI1_SPFIFO_RFWM_MASK        0x0CU
  #define QSPI1_SPFIFO_RFWM_BITNUM      0x02U
  #define QSPI1_SPFIFO_TFWM_MASK        0x60U
  #define QSPI1_SPFIFO_TFWM_BITNUM      0x05U
  #define QSPI1_SPFIFO_RFCNT_MASK       0x0700U
  #define QSPI1_SPFIFO_RFCNT_BITNUM     0x08U
  #define QSPI1_SPFIFO_TFCNT_MASK       0x7000U
  #define QSPI1_SPFIFO_TFCNT_BITNUM     0x0CU
  #define QSPI1_SPFIFO                  (*((volatile word *)0x0000E0C4))


  /*** QSPI1_SPWAIT - SPI Word Delay Register; 0x0000E0C5 ***/
  union {
    word Word;
  } QSPI1_SPWAIT_STR;

  #define QSPI1_SPWAIT_WAIT0_MASK       0x01U
  #define QSPI1_SPWAIT_WAIT1_MASK       0x02U
  #define QSPI1_SPWAIT_WAIT2_MASK       0x04U
  #define QSPI1_SPWAIT_WAIT3_MASK       0x08U
  #define QSPI1_SPWAIT_WAIT4_MASK       0x10U
  #define QSPI1_SPWAIT_WAIT5_MASK       0x20U
  #define QSPI1_SPWAIT_WAIT6_MASK       0x40U
  #define QSPI1_SPWAIT_WAIT7_MASK       0x80U
  #define QSPI1_SPWAIT_WAIT8_MASK       0x0100U
  #define QSPI1_SPWAIT_WAIT9_MASK       0x0200U
  #define QSPI1_SPWAIT_WAIT10_MASK      0x0400U
  #define QSPI1_SPWAIT_WAIT11_MASK      0x0800U
  #define QSPI1_SPWAIT_WAIT12_MASK      0x1000U
  #define QSPI1_SPWAIT_WAIT_MASK        0x1FFFU
  #define QSPI1_SPWAIT_WAIT_BITNUM      0x00U
  #define QSPI1_SPWAIT                  (*((volatile word *)0x0000E0C5))


  /*** QSPI1_SPCTL2 - SPI Control Register 2; 0x0000E0C6 ***/
  union {
    word Word;
  } QSPI1_SPCTL2_STR;

  #define QSPI1_SPCTL2_SHEN_MASK        0x01U
  #define QSPI1_SPCTL2                  (*((volatile word *)0x0000E0C6))


} QSPI1_PRPH;
/******************************************
*** Peripheral QSPI2
*******************************************/
typedef volatile struct {
  /*** QSPI2_SPSCR - SPI Status and Control Register; 0x0000E0D0 ***/
  union {
    word Word;
  } QSPI2_SPSCR_STR;

  #define QSPI2_SPSCR_SPTE_MASK         0x01U
  #define QSPI2_SPSCR_MODF_MASK         0x02U
  #define QSPI2_SPSCR_OVRF_MASK         0x04U
  #define QSPI2_SPSCR_SPRF_MASK         0x08U
  #define QSPI2_SPSCR_SPTIE_MASK        0x10U
  #define QSPI2_SPSCR_SPE_MASK          0x20U
  #define QSPI2_SPSCR_CPHA_MASK         0x40U
  #define QSPI2_SPSCR_CPOL_MASK         0x80U
  #define QSPI2_SPSCR_SPMSTR_MASK       0x0100U
  #define QSPI2_SPSCR_SPRIE_MASK        0x0200U
  #define QSPI2_SPSCR_MODFEN_MASK       0x0400U
  #define QSPI2_SPSCR_ERRIE_MASK        0x0800U
  #define QSPI2_SPSCR_DSO_MASK          0x1000U
  #define QSPI2_SPSCR_SPR0_MASK         0x2000U
  #define QSPI2_SPSCR_SPR1_MASK         0x4000U
  #define QSPI2_SPSCR_SPR2_MASK         0x8000U
  #define QSPI2_SPSCR_SPR_MASK          0xE000U
  #define QSPI2_SPSCR_SPR_BITNUM        0x0DU
  #define QSPI2_SPSCR                   (*((volatile word *)0x0000E0D0))


  /*** QSPI2_SPDSR - SPI Data Size and Control Register; 0x0000E0D1 ***/
  union {
    word Word;
  } QSPI2_SPDSR_STR;

  #define QSPI2_SPDSR_DS0_MASK          0x01U
  #define QSPI2_SPDSR_DS1_MASK          0x02U
  #define QSPI2_SPDSR_DS2_MASK          0x04U
  #define QSPI2_SPDSR_DS3_MASK          0x08U
  #define QSPI2_SPDSR_SPR3_MASK         0x10U
  #define QSPI2_SPDSR_SSB_OVER_MASK     0x20U
  #define QSPI2_SPDSR_SSB_STRB_MASK     0x40U
  #define QSPI2_SPDSR_SSB_DDR_MASK      0x80U
  #define QSPI2_SPDSR_SSB_AUTO_MASK     0x0100U
  #define QSPI2_SPDSR_SSB_ODM_MASK      0x0200U
  #define QSPI2_SPDSR_SSB_DATA_MASK     0x0400U
  #define QSPI2_SPDSR_SSB_IN_MASK       0x0800U
  #define QSPI2_SPDSR_BD2X_MASK         0x1000U
  #define QSPI2_SPDSR_RDMAEN_MASK       0x2000U
  #define QSPI2_SPDSR_TDMAEN_MASK       0x4000U
  #define QSPI2_SPDSR_WOM_MASK          0x8000U
  #define QSPI2_SPDSR_DS_MASK           0x0FU
  #define QSPI2_SPDSR_DS_BITNUM         0x00U
  #define QSPI2_SPDSR                   (*((volatile word *)0x0000E0D1))


  /*** QSPI2_SPDRR - SPI Data Receive Register; 0x0000E0D2 ***/
  union {
    word Word;
  } QSPI2_SPDRR_STR;

  #define QSPI2_SPDRR_R0_MASK           0x01U
  #define QSPI2_SPDRR_R1_MASK           0x02U
  #define QSPI2_SPDRR_R2_MASK           0x04U
  #define QSPI2_SPDRR_R3_MASK           0x08U
  #define QSPI2_SPDRR_R4_MASK           0x10U
  #define QSPI2_SPDRR_R5_MASK           0x20U
  #define QSPI2_SPDRR_R6_MASK           0x40U
  #define QSPI2_SPDRR_R7_MASK           0x80U
  #define QSPI2_SPDRR_R8_MASK           0x0100U
  #define QSPI2_SPDRR_R9_MASK           0x0200U
  #define QSPI2_SPDRR_R10_MASK          0x0400U
  #define QSPI2_SPDRR_R11_MASK          0x0800U
  #define QSPI2_SPDRR_R12_MASK          0x1000U
  #define QSPI2_SPDRR_R13_MASK          0x2000U
  #define QSPI2_SPDRR_R14_MASK          0x4000U
  #define QSPI2_SPDRR_R15_MASK          0x8000U
  #define QSPI2_SPDRR                   (*((volatile word *)0x0000E0D2))


  /*** QSPI2_SPDTR - SPI Data Transmit Register; 0x0000E0D3 ***/
  union {
    word Word;
  } QSPI2_SPDTR_STR;

  #define QSPI2_SPDTR_T0_MASK           0x01U
  #define QSPI2_SPDTR_T1_MASK           0x02U
  #define QSPI2_SPDTR_T2_MASK           0x04U
  #define QSPI2_SPDTR_T3_MASK           0x08U
  #define QSPI2_SPDTR_T4_MASK           0x10U
  #define QSPI2_SPDTR_T5_MASK           0x20U
  #define QSPI2_SPDTR_T6_MASK           0x40U
  #define QSPI2_SPDTR_T7_MASK           0x80U
  #define QSPI2_SPDTR_T8_MASK           0x0100U
  #define QSPI2_SPDTR_T9_MASK           0x0200U
  #define QSPI2_SPDTR_T10_MASK          0x0400U
  #define QSPI2_SPDTR_T11_MASK          0x0800U
  #define QSPI2_SPDTR_T12_MASK          0x1000U
  #define QSPI2_SPDTR_T13_MASK          0x2000U
  #define QSPI2_SPDTR_T14_MASK          0x4000U
  #define QSPI2_SPDTR_T15_MASK          0x8000U
  #define QSPI2_SPDTR                   (*((volatile word *)0x0000E0D3))


  /*** QSPI2_SPFIFO - SPI FIFO Control Register; 0x0000E0D4 ***/
  union {
    word Word;
  } QSPI2_SPFIFO_STR;

  #define QSPI2_SPFIFO_FIFO_ENA_MASK    0x01U
  #define QSPI2_SPFIFO_RFWM0_MASK       0x04U
  #define QSPI2_SPFIFO_RFWM1_MASK       0x08U
  #define QSPI2_SPFIFO_TFWM0_MASK       0x20U
  #define QSPI2_SPFIFO_TFWM1_MASK       0x40U
  #define QSPI2_SPFIFO_RFCNT0_MASK      0x0100U
  #define QSPI2_SPFIFO_RFCNT1_MASK      0x0200U
  #define QSPI2_SPFIFO_RFCNT2_MASK      0x0400U
  #define QSPI2_SPFIFO_TFCNT0_MASK      0x1000U
  #define QSPI2_SPFIFO_TFCNT1_MASK      0x2000U
  #define QSPI2_SPFIFO_TFCNT2_MASK      0x4000U
  #define QSPI2_SPFIFO_RFWM_MASK        0x0CU
  #define QSPI2_SPFIFO_RFWM_BITNUM      0x02U
  #define QSPI2_SPFIFO_TFWM_MASK        0x60U
  #define QSPI2_SPFIFO_TFWM_BITNUM      0x05U
  #define QSPI2_SPFIFO_RFCNT_MASK       0x0700U
  #define QSPI2_SPFIFO_RFCNT_BITNUM     0x08U
  #define QSPI2_SPFIFO_TFCNT_MASK       0x7000U
  #define QSPI2_SPFIFO_TFCNT_BITNUM     0x0CU
  #define QSPI2_SPFIFO                  (*((volatile word *)0x0000E0D4))


  /*** QSPI2_SPWAIT - SPI Word Delay Register; 0x0000E0D5 ***/
  union {
    word Word;
  } QSPI2_SPWAIT_STR;

  #define QSPI2_SPWAIT_WAIT0_MASK       0x01U
  #define QSPI2_SPWAIT_WAIT1_MASK       0x02U
  #define QSPI2_SPWAIT_WAIT2_MASK       0x04U
  #define QSPI2_SPWAIT_WAIT3_MASK       0x08U
  #define QSPI2_SPWAIT_WAIT4_MASK       0x10U
  #define QSPI2_SPWAIT_WAIT5_MASK       0x20U
  #define QSPI2_SPWAIT_WAIT6_MASK       0x40U
  #define QSPI2_SPWAIT_WAIT7_MASK       0x80U
  #define QSPI2_SPWAIT_WAIT8_MASK       0x0100U
  #define QSPI2_SPWAIT_WAIT9_MASK       0x0200U
  #define QSPI2_SPWAIT_WAIT10_MASK      0x0400U
  #define QSPI2_SPWAIT_WAIT11_MASK      0x0800U
  #define QSPI2_SPWAIT_WAIT12_MASK      0x1000U
  #define QSPI2_SPWAIT_WAIT_MASK        0x1FFFU
  #define QSPI2_SPWAIT_WAIT_BITNUM      0x00U
  #define QSPI2_SPWAIT                  (*((volatile word *)0x0000E0D5))


  /*** QSPI2_SPCTL2 - SPI Control Register 2; 0x0000E0D6 ***/
  union {
    word Word;
  } QSPI2_SPCTL2_STR;

  #define QSPI2_SPCTL2_SHEN_MASK        0x01U
  #define QSPI2_SPCTL2                  (*((volatile word *)0x0000E0D6))


} QSPI2_PRPH;
/******************************************
*** Peripheral I2C0
*******************************************/
typedef volatile struct {
  /*** I2C0_A1 - I2C Address Register 1; 0x0000E0E0 ***/
  union {
    word Word;
  } I2C0_A1_STR;

  #define I2C0_A1_AD0_MASK              0x02U
  #define I2C0_A1_AD1_MASK              0x04U
  #define I2C0_A1_AD2_MASK              0x08U
  #define I2C0_A1_AD3_MASK              0x10U
  #define I2C0_A1_AD4_MASK              0x20U
  #define I2C0_A1_AD5_MASK              0x40U
  #define I2C0_A1_AD6_MASK              0x80U
  #define I2C0_A1_AD_MASK               0xFEU
  #define I2C0_A1_AD_BITNUM             0x01U
  #define I2C0_A1                       (*((volatile word *)0x0000E0E0))


  /*** I2C0_F - I2C Frequency Divider register; 0x0000E0E1 ***/
  union {
    word Word;
  } I2C0_F_STR;

  #define I2C0_F_ICR0_MASK              0x01U
  #define I2C0_F_ICR1_MASK              0x02U
  #define I2C0_F_ICR2_MASK              0x04U
  #define I2C0_F_ICR3_MASK              0x08U
  #define I2C0_F_ICR4_MASK              0x10U
  #define I2C0_F_ICR5_MASK              0x20U
  #define I2C0_F_MULT0_MASK             0x40U
  #define I2C0_F_MULT1_MASK             0x80U
  #define I2C0_F_ICR_MASK               0x3FU
  #define I2C0_F_ICR_BITNUM             0x00U
  #define I2C0_F_MULT_MASK              0xC0U
  #define I2C0_F_MULT_BITNUM            0x06U
  #define I2C0_F                        (*((volatile word *)0x0000E0E1))


  /*** I2C0_C1 - I2C Control Register 1; 0x0000E0E2 ***/
  union {
    word Word;
  } I2C0_C1_STR;

  #define I2C0_C1_DMAEN_MASK            0x01U
  #define I2C0_C1_WUEN_MASK             0x02U
  #define I2C0_C1_RSTA_MASK             0x04U
  #define I2C0_C1_TXAK_MASK             0x08U
  #define I2C0_C1_TX_MASK               0x10U
  #define I2C0_C1_MST_MASK              0x20U
  #define I2C0_C1_IICIE_MASK            0x40U
  #define I2C0_C1_IICEN_MASK            0x80U
  #define I2C0_C1                       (*((volatile word *)0x0000E0E2))


  /*** I2C0_S - I2C Status Register; 0x0000E0E3 ***/
  union {
    word Word;
  } I2C0_S_STR;

  #define I2C0_S_RXAK_MASK              0x01U
  #define I2C0_S_IICIF_MASK             0x02U
  #define I2C0_S_SRW_MASK               0x04U
  #define I2C0_S_RAM_MASK               0x08U
  #define I2C0_S_ARBL_MASK              0x10U
  #define I2C0_S_BUSY_MASK              0x20U
  #define I2C0_S_IAAS_MASK              0x40U
  #define I2C0_S_TCF_MASK               0x80U
  #define I2C0_S                        (*((volatile word *)0x0000E0E3))


  /*** I2C0_D - I2C Data I/O register; 0x0000E0E4 ***/
  union {
    word Word;
  } I2C0_D_STR;

  #define I2C0_D_DATA0_MASK             0x01U
  #define I2C0_D_DATA1_MASK             0x02U
  #define I2C0_D_DATA2_MASK             0x04U
  #define I2C0_D_DATA3_MASK             0x08U
  #define I2C0_D_DATA4_MASK             0x10U
  #define I2C0_D_DATA5_MASK             0x20U
  #define I2C0_D_DATA6_MASK             0x40U
  #define I2C0_D_DATA7_MASK             0x80U
  #define I2C0_D_DATA_MASK              0xFFU
  #define I2C0_D_DATA_BITNUM            0x00U
  #define I2C0_D                        (*((volatile word *)0x0000E0E4))


  /*** I2C0_C2 - I2C Control Register 2; 0x0000E0E5 ***/
  union {
    word Word;
  } I2C0_C2_STR;

  #define I2C0_C2_AD0_MASK              0x01U
  #define I2C0_C2_AD1_MASK              0x02U
  #define I2C0_C2_AD2_MASK              0x04U
  #define I2C0_C2_RMEN_MASK             0x08U
  #define I2C0_C2_SBRC_MASK             0x10U
  #define I2C0_C2_HDRS_MASK             0x20U
  #define I2C0_C2_ADEXT_MASK            0x40U
  #define I2C0_C2_GCAEN_MASK            0x80U
  #define I2C0_C2_AD_MASK               0x07U
  #define I2C0_C2_AD_BITNUM             0x00U
  #define I2C0_C2                       (*((volatile word *)0x0000E0E5))


  /*** I2C0_FLT - I2C Programmable Input Glitch Filter register; 0x0000E0E6 ***/
  union {
    word Word;
  } I2C0_FLT_STR;

  #define I2C0_FLT_FLT0_MASK            0x01U
  #define I2C0_FLT_FLT1_MASK            0x02U
  #define I2C0_FLT_FLT2_MASK            0x04U
  #define I2C0_FLT_FLT3_MASK            0x08U
  #define I2C0_FLT_FLT4_MASK            0x10U
  #define I2C0_FLT_SHEN_MASK            0x80U
  #define I2C0_FLT_FLT_MASK             0x1FU
  #define I2C0_FLT_FLT_BITNUM           0x00U
  #define I2C0_FLT                      (*((volatile word *)0x0000E0E6))


  /*** I2C0_RA - I2C Range Address register; 0x0000E0E7 ***/
  union {
    word Word;
  } I2C0_RA_STR;

  #define I2C0_RA_RAD0_MASK             0x02U
  #define I2C0_RA_RAD1_MASK             0x04U
  #define I2C0_RA_RAD2_MASK             0x08U
  #define I2C0_RA_RAD3_MASK             0x10U
  #define I2C0_RA_RAD4_MASK             0x20U
  #define I2C0_RA_RAD5_MASK             0x40U
  #define I2C0_RA_RAD6_MASK             0x80U
  #define I2C0_RA_RAD_MASK              0xFEU
  #define I2C0_RA_RAD_BITNUM            0x01U
  #define I2C0_RA                       (*((volatile word *)0x0000E0E7))


  /*** I2C0_SMB - I2C SMBus Control and Status register; 0x0000E0E8 ***/
  union {
    word Word;
  } I2C0_SMB_STR;

  #define I2C0_SMB_SHTF2IE_MASK         0x01U
  #define I2C0_SMB_SHTF2_MASK           0x02U
  #define I2C0_SMB_SHTF1_MASK           0x04U
  #define I2C0_SMB_SLTF_MASK            0x08U
  #define I2C0_SMB_TCKSEL_MASK          0x10U
  #define I2C0_SMB_SIICAEN_MASK         0x20U
  #define I2C0_SMB_ALERTEN_MASK         0x40U
  #define I2C0_SMB_FACK_MASK            0x80U
  #define I2C0_SMB                      (*((volatile word *)0x0000E0E8))


  /*** I2C0_A2 - I2C Address Register 2; 0x0000E0E9 ***/
  union {
    word Word;
  } I2C0_A2_STR;

  #define I2C0_A2_SAD0_MASK             0x02U
  #define I2C0_A2_SAD1_MASK             0x04U
  #define I2C0_A2_SAD2_MASK             0x08U
  #define I2C0_A2_SAD3_MASK             0x10U
  #define I2C0_A2_SAD4_MASK             0x20U
  #define I2C0_A2_SAD5_MASK             0x40U
  #define I2C0_A2_SAD6_MASK             0x80U
  #define I2C0_A2_SAD_MASK              0xFEU
  #define I2C0_A2_SAD_BITNUM            0x01U
  #define I2C0_A2                       (*((volatile word *)0x0000E0E9))


  /*** I2C0_SLTH - I2C SCL Low Timeout Register High; 0x0000E0EA ***/
  union {
    word Word;
  } I2C0_SLTH_STR;

  #define I2C0_SLTH_SSLT0_MASK          0x01U
  #define I2C0_SLTH_SSLT1_MASK          0x02U
  #define I2C0_SLTH_SSLT2_MASK          0x04U
  #define I2C0_SLTH_SSLT3_MASK          0x08U
  #define I2C0_SLTH_SSLT4_MASK          0x10U
  #define I2C0_SLTH_SSLT5_MASK          0x20U
  #define I2C0_SLTH_SSLT6_MASK          0x40U
  #define I2C0_SLTH_SSLT7_MASK          0x80U
  #define I2C0_SLTH_SSLT_MASK           0xFFU
  #define I2C0_SLTH_SSLT_BITNUM         0x00U
  #define I2C0_SLTH                     (*((volatile word *)0x0000E0EA))


  /*** I2C0_SLTL - I2C SCL Low Timeout Register Low; 0x0000E0EB ***/
  union {
    word Word;
  } I2C0_SLTL_STR;

  #define I2C0_SLTL_SSLT0_MASK          0x01U
  #define I2C0_SLTL_SSLT1_MASK          0x02U
  #define I2C0_SLTL_SSLT2_MASK          0x04U
  #define I2C0_SLTL_SSLT3_MASK          0x08U
  #define I2C0_SLTL_SSLT4_MASK          0x10U
  #define I2C0_SLTL_SSLT5_MASK          0x20U
  #define I2C0_SLTL_SSLT6_MASK          0x40U
  #define I2C0_SLTL_SSLT7_MASK          0x80U
  #define I2C0_SLTL_SSLT_MASK           0xFFU
  #define I2C0_SLTL_SSLT_BITNUM         0x00U
  #define I2C0_SLTL                     (*((volatile word *)0x0000E0EB))


} I2C0_PRPH;
/******************************************
*** Peripheral I2C1
*******************************************/
typedef volatile struct {
  /*** I2C1_A1 - I2C Address Register 1; 0x0000E0F0 ***/
  union {
    word Word;
  } I2C1_A1_STR;

  #define I2C1_A1_AD0_MASK              0x02U
  #define I2C1_A1_AD1_MASK              0x04U
  #define I2C1_A1_AD2_MASK              0x08U
  #define I2C1_A1_AD3_MASK              0x10U
  #define I2C1_A1_AD4_MASK              0x20U
  #define I2C1_A1_AD5_MASK              0x40U
  #define I2C1_A1_AD6_MASK              0x80U
  #define I2C1_A1_AD_MASK               0xFEU
  #define I2C1_A1_AD_BITNUM             0x01U
  #define I2C1_A1                       (*((volatile word *)0x0000E0F0))


  /*** I2C1_F - I2C Frequency Divider register; 0x0000E0F1 ***/
  union {
    word Word;
  } I2C1_F_STR;

  #define I2C1_F_ICR0_MASK              0x01U
  #define I2C1_F_ICR1_MASK              0x02U
  #define I2C1_F_ICR2_MASK              0x04U
  #define I2C1_F_ICR3_MASK              0x08U
  #define I2C1_F_ICR4_MASK              0x10U
  #define I2C1_F_ICR5_MASK              0x20U
  #define I2C1_F_MULT0_MASK             0x40U
  #define I2C1_F_MULT1_MASK             0x80U
  #define I2C1_F_ICR_MASK               0x3FU
  #define I2C1_F_ICR_BITNUM             0x00U
  #define I2C1_F_MULT_MASK              0xC0U
  #define I2C1_F_MULT_BITNUM            0x06U
  #define I2C1_F                        (*((volatile word *)0x0000E0F1))


  /*** I2C1_C1 - I2C Control Register 1; 0x0000E0F2 ***/
  union {
    word Word;
  } I2C1_C1_STR;

  #define I2C1_C1_DMAEN_MASK            0x01U
  #define I2C1_C1_WUEN_MASK             0x02U
  #define I2C1_C1_RSTA_MASK             0x04U
  #define I2C1_C1_TXAK_MASK             0x08U
  #define I2C1_C1_TX_MASK               0x10U
  #define I2C1_C1_MST_MASK              0x20U
  #define I2C1_C1_IICIE_MASK            0x40U
  #define I2C1_C1_IICEN_MASK            0x80U
  #define I2C1_C1                       (*((volatile word *)0x0000E0F2))


  /*** I2C1_S - I2C Status Register; 0x0000E0F3 ***/
  union {
    word Word;
  } I2C1_S_STR;

  #define I2C1_S_RXAK_MASK              0x01U
  #define I2C1_S_IICIF_MASK             0x02U
  #define I2C1_S_SRW_MASK               0x04U
  #define I2C1_S_RAM_MASK               0x08U
  #define I2C1_S_ARBL_MASK              0x10U
  #define I2C1_S_BUSY_MASK              0x20U
  #define I2C1_S_IAAS_MASK              0x40U
  #define I2C1_S_TCF_MASK               0x80U
  #define I2C1_S                        (*((volatile word *)0x0000E0F3))


  /*** I2C1_D - I2C Data I/O register; 0x0000E0F4 ***/
  union {
    word Word;
  } I2C1_D_STR;

  #define I2C1_D_DATA0_MASK             0x01U
  #define I2C1_D_DATA1_MASK             0x02U
  #define I2C1_D_DATA2_MASK             0x04U
  #define I2C1_D_DATA3_MASK             0x08U
  #define I2C1_D_DATA4_MASK             0x10U
  #define I2C1_D_DATA5_MASK             0x20U
  #define I2C1_D_DATA6_MASK             0x40U
  #define I2C1_D_DATA7_MASK             0x80U
  #define I2C1_D_DATA_MASK              0xFFU
  #define I2C1_D_DATA_BITNUM            0x00U
  #define I2C1_D                        (*((volatile word *)0x0000E0F4))


  /*** I2C1_C2 - I2C Control Register 2; 0x0000E0F5 ***/
  union {
    word Word;
  } I2C1_C2_STR;

  #define I2C1_C2_AD0_MASK              0x01U
  #define I2C1_C2_AD1_MASK              0x02U
  #define I2C1_C2_AD2_MASK              0x04U
  #define I2C1_C2_RMEN_MASK             0x08U
  #define I2C1_C2_SBRC_MASK             0x10U
  #define I2C1_C2_HDRS_MASK             0x20U
  #define I2C1_C2_ADEXT_MASK            0x40U
  #define I2C1_C2_GCAEN_MASK            0x80U
  #define I2C1_C2_AD_MASK               0x07U
  #define I2C1_C2_AD_BITNUM             0x00U
  #define I2C1_C2                       (*((volatile word *)0x0000E0F5))


  /*** I2C1_FLT - I2C Programmable Input Glitch Filter register; 0x0000E0F6 ***/
  union {
    word Word;
  } I2C1_FLT_STR;

  #define I2C1_FLT_FLT0_MASK            0x01U
  #define I2C1_FLT_FLT1_MASK            0x02U
  #define I2C1_FLT_FLT2_MASK            0x04U
  #define I2C1_FLT_FLT3_MASK            0x08U
  #define I2C1_FLT_FLT4_MASK            0x10U
  #define I2C1_FLT_SHEN_MASK            0x80U
  #define I2C1_FLT_FLT_MASK             0x1FU
  #define I2C1_FLT_FLT_BITNUM           0x00U
  #define I2C1_FLT                      (*((volatile word *)0x0000E0F6))


  /*** I2C1_RA - I2C Range Address register; 0x0000E0F7 ***/
  union {
    word Word;
  } I2C1_RA_STR;

  #define I2C1_RA_RAD0_MASK             0x02U
  #define I2C1_RA_RAD1_MASK             0x04U
  #define I2C1_RA_RAD2_MASK             0x08U
  #define I2C1_RA_RAD3_MASK             0x10U
  #define I2C1_RA_RAD4_MASK             0x20U
  #define I2C1_RA_RAD5_MASK             0x40U
  #define I2C1_RA_RAD6_MASK             0x80U
  #define I2C1_RA_RAD_MASK              0xFEU
  #define I2C1_RA_RAD_BITNUM            0x01U
  #define I2C1_RA                       (*((volatile word *)0x0000E0F7))


  /*** I2C1_SMB - I2C SMBus Control and Status register; 0x0000E0F8 ***/
  union {
    word Word;
  } I2C1_SMB_STR;

  #define I2C1_SMB_SHTF2IE_MASK         0x01U
  #define I2C1_SMB_SHTF2_MASK           0x02U
  #define I2C1_SMB_SHTF1_MASK           0x04U
  #define I2C1_SMB_SLTF_MASK            0x08U
  #define I2C1_SMB_TCKSEL_MASK          0x10U
  #define I2C1_SMB_SIICAEN_MASK         0x20U
  #define I2C1_SMB_ALERTEN_MASK         0x40U
  #define I2C1_SMB_FACK_MASK            0x80U
  #define I2C1_SMB                      (*((volatile word *)0x0000E0F8))


  /*** I2C1_A2 - I2C Address Register 2; 0x0000E0F9 ***/
  union {
    word Word;
  } I2C1_A2_STR;

  #define I2C1_A2_SAD0_MASK             0x02U
  #define I2C1_A2_SAD1_MASK             0x04U
  #define I2C1_A2_SAD2_MASK             0x08U
  #define I2C1_A2_SAD3_MASK             0x10U
  #define I2C1_A2_SAD4_MASK             0x20U
  #define I2C1_A2_SAD5_MASK             0x40U
  #define I2C1_A2_SAD6_MASK             0x80U
  #define I2C1_A2_SAD_MASK              0xFEU
  #define I2C1_A2_SAD_BITNUM            0x01U
  #define I2C1_A2                       (*((volatile word *)0x0000E0F9))


  /*** I2C1_SLTH - I2C SCL Low Timeout Register High; 0x0000E0FA ***/
  union {
    word Word;
  } I2C1_SLTH_STR;

  #define I2C1_SLTH_SSLT0_MASK          0x01U
  #define I2C1_SLTH_SSLT1_MASK          0x02U
  #define I2C1_SLTH_SSLT2_MASK          0x04U
  #define I2C1_SLTH_SSLT3_MASK          0x08U
  #define I2C1_SLTH_SSLT4_MASK          0x10U
  #define I2C1_SLTH_SSLT5_MASK          0x20U
  #define I2C1_SLTH_SSLT6_MASK          0x40U
  #define I2C1_SLTH_SSLT7_MASK          0x80U
  #define I2C1_SLTH_SSLT_MASK           0xFFU
  #define I2C1_SLTH_SSLT_BITNUM         0x00U
  #define I2C1_SLTH                     (*((volatile word *)0x0000E0FA))


  /*** I2C1_SLTL - I2C SCL Low Timeout Register Low; 0x0000E0FB ***/
  union {
    word Word;
  } I2C1_SLTL_STR;

  #define I2C1_SLTL_SSLT0_MASK          0x01U
  #define I2C1_SLTL_SSLT1_MASK          0x02U
  #define I2C1_SLTL_SSLT2_MASK          0x04U
  #define I2C1_SLTL_SSLT3_MASK          0x08U
  #define I2C1_SLTL_SSLT4_MASK          0x10U
  #define I2C1_SLTL_SSLT5_MASK          0x20U
  #define I2C1_SLTL_SSLT6_MASK          0x40U
  #define I2C1_SLTL_SSLT7_MASK          0x80U
  #define I2C1_SLTL_SSLT_MASK           0xFFU
  #define I2C1_SLTL_SSLT_BITNUM         0x00U
  #define I2C1_SLTL                     (*((volatile word *)0x0000E0FB))


} I2C1_PRPH;
/******************************************
*** Peripheral PIT0
*******************************************/
typedef volatile struct {
  /*** PIT0_CTRL - PIT Control Register; 0x0000E100 ***/
  union {
    word Word;
  } PIT0_CTRL_STR;

  #define PIT0_CTRL_CNT_EN_MASK         0x01U
  #define PIT0_CTRL_PRIE_MASK           0x02U
  #define PIT0_CTRL_PRF_MASK            0x04U
  #define PIT0_CTRL_PRESCALER0_MASK     0x08U
  #define PIT0_CTRL_PRESCALER1_MASK     0x10U
  #define PIT0_CTRL_PRESCALER2_MASK     0x20U
  #define PIT0_CTRL_PRESCALER3_MASK     0x40U
  #define PIT0_CTRL_CLKSEL0_MASK        0x0100U
  #define PIT0_CTRL_CLKSEL1_MASK        0x0200U
  #define PIT0_CTRL_SLAVE_MASK          0x8000U
  #define PIT0_CTRL_PRESCALER_MASK      0x78U
  #define PIT0_CTRL_PRESCALER_BITNUM    0x03U
  #define PIT0_CTRL_CLKSEL_MASK         0x0300U
  #define PIT0_CTRL_CLKSEL_BITNUM       0x08U
  #define PIT0_CTRL                     (*((volatile word *)0x0000E100))


  /*** PIT0_MOD - PIT Modulo Register; 0x0000E101 ***/
  union {
    word Word;
  } PIT0_MOD_STR;

  #define PIT0_MOD                      (*((volatile word *)0x0000E101))


  /*** PIT0_CNTR - PIT Counter Register; 0x0000E102 ***/
  union {
    word Word;
  } PIT0_CNTR_STR;

  #define PIT0_CNTR                     (*((volatile word *)0x0000E102))


} PIT0_PRPH;
/******************************************
*** Peripheral PIT1
*******************************************/
typedef volatile struct {
  /*** PIT1_CTRL - PIT Control Register; 0x0000E110 ***/
  union {
    word Word;
  } PIT1_CTRL_STR;

  #define PIT1_CTRL_CNT_EN_MASK         0x01U
  #define PIT1_CTRL_PRIE_MASK           0x02U
  #define PIT1_CTRL_PRF_MASK            0x04U
  #define PIT1_CTRL_PRESCALER0_MASK     0x08U
  #define PIT1_CTRL_PRESCALER1_MASK     0x10U
  #define PIT1_CTRL_PRESCALER2_MASK     0x20U
  #define PIT1_CTRL_PRESCALER3_MASK     0x40U
  #define PIT1_CTRL_CLKSEL0_MASK        0x0100U
  #define PIT1_CTRL_CLKSEL1_MASK        0x0200U
  #define PIT1_CTRL_SLAVE_MASK          0x8000U
  #define PIT1_CTRL_PRESCALER_MASK      0x78U
  #define PIT1_CTRL_PRESCALER_BITNUM    0x03U
  #define PIT1_CTRL_CLKSEL_MASK         0x0300U
  #define PIT1_CTRL_CLKSEL_BITNUM       0x08U
  #define PIT1_CTRL                     (*((volatile word *)0x0000E110))


  /*** PIT1_MOD - PIT Modulo Register; 0x0000E111 ***/
  union {
    word Word;
  } PIT1_MOD_STR;

  #define PIT1_MOD                      (*((volatile word *)0x0000E111))


  /*** PIT1_CNTR - PIT Counter Register; 0x0000E112 ***/
  union {
    word Word;
  } PIT1_CNTR_STR;

  #define PIT1_CNTR                     (*((volatile word *)0x0000E112))


} PIT1_PRPH;
/******************************************
*** Peripheral PDB0
*******************************************/
typedef volatile struct {
  /*** PDB0_MCTRL - Master Control Register; 0x0000E120 ***/
  union {
    word Word;
  } PDB0_MCTRL_STR;

  #define PDB0_MCTRL_PDBEN_MASK         0x01U
  #define PDB0_MCTRL_TRIGSEL0_MASK      0x10U
  #define PDB0_MCTRL_TRIGSEL1_MASK      0x20U
  #define PDB0_MCTRL_TRIGSEL2_MASK      0x40U
  #define PDB0_MCTRL_SWTRIG_MASK        0x80U
  #define PDB0_MCTRL_COIE_MASK          0x0100U
  #define PDB0_MCTRL_COF_MASK           0x0200U
  #define PDB0_MCTRL_CONT_MASK          0x0400U
  #define PDB0_MCTRL_LDOK_MASK          0x0800U
  #define PDB0_MCTRL_LDMOD_MASK         0x1000U
  #define PDB0_MCTRL_PRESCALER0_MASK    0x2000U
  #define PDB0_MCTRL_PRESCALER1_MASK    0x4000U
  #define PDB0_MCTRL_PRESCALER2_MASK    0x8000U
  #define PDB0_MCTRL_TRIGSEL_MASK       0x70U
  #define PDB0_MCTRL_TRIGSEL_BITNUM     0x04U
  #define PDB0_MCTRL_PRESCALER_MASK     0xE000U
  #define PDB0_MCTRL_PRESCALER_BITNUM   0x0DU
  #define PDB0_MCTRL                    (*((volatile word *)0x0000E120))


  /*** PDB0_CTRLA - Control A Register; 0x0000E121 ***/
  union {
    word Word;
  } PDB0_CTRLA_STR;

  #define PDB0_CTRLA_ENB_MASK           0x01U
  #define PDB0_CTRLA_ENA_MASK           0x02U
  #define PDB0_CTRLA_BYPB_MASK          0x04U
  #define PDB0_CTRLA_BYPA_MASK          0x08U
  #define PDB0_CTRLA_ABSEL_MASK         0x10U
  #define PDB0_CTRLA_AINIT_MASK         0x20U
  #define PDB0_CTRLA_DBIE_MASK          0x0100U
  #define PDB0_CTRLA_DBF_MASK           0x0200U
  #define PDB0_CTRLA_DAIE_MASK          0x0400U
  #define PDB0_CTRLA_DAF_MASK           0x0800U
  #define PDB0_CTRLA_FLENA_MASK         0x1000U
  #define PDB0_CTRLA_FPOLA_MASK         0x2000U
  #define PDB0_CTRLA_FLTAEN_MASK        0x4000U
  #define PDB0_CTRLA_FLTA_MASK          0x8000U
  #define PDB0_CTRLA                    (*((volatile word *)0x0000E121))


  /*** PDB0_CTRLC - Control C Register; 0x0000E122 ***/
  union {
    word Word;
  } PDB0_CTRLC_STR;

  #define PDB0_CTRLC_END_MASK           0x01U
  #define PDB0_CTRLC_ENC_MASK           0x02U
  #define PDB0_CTRLC_BYPD_MASK          0x04U
  #define PDB0_CTRLC_BYPC_MASK          0x08U
  #define PDB0_CTRLC_CDSEL_MASK         0x10U
  #define PDB0_CTRLC_CINIT_MASK         0x20U
  #define PDB0_CTRLC_DDIE_MASK          0x0100U
  #define PDB0_CTRLC_DDF_MASK           0x0200U
  #define PDB0_CTRLC_DCIE_MASK          0x0400U
  #define PDB0_CTRLC_DCF_MASK           0x0800U
  #define PDB0_CTRLC_FLENC_MASK         0x1000U
  #define PDB0_CTRLC_FPOLC_MASK         0x2000U
  #define PDB0_CTRLC_FLTCEN_MASK        0x4000U
  #define PDB0_CTRLC_FLTC_MASK          0x8000U
  #define PDB0_CTRLC                    (*((volatile word *)0x0000E122))


  /*** PDB0_DELAYA - DelayA Register; 0x0000E123 ***/
  union {
    word Word;
  } PDB0_DELAYA_STR;

  #define PDB0_DELAYA                   (*((volatile word *)0x0000E123))


  /*** PDB0_DELAYB - DelayB Register; 0x0000E124 ***/
  union {
    word Word;
  } PDB0_DELAYB_STR;

  #define PDB0_DELAYB                   (*((volatile word *)0x0000E124))


  /*** PDB0_DELAYC - DelayC Register; 0x0000E125 ***/
  union {
    word Word;
  } PDB0_DELAYC_STR;

  #define PDB0_DELAYC                   (*((volatile word *)0x0000E125))


  /*** PDB0_DELAYD - DelayD Register; 0x0000E126 ***/
  union {
    word Word;
  } PDB0_DELAYD_STR;

  #define PDB0_DELAYD                   (*((volatile word *)0x0000E126))


  /*** PDB0_MOD - Modulus Register; 0x0000E127 ***/
  union {
    word Word;
  } PDB0_MOD_STR;

  #define PDB0_MOD                      (*((volatile word *)0x0000E127))


  /*** PDB0_CNTR - Counter Register; 0x0000E128 ***/
  union {
    word Word;
  } PDB0_CNTR_STR;

  #define PDB0_CNTR                     (*((volatile word *)0x0000E128))


} PDB0_PRPH;
/******************************************
*** Peripheral PDB1
*******************************************/
typedef volatile struct {
  /*** PDB1_MCTRL - Master Control Register; 0x0000E130 ***/
  union {
    word Word;
  } PDB1_MCTRL_STR;

  #define PDB1_MCTRL_PDBEN_MASK         0x01U
  #define PDB1_MCTRL_TRIGSEL0_MASK      0x10U
  #define PDB1_MCTRL_TRIGSEL1_MASK      0x20U
  #define PDB1_MCTRL_TRIGSEL2_MASK      0x40U
  #define PDB1_MCTRL_SWTRIG_MASK        0x80U
  #define PDB1_MCTRL_COIE_MASK          0x0100U
  #define PDB1_MCTRL_COF_MASK           0x0200U
  #define PDB1_MCTRL_CONT_MASK          0x0400U
  #define PDB1_MCTRL_LDOK_MASK          0x0800U
  #define PDB1_MCTRL_LDMOD_MASK         0x1000U
  #define PDB1_MCTRL_PRESCALER0_MASK    0x2000U
  #define PDB1_MCTRL_PRESCALER1_MASK    0x4000U
  #define PDB1_MCTRL_PRESCALER2_MASK    0x8000U
  #define PDB1_MCTRL_TRIGSEL_MASK       0x70U
  #define PDB1_MCTRL_TRIGSEL_BITNUM     0x04U
  #define PDB1_MCTRL_PRESCALER_MASK     0xE000U
  #define PDB1_MCTRL_PRESCALER_BITNUM   0x0DU
  #define PDB1_MCTRL                    (*((volatile word *)0x0000E130))


  /*** PDB1_CTRLA - Control A Register; 0x0000E131 ***/
  union {
    word Word;
  } PDB1_CTRLA_STR;

  #define PDB1_CTRLA_ENB_MASK           0x01U
  #define PDB1_CTRLA_ENA_MASK           0x02U
  #define PDB1_CTRLA_BYPB_MASK          0x04U
  #define PDB1_CTRLA_BYPA_MASK          0x08U
  #define PDB1_CTRLA_ABSEL_MASK         0x10U
  #define PDB1_CTRLA_AINIT_MASK         0x20U
  #define PDB1_CTRLA_DBIE_MASK          0x0100U
  #define PDB1_CTRLA_DBF_MASK           0x0200U
  #define PDB1_CTRLA_DAIE_MASK          0x0400U
  #define PDB1_CTRLA_DAF_MASK           0x0800U
  #define PDB1_CTRLA_FLENA_MASK         0x1000U
  #define PDB1_CTRLA_FPOLA_MASK         0x2000U
  #define PDB1_CTRLA_FLTAEN_MASK        0x4000U
  #define PDB1_CTRLA_FLTA_MASK          0x8000U
  #define PDB1_CTRLA                    (*((volatile word *)0x0000E131))


  /*** PDB1_CTRLC - Control C Register; 0x0000E132 ***/
  union {
    word Word;
  } PDB1_CTRLC_STR;

  #define PDB1_CTRLC_END_MASK           0x01U
  #define PDB1_CTRLC_ENC_MASK           0x02U
  #define PDB1_CTRLC_BYPD_MASK          0x04U
  #define PDB1_CTRLC_BYPC_MASK          0x08U
  #define PDB1_CTRLC_CDSEL_MASK         0x10U
  #define PDB1_CTRLC_CINIT_MASK         0x20U
  #define PDB1_CTRLC_DDIE_MASK          0x0100U
  #define PDB1_CTRLC_DDF_MASK           0x0200U
  #define PDB1_CTRLC_DCIE_MASK          0x0400U
  #define PDB1_CTRLC_DCF_MASK           0x0800U
  #define PDB1_CTRLC_FLENC_MASK         0x1000U
  #define PDB1_CTRLC_FPOLC_MASK         0x2000U
  #define PDB1_CTRLC_FLTCEN_MASK        0x4000U
  #define PDB1_CTRLC_FLTC_MASK          0x8000U
  #define PDB1_CTRLC                    (*((volatile word *)0x0000E132))


  /*** PDB1_DELAYA - DelayA Register; 0x0000E133 ***/
  union {
    word Word;
  } PDB1_DELAYA_STR;

  #define PDB1_DELAYA                   (*((volatile word *)0x0000E133))


  /*** PDB1_DELAYB - DelayB Register; 0x0000E134 ***/
  union {
    word Word;
  } PDB1_DELAYB_STR;

  #define PDB1_DELAYB                   (*((volatile word *)0x0000E134))


  /*** PDB1_DELAYC - DelayC Register; 0x0000E135 ***/
  union {
    word Word;
  } PDB1_DELAYC_STR;

  #define PDB1_DELAYC                   (*((volatile word *)0x0000E135))


  /*** PDB1_DELAYD - DelayD Register; 0x0000E136 ***/
  union {
    word Word;
  } PDB1_DELAYD_STR;

  #define PDB1_DELAYD                   (*((volatile word *)0x0000E136))


  /*** PDB1_MOD - Modulus Register; 0x0000E137 ***/
  union {
    word Word;
  } PDB1_MOD_STR;

  #define PDB1_MOD                      (*((volatile word *)0x0000E137))


  /*** PDB1_CNTR - Counter Register; 0x0000E138 ***/
  union {
    word Word;
  } PDB1_CNTR_STR;

  #define PDB1_CNTR                     (*((volatile word *)0x0000E138))


} PDB1_PRPH;
/******************************************
*** Peripheral TMRA
*******************************************/
typedef volatile struct {
  /*** TMRA_0_COMP1 - Timer Channel Compare Register 1; 0x0000E140 ***/
  union {
    word Word;
  } TMRA_0_COMP1_STR;

  #define TMRA_0_COMP1                  (*((volatile word *)0x0000E140))


  /*** TMRA_0_COMP2 - Timer Channel Compare Register 2; 0x0000E141 ***/
  union {
    word Word;
  } TMRA_0_COMP2_STR;

  #define TMRA_0_COMP2                  (*((volatile word *)0x0000E141))


  /*** TMRA_0_CAPT - Timer Channel Capture Register; 0x0000E142 ***/
  union {
    word Word;
  } TMRA_0_CAPT_STR;

  #define TMRA_0_CAPT                   (*((volatile word *)0x0000E142))


  /*** TMRA_0_LOAD - Timer Channel Load Register; 0x0000E143 ***/
  union {
    word Word;
  } TMRA_0_LOAD_STR;

  #define TMRA_0_LOAD                   (*((volatile word *)0x0000E143))


  /*** TMRA_0_HOLD - Timer Channel Hold Register; 0x0000E144 ***/
  union {
    word Word;
  } TMRA_0_HOLD_STR;

  #define TMRA_0_HOLD                   (*((volatile word *)0x0000E144))


  /*** TMRA_0_CNTR - Timer Channel Counter Register; 0x0000E145 ***/
  union {
    word Word;
  } TMRA_0_CNTR_STR;

  #define TMRA_0_CNTR                   (*((volatile word *)0x0000E145))


  /*** TMRA_0_CTRL - Timer Channel Control Register; 0x0000E146 ***/
  union {
    word Word;
  } TMRA_0_CTRL_STR;

  #define TMRA_0_CTRL_OUTMODE0_MASK     0x01U
  #define TMRA_0_CTRL_OUTMODE1_MASK     0x02U
  #define TMRA_0_CTRL_OUTMODE2_MASK     0x04U
  #define TMRA_0_CTRL_COINIT_MASK       0x08U
  #define TMRA_0_CTRL_DIR_MASK          0x10U
  #define TMRA_0_CTRL_LENGTH_MASK       0x20U
  #define TMRA_0_CTRL_ONCE_MASK         0x40U
  #define TMRA_0_CTRL_SCS0_MASK         0x80U
  #define TMRA_0_CTRL_SCS1_MASK         0x0100U
  #define TMRA_0_CTRL_PCS0_MASK         0x0200U
  #define TMRA_0_CTRL_PCS1_MASK         0x0400U
  #define TMRA_0_CTRL_PCS2_MASK         0x0800U
  #define TMRA_0_CTRL_PCS3_MASK         0x1000U
  #define TMRA_0_CTRL_CM0_MASK          0x2000U
  #define TMRA_0_CTRL_CM1_MASK          0x4000U
  #define TMRA_0_CTRL_CM2_MASK          0x8000U
  #define TMRA_0_CTRL_OUTMODE_MASK      0x07U
  #define TMRA_0_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRA_0_CTRL_SCS_MASK          0x0180U
  #define TMRA_0_CTRL_SCS_BITNUM        0x07U
  #define TMRA_0_CTRL_PCS_MASK          0x1E00U
  #define TMRA_0_CTRL_PCS_BITNUM        0x09U
  #define TMRA_0_CTRL_CM_MASK           0xE000U
  #define TMRA_0_CTRL_CM_BITNUM         0x0DU
  #define TMRA_0_CTRL                   (*((volatile word *)0x0000E146))


  /*** TMRA_0_SCTRL - Timer Channel Status and Control Register; 0x0000E147 ***/
  union {
    word Word;
  } TMRA_0_SCTRL_STR;

  #define TMRA_0_SCTRL_OEN_MASK         0x01U
  #define TMRA_0_SCTRL_OPS_MASK         0x02U
  #define TMRA_0_SCTRL_FORCE_MASK       0x04U
  #define TMRA_0_SCTRL_VAL_MASK         0x08U
  #define TMRA_0_SCTRL_EEOF_MASK        0x10U
  #define TMRA_0_SCTRL_MSTR_MASK        0x20U
  #define TMRA_0_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRA_0_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRA_0_SCTRL_INPUT_MASK       0x0100U
  #define TMRA_0_SCTRL_IPS_MASK         0x0200U
  #define TMRA_0_SCTRL_IEFIE_MASK       0x0400U
  #define TMRA_0_SCTRL_IEF_MASK         0x0800U
  #define TMRA_0_SCTRL_TOFIE_MASK       0x1000U
  #define TMRA_0_SCTRL_TOF_MASK         0x2000U
  #define TMRA_0_SCTRL_TCFIE_MASK       0x4000U
  #define TMRA_0_SCTRL_TCF_MASK         0x8000U
  #define TMRA_0_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRA_0_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRA_0_SCTRL                  (*((volatile word *)0x0000E147))


  /*** TMRA_0_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E148 ***/
  union {
    word Word;
  } TMRA_0_CMPLD1_STR;

  #define TMRA_0_CMPLD1                 (*((volatile word *)0x0000E148))


  /*** TMRA_0_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E149 ***/
  union {
    word Word;
  } TMRA_0_CMPLD2_STR;

  #define TMRA_0_CMPLD2                 (*((volatile word *)0x0000E149))


  /*** TMRA_0_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E14A ***/
  union {
    word Word;
  } TMRA_0_CSCTRL_STR;

  #define TMRA_0_CSCTRL_CL10_MASK       0x01U
  #define TMRA_0_CSCTRL_CL11_MASK       0x02U
  #define TMRA_0_CSCTRL_CL20_MASK       0x04U
  #define TMRA_0_CSCTRL_CL21_MASK       0x08U
  #define TMRA_0_CSCTRL_TCF1_MASK       0x10U
  #define TMRA_0_CSCTRL_TCF2_MASK       0x20U
  #define TMRA_0_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRA_0_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRA_0_CSCTRL_UP_MASK         0x0200U
  #define TMRA_0_CSCTRL_TCI_MASK        0x0400U
  #define TMRA_0_CSCTRL_ROC_MASK        0x0800U
  #define TMRA_0_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRA_0_CSCTRL_FAULT_MASK      0x2000U
  #define TMRA_0_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRA_0_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRA_0_CSCTRL_CL1_MASK        0x03U
  #define TMRA_0_CSCTRL_CL1_BITNUM      0x00U
  #define TMRA_0_CSCTRL_CL2_MASK        0x0CU
  #define TMRA_0_CSCTRL_CL2_BITNUM      0x02U
  #define TMRA_0_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRA_0_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRA_0_CSCTRL                 (*((volatile word *)0x0000E14A))


  /*** TMRA_0_FILT - Timer Channel Input Filter Register; 0x0000E14B ***/
  union {
    word Word;
  } TMRA_0_FILT_STR;

  #define TMRA_0_FILT_FILT_PER0_MASK    0x01U
  #define TMRA_0_FILT_FILT_PER1_MASK    0x02U
  #define TMRA_0_FILT_FILT_PER2_MASK    0x04U
  #define TMRA_0_FILT_FILT_PER3_MASK    0x08U
  #define TMRA_0_FILT_FILT_PER4_MASK    0x10U
  #define TMRA_0_FILT_FILT_PER5_MASK    0x20U
  #define TMRA_0_FILT_FILT_PER6_MASK    0x40U
  #define TMRA_0_FILT_FILT_PER7_MASK    0x80U
  #define TMRA_0_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRA_0_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRA_0_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRA_0_FILT_FILT_PER_MASK     0xFFU
  #define TMRA_0_FILT_FILT_PER_BITNUM   0x00U
  #define TMRA_0_FILT_FILT_CNT_MASK     0x0700U
  #define TMRA_0_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRA_0_FILT                   (*((volatile word *)0x0000E14B))


  /*** TMRA_0_DMA - Timer Channel DMA Enable Register; 0x0000E14C ***/
  union {
    word Word;
  } TMRA_0_DMA_STR;

  #define TMRA_0_DMA_IEFDE_MASK         0x01U
  #define TMRA_0_DMA_CMPLD1DE_MASK      0x02U
  #define TMRA_0_DMA_CMPLD2DE_MASK      0x04U
  #define TMRA_0_DMA                    (*((volatile word *)0x0000E14C))


  word Reserved0[2];                   /* Reserved (unused) registers */

  /*** TMRA_0_ENBL - Timer Channel Enable Register; 0x0000E14F ***/
  union {
    word Word;
  } TMRA_0_ENBL_STR;

  #define TMRA_0_ENBL_ENBL0_MASK        0x01U
  #define TMRA_0_ENBL_ENBL1_MASK        0x02U
  #define TMRA_0_ENBL_ENBL2_MASK        0x04U
  #define TMRA_0_ENBL_ENBL3_MASK        0x08U
  #define TMRA_0_ENBL_ENBL_MASK         0x0FU
  #define TMRA_0_ENBL_ENBL_BITNUM       0x00U
  #define TMRA_0_ENBL                   (*((volatile word *)0x0000E14F))


  /*** TMRA_1_COMP1 - Timer Channel Compare Register 1; 0x0000E150 ***/
  union {
    word Word;
  } TMRA_1_COMP1_STR;

  #define TMRA_1_COMP1                  (*((volatile word *)0x0000E150))


  /*** TMRA_1_COMP2 - Timer Channel Compare Register 2; 0x0000E151 ***/
  union {
    word Word;
  } TMRA_1_COMP2_STR;

  #define TMRA_1_COMP2                  (*((volatile word *)0x0000E151))


  /*** TMRA_1_CAPT - Timer Channel Capture Register; 0x0000E152 ***/
  union {
    word Word;
  } TMRA_1_CAPT_STR;

  #define TMRA_1_CAPT                   (*((volatile word *)0x0000E152))


  /*** TMRA_1_LOAD - Timer Channel Load Register; 0x0000E153 ***/
  union {
    word Word;
  } TMRA_1_LOAD_STR;

  #define TMRA_1_LOAD                   (*((volatile word *)0x0000E153))


  /*** TMRA_1_HOLD - Timer Channel Hold Register; 0x0000E154 ***/
  union {
    word Word;
  } TMRA_1_HOLD_STR;

  #define TMRA_1_HOLD                   (*((volatile word *)0x0000E154))


  /*** TMRA_1_CNTR - Timer Channel Counter Register; 0x0000E155 ***/
  union {
    word Word;
  } TMRA_1_CNTR_STR;

  #define TMRA_1_CNTR                   (*((volatile word *)0x0000E155))


  /*** TMRA_1_CTRL - Timer Channel Control Register; 0x0000E156 ***/
  union {
    word Word;
  } TMRA_1_CTRL_STR;

  #define TMRA_1_CTRL_OUTMODE0_MASK     0x01U
  #define TMRA_1_CTRL_OUTMODE1_MASK     0x02U
  #define TMRA_1_CTRL_OUTMODE2_MASK     0x04U
  #define TMRA_1_CTRL_COINIT_MASK       0x08U
  #define TMRA_1_CTRL_DIR_MASK          0x10U
  #define TMRA_1_CTRL_LENGTH_MASK       0x20U
  #define TMRA_1_CTRL_ONCE_MASK         0x40U
  #define TMRA_1_CTRL_SCS0_MASK         0x80U
  #define TMRA_1_CTRL_SCS1_MASK         0x0100U
  #define TMRA_1_CTRL_PCS0_MASK         0x0200U
  #define TMRA_1_CTRL_PCS1_MASK         0x0400U
  #define TMRA_1_CTRL_PCS2_MASK         0x0800U
  #define TMRA_1_CTRL_PCS3_MASK         0x1000U
  #define TMRA_1_CTRL_CM0_MASK          0x2000U
  #define TMRA_1_CTRL_CM1_MASK          0x4000U
  #define TMRA_1_CTRL_CM2_MASK          0x8000U
  #define TMRA_1_CTRL_OUTMODE_MASK      0x07U
  #define TMRA_1_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRA_1_CTRL_SCS_MASK          0x0180U
  #define TMRA_1_CTRL_SCS_BITNUM        0x07U
  #define TMRA_1_CTRL_PCS_MASK          0x1E00U
  #define TMRA_1_CTRL_PCS_BITNUM        0x09U
  #define TMRA_1_CTRL_CM_MASK           0xE000U
  #define TMRA_1_CTRL_CM_BITNUM         0x0DU
  #define TMRA_1_CTRL                   (*((volatile word *)0x0000E156))


  /*** TMRA_1_SCTRL - Timer Channel Status and Control Register; 0x0000E157 ***/
  union {
    word Word;
  } TMRA_1_SCTRL_STR;

  #define TMRA_1_SCTRL_OEN_MASK         0x01U
  #define TMRA_1_SCTRL_OPS_MASK         0x02U
  #define TMRA_1_SCTRL_FORCE_MASK       0x04U
  #define TMRA_1_SCTRL_VAL_MASK         0x08U
  #define TMRA_1_SCTRL_EEOF_MASK        0x10U
  #define TMRA_1_SCTRL_MSTR_MASK        0x20U
  #define TMRA_1_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRA_1_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRA_1_SCTRL_INPUT_MASK       0x0100U
  #define TMRA_1_SCTRL_IPS_MASK         0x0200U
  #define TMRA_1_SCTRL_IEFIE_MASK       0x0400U
  #define TMRA_1_SCTRL_IEF_MASK         0x0800U
  #define TMRA_1_SCTRL_TOFIE_MASK       0x1000U
  #define TMRA_1_SCTRL_TOF_MASK         0x2000U
  #define TMRA_1_SCTRL_TCFIE_MASK       0x4000U
  #define TMRA_1_SCTRL_TCF_MASK         0x8000U
  #define TMRA_1_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRA_1_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRA_1_SCTRL                  (*((volatile word *)0x0000E157))


  /*** TMRA_1_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E158 ***/
  union {
    word Word;
  } TMRA_1_CMPLD1_STR;

  #define TMRA_1_CMPLD1                 (*((volatile word *)0x0000E158))


  /*** TMRA_1_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E159 ***/
  union {
    word Word;
  } TMRA_1_CMPLD2_STR;

  #define TMRA_1_CMPLD2                 (*((volatile word *)0x0000E159))


  /*** TMRA_1_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E15A ***/
  union {
    word Word;
  } TMRA_1_CSCTRL_STR;

  #define TMRA_1_CSCTRL_CL10_MASK       0x01U
  #define TMRA_1_CSCTRL_CL11_MASK       0x02U
  #define TMRA_1_CSCTRL_CL20_MASK       0x04U
  #define TMRA_1_CSCTRL_CL21_MASK       0x08U
  #define TMRA_1_CSCTRL_TCF1_MASK       0x10U
  #define TMRA_1_CSCTRL_TCF2_MASK       0x20U
  #define TMRA_1_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRA_1_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRA_1_CSCTRL_UP_MASK         0x0200U
  #define TMRA_1_CSCTRL_TCI_MASK        0x0400U
  #define TMRA_1_CSCTRL_ROC_MASK        0x0800U
  #define TMRA_1_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRA_1_CSCTRL_FAULT_MASK      0x2000U
  #define TMRA_1_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRA_1_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRA_1_CSCTRL_CL1_MASK        0x03U
  #define TMRA_1_CSCTRL_CL1_BITNUM      0x00U
  #define TMRA_1_CSCTRL_CL2_MASK        0x0CU
  #define TMRA_1_CSCTRL_CL2_BITNUM      0x02U
  #define TMRA_1_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRA_1_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRA_1_CSCTRL                 (*((volatile word *)0x0000E15A))


  /*** TMRA_1_FILT - Timer Channel Input Filter Register; 0x0000E15B ***/
  union {
    word Word;
  } TMRA_1_FILT_STR;

  #define TMRA_1_FILT_FILT_PER0_MASK    0x01U
  #define TMRA_1_FILT_FILT_PER1_MASK    0x02U
  #define TMRA_1_FILT_FILT_PER2_MASK    0x04U
  #define TMRA_1_FILT_FILT_PER3_MASK    0x08U
  #define TMRA_1_FILT_FILT_PER4_MASK    0x10U
  #define TMRA_1_FILT_FILT_PER5_MASK    0x20U
  #define TMRA_1_FILT_FILT_PER6_MASK    0x40U
  #define TMRA_1_FILT_FILT_PER7_MASK    0x80U
  #define TMRA_1_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRA_1_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRA_1_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRA_1_FILT_FILT_PER_MASK     0xFFU
  #define TMRA_1_FILT_FILT_PER_BITNUM   0x00U
  #define TMRA_1_FILT_FILT_CNT_MASK     0x0700U
  #define TMRA_1_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRA_1_FILT                   (*((volatile word *)0x0000E15B))


  /*** TMRA_1_DMA - Timer Channel DMA Enable Register; 0x0000E15C ***/
  union {
    word Word;
  } TMRA_1_DMA_STR;

  #define TMRA_1_DMA_IEFDE_MASK         0x01U
  #define TMRA_1_DMA_CMPLD1DE_MASK      0x02U
  #define TMRA_1_DMA_CMPLD2DE_MASK      0x04U
  #define TMRA_1_DMA                    (*((volatile word *)0x0000E15C))


  word Reserved1[3];                   /* Reserved (unused) registers */

  /*** TMRA_2_COMP1 - Timer Channel Compare Register 1; 0x0000E160 ***/
  union {
    word Word;
  } TMRA_2_COMP1_STR;

  #define TMRA_2_COMP1                  (*((volatile word *)0x0000E160))


  /*** TMRA_2_COMP2 - Timer Channel Compare Register 2; 0x0000E161 ***/
  union {
    word Word;
  } TMRA_2_COMP2_STR;

  #define TMRA_2_COMP2                  (*((volatile word *)0x0000E161))


  /*** TMRA_2_CAPT - Timer Channel Capture Register; 0x0000E162 ***/
  union {
    word Word;
  } TMRA_2_CAPT_STR;

  #define TMRA_2_CAPT                   (*((volatile word *)0x0000E162))


  /*** TMRA_2_LOAD - Timer Channel Load Register; 0x0000E163 ***/
  union {
    word Word;
  } TMRA_2_LOAD_STR;

  #define TMRA_2_LOAD                   (*((volatile word *)0x0000E163))


  /*** TMRA_2_HOLD - Timer Channel Hold Register; 0x0000E164 ***/
  union {
    word Word;
  } TMRA_2_HOLD_STR;

  #define TMRA_2_HOLD                   (*((volatile word *)0x0000E164))


  /*** TMRA_2_CNTR - Timer Channel Counter Register; 0x0000E165 ***/
  union {
    word Word;
  } TMRA_2_CNTR_STR;

  #define TMRA_2_CNTR                   (*((volatile word *)0x0000E165))


  /*** TMRA_2_CTRL - Timer Channel Control Register; 0x0000E166 ***/
  union {
    word Word;
  } TMRA_2_CTRL_STR;

  #define TMRA_2_CTRL_OUTMODE0_MASK     0x01U
  #define TMRA_2_CTRL_OUTMODE1_MASK     0x02U
  #define TMRA_2_CTRL_OUTMODE2_MASK     0x04U
  #define TMRA_2_CTRL_COINIT_MASK       0x08U
  #define TMRA_2_CTRL_DIR_MASK          0x10U
  #define TMRA_2_CTRL_LENGTH_MASK       0x20U
  #define TMRA_2_CTRL_ONCE_MASK         0x40U
  #define TMRA_2_CTRL_SCS0_MASK         0x80U
  #define TMRA_2_CTRL_SCS1_MASK         0x0100U
  #define TMRA_2_CTRL_PCS0_MASK         0x0200U
  #define TMRA_2_CTRL_PCS1_MASK         0x0400U
  #define TMRA_2_CTRL_PCS2_MASK         0x0800U
  #define TMRA_2_CTRL_PCS3_MASK         0x1000U
  #define TMRA_2_CTRL_CM0_MASK          0x2000U
  #define TMRA_2_CTRL_CM1_MASK          0x4000U
  #define TMRA_2_CTRL_CM2_MASK          0x8000U
  #define TMRA_2_CTRL_OUTMODE_MASK      0x07U
  #define TMRA_2_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRA_2_CTRL_SCS_MASK          0x0180U
  #define TMRA_2_CTRL_SCS_BITNUM        0x07U
  #define TMRA_2_CTRL_PCS_MASK          0x1E00U
  #define TMRA_2_CTRL_PCS_BITNUM        0x09U
  #define TMRA_2_CTRL_CM_MASK           0xE000U
  #define TMRA_2_CTRL_CM_BITNUM         0x0DU
  #define TMRA_2_CTRL                   (*((volatile word *)0x0000E166))


  /*** TMRA_2_SCTRL - Timer Channel Status and Control Register; 0x0000E167 ***/
  union {
    word Word;
  } TMRA_2_SCTRL_STR;

  #define TMRA_2_SCTRL_OEN_MASK         0x01U
  #define TMRA_2_SCTRL_OPS_MASK         0x02U
  #define TMRA_2_SCTRL_FORCE_MASK       0x04U
  #define TMRA_2_SCTRL_VAL_MASK         0x08U
  #define TMRA_2_SCTRL_EEOF_MASK        0x10U
  #define TMRA_2_SCTRL_MSTR_MASK        0x20U
  #define TMRA_2_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRA_2_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRA_2_SCTRL_INPUT_MASK       0x0100U
  #define TMRA_2_SCTRL_IPS_MASK         0x0200U
  #define TMRA_2_SCTRL_IEFIE_MASK       0x0400U
  #define TMRA_2_SCTRL_IEF_MASK         0x0800U
  #define TMRA_2_SCTRL_TOFIE_MASK       0x1000U
  #define TMRA_2_SCTRL_TOF_MASK         0x2000U
  #define TMRA_2_SCTRL_TCFIE_MASK       0x4000U
  #define TMRA_2_SCTRL_TCF_MASK         0x8000U
  #define TMRA_2_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRA_2_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRA_2_SCTRL                  (*((volatile word *)0x0000E167))


  /*** TMRA_2_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E168 ***/
  union {
    word Word;
  } TMRA_2_CMPLD1_STR;

  #define TMRA_2_CMPLD1                 (*((volatile word *)0x0000E168))


  /*** TMRA_2_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E169 ***/
  union {
    word Word;
  } TMRA_2_CMPLD2_STR;

  #define TMRA_2_CMPLD2                 (*((volatile word *)0x0000E169))


  /*** TMRA_2_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E16A ***/
  union {
    word Word;
  } TMRA_2_CSCTRL_STR;

  #define TMRA_2_CSCTRL_CL10_MASK       0x01U
  #define TMRA_2_CSCTRL_CL11_MASK       0x02U
  #define TMRA_2_CSCTRL_CL20_MASK       0x04U
  #define TMRA_2_CSCTRL_CL21_MASK       0x08U
  #define TMRA_2_CSCTRL_TCF1_MASK       0x10U
  #define TMRA_2_CSCTRL_TCF2_MASK       0x20U
  #define TMRA_2_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRA_2_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRA_2_CSCTRL_UP_MASK         0x0200U
  #define TMRA_2_CSCTRL_TCI_MASK        0x0400U
  #define TMRA_2_CSCTRL_ROC_MASK        0x0800U
  #define TMRA_2_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRA_2_CSCTRL_FAULT_MASK      0x2000U
  #define TMRA_2_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRA_2_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRA_2_CSCTRL_CL1_MASK        0x03U
  #define TMRA_2_CSCTRL_CL1_BITNUM      0x00U
  #define TMRA_2_CSCTRL_CL2_MASK        0x0CU
  #define TMRA_2_CSCTRL_CL2_BITNUM      0x02U
  #define TMRA_2_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRA_2_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRA_2_CSCTRL                 (*((volatile word *)0x0000E16A))


  /*** TMRA_2_FILT - Timer Channel Input Filter Register; 0x0000E16B ***/
  union {
    word Word;
  } TMRA_2_FILT_STR;

  #define TMRA_2_FILT_FILT_PER0_MASK    0x01U
  #define TMRA_2_FILT_FILT_PER1_MASK    0x02U
  #define TMRA_2_FILT_FILT_PER2_MASK    0x04U
  #define TMRA_2_FILT_FILT_PER3_MASK    0x08U
  #define TMRA_2_FILT_FILT_PER4_MASK    0x10U
  #define TMRA_2_FILT_FILT_PER5_MASK    0x20U
  #define TMRA_2_FILT_FILT_PER6_MASK    0x40U
  #define TMRA_2_FILT_FILT_PER7_MASK    0x80U
  #define TMRA_2_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRA_2_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRA_2_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRA_2_FILT_FILT_PER_MASK     0xFFU
  #define TMRA_2_FILT_FILT_PER_BITNUM   0x00U
  #define TMRA_2_FILT_FILT_CNT_MASK     0x0700U
  #define TMRA_2_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRA_2_FILT                   (*((volatile word *)0x0000E16B))


  /*** TMRA_2_DMA - Timer Channel DMA Enable Register; 0x0000E16C ***/
  union {
    word Word;
  } TMRA_2_DMA_STR;

  #define TMRA_2_DMA_IEFDE_MASK         0x01U
  #define TMRA_2_DMA_CMPLD1DE_MASK      0x02U
  #define TMRA_2_DMA_CMPLD2DE_MASK      0x04U
  #define TMRA_2_DMA                    (*((volatile word *)0x0000E16C))


  word Reserved2[3];                   /* Reserved (unused) registers */

  /*** TMRA_3_COMP1 - Timer Channel Compare Register 1; 0x0000E170 ***/
  union {
    word Word;
  } TMRA_3_COMP1_STR;

  #define TMRA_3_COMP1                  (*((volatile word *)0x0000E170))


  /*** TMRA_3_COMP2 - Timer Channel Compare Register 2; 0x0000E171 ***/
  union {
    word Word;
  } TMRA_3_COMP2_STR;

  #define TMRA_3_COMP2                  (*((volatile word *)0x0000E171))


  /*** TMRA_3_CAPT - Timer Channel Capture Register; 0x0000E172 ***/
  union {
    word Word;
  } TMRA_3_CAPT_STR;

  #define TMRA_3_CAPT                   (*((volatile word *)0x0000E172))


  /*** TMRA_3_LOAD - Timer Channel Load Register; 0x0000E173 ***/
  union {
    word Word;
  } TMRA_3_LOAD_STR;

  #define TMRA_3_LOAD                   (*((volatile word *)0x0000E173))


  /*** TMRA_3_HOLD - Timer Channel Hold Register; 0x0000E174 ***/
  union {
    word Word;
  } TMRA_3_HOLD_STR;

  #define TMRA_3_HOLD                   (*((volatile word *)0x0000E174))


  /*** TMRA_3_CNTR - Timer Channel Counter Register; 0x0000E175 ***/
  union {
    word Word;
  } TMRA_3_CNTR_STR;

  #define TMRA_3_CNTR                   (*((volatile word *)0x0000E175))


  /*** TMRA_3_CTRL - Timer Channel Control Register; 0x0000E176 ***/
  union {
    word Word;
  } TMRA_3_CTRL_STR;

  #define TMRA_3_CTRL_OUTMODE0_MASK     0x01U
  #define TMRA_3_CTRL_OUTMODE1_MASK     0x02U
  #define TMRA_3_CTRL_OUTMODE2_MASK     0x04U
  #define TMRA_3_CTRL_COINIT_MASK       0x08U
  #define TMRA_3_CTRL_DIR_MASK          0x10U
  #define TMRA_3_CTRL_LENGTH_MASK       0x20U
  #define TMRA_3_CTRL_ONCE_MASK         0x40U
  #define TMRA_3_CTRL_SCS0_MASK         0x80U
  #define TMRA_3_CTRL_SCS1_MASK         0x0100U
  #define TMRA_3_CTRL_PCS0_MASK         0x0200U
  #define TMRA_3_CTRL_PCS1_MASK         0x0400U
  #define TMRA_3_CTRL_PCS2_MASK         0x0800U
  #define TMRA_3_CTRL_PCS3_MASK         0x1000U
  #define TMRA_3_CTRL_CM0_MASK          0x2000U
  #define TMRA_3_CTRL_CM1_MASK          0x4000U
  #define TMRA_3_CTRL_CM2_MASK          0x8000U
  #define TMRA_3_CTRL_OUTMODE_MASK      0x07U
  #define TMRA_3_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRA_3_CTRL_SCS_MASK          0x0180U
  #define TMRA_3_CTRL_SCS_BITNUM        0x07U
  #define TMRA_3_CTRL_PCS_MASK          0x1E00U
  #define TMRA_3_CTRL_PCS_BITNUM        0x09U
  #define TMRA_3_CTRL_CM_MASK           0xE000U
  #define TMRA_3_CTRL_CM_BITNUM         0x0DU
  #define TMRA_3_CTRL                   (*((volatile word *)0x0000E176))


  /*** TMRA_3_SCTRL - Timer Channel Status and Control Register; 0x0000E177 ***/
  union {
    word Word;
  } TMRA_3_SCTRL_STR;

  #define TMRA_3_SCTRL_OEN_MASK         0x01U
  #define TMRA_3_SCTRL_OPS_MASK         0x02U
  #define TMRA_3_SCTRL_FORCE_MASK       0x04U
  #define TMRA_3_SCTRL_VAL_MASK         0x08U
  #define TMRA_3_SCTRL_EEOF_MASK        0x10U
  #define TMRA_3_SCTRL_MSTR_MASK        0x20U
  #define TMRA_3_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRA_3_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRA_3_SCTRL_INPUT_MASK       0x0100U
  #define TMRA_3_SCTRL_IPS_MASK         0x0200U
  #define TMRA_3_SCTRL_IEFIE_MASK       0x0400U
  #define TMRA_3_SCTRL_IEF_MASK         0x0800U
  #define TMRA_3_SCTRL_TOFIE_MASK       0x1000U
  #define TMRA_3_SCTRL_TOF_MASK         0x2000U
  #define TMRA_3_SCTRL_TCFIE_MASK       0x4000U
  #define TMRA_3_SCTRL_TCF_MASK         0x8000U
  #define TMRA_3_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRA_3_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRA_3_SCTRL                  (*((volatile word *)0x0000E177))


  /*** TMRA_3_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E178 ***/
  union {
    word Word;
  } TMRA_3_CMPLD1_STR;

  #define TMRA_3_CMPLD1                 (*((volatile word *)0x0000E178))


  /*** TMRA_3_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E179 ***/
  union {
    word Word;
  } TMRA_3_CMPLD2_STR;

  #define TMRA_3_CMPLD2                 (*((volatile word *)0x0000E179))


  /*** TMRA_3_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E17A ***/
  union {
    word Word;
  } TMRA_3_CSCTRL_STR;

  #define TMRA_3_CSCTRL_CL10_MASK       0x01U
  #define TMRA_3_CSCTRL_CL11_MASK       0x02U
  #define TMRA_3_CSCTRL_CL20_MASK       0x04U
  #define TMRA_3_CSCTRL_CL21_MASK       0x08U
  #define TMRA_3_CSCTRL_TCF1_MASK       0x10U
  #define TMRA_3_CSCTRL_TCF2_MASK       0x20U
  #define TMRA_3_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRA_3_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRA_3_CSCTRL_UP_MASK         0x0200U
  #define TMRA_3_CSCTRL_TCI_MASK        0x0400U
  #define TMRA_3_CSCTRL_ROC_MASK        0x0800U
  #define TMRA_3_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRA_3_CSCTRL_FAULT_MASK      0x2000U
  #define TMRA_3_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRA_3_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRA_3_CSCTRL_CL1_MASK        0x03U
  #define TMRA_3_CSCTRL_CL1_BITNUM      0x00U
  #define TMRA_3_CSCTRL_CL2_MASK        0x0CU
  #define TMRA_3_CSCTRL_CL2_BITNUM      0x02U
  #define TMRA_3_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRA_3_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRA_3_CSCTRL                 (*((volatile word *)0x0000E17A))


  /*** TMRA_3_FILT - Timer Channel Input Filter Register; 0x0000E17B ***/
  union {
    word Word;
  } TMRA_3_FILT_STR;

  #define TMRA_3_FILT_FILT_PER0_MASK    0x01U
  #define TMRA_3_FILT_FILT_PER1_MASK    0x02U
  #define TMRA_3_FILT_FILT_PER2_MASK    0x04U
  #define TMRA_3_FILT_FILT_PER3_MASK    0x08U
  #define TMRA_3_FILT_FILT_PER4_MASK    0x10U
  #define TMRA_3_FILT_FILT_PER5_MASK    0x20U
  #define TMRA_3_FILT_FILT_PER6_MASK    0x40U
  #define TMRA_3_FILT_FILT_PER7_MASK    0x80U
  #define TMRA_3_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRA_3_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRA_3_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRA_3_FILT_FILT_PER_MASK     0xFFU
  #define TMRA_3_FILT_FILT_PER_BITNUM   0x00U
  #define TMRA_3_FILT_FILT_CNT_MASK     0x0700U
  #define TMRA_3_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRA_3_FILT                   (*((volatile word *)0x0000E17B))


  /*** TMRA_3_DMA - Timer Channel DMA Enable Register; 0x0000E17C ***/
  union {
    word Word;
  } TMRA_3_DMA_STR;

  #define TMRA_3_DMA_IEFDE_MASK         0x01U
  #define TMRA_3_DMA_CMPLD1DE_MASK      0x02U
  #define TMRA_3_DMA_CMPLD2DE_MASK      0x04U
  #define TMRA_3_DMA                    (*((volatile word *)0x0000E17C))


} TMRA_PRPH;
/******************************************
*** Peripheral TMRB
*******************************************/
typedef volatile struct {
  /*** TMRB_0_COMP1 - Timer Channel Compare Register 1; 0x0000E180 ***/
  union {
    word Word;
  } TMRB_0_COMP1_STR;

  #define TMRB_0_COMP1                  (*((volatile word *)0x0000E180))


  /*** TMRB_0_COMP2 - Timer Channel Compare Register 2; 0x0000E181 ***/
  union {
    word Word;
  } TMRB_0_COMP2_STR;

  #define TMRB_0_COMP2                  (*((volatile word *)0x0000E181))


  /*** TMRB_0_CAPT - Timer Channel Capture Register; 0x0000E182 ***/
  union {
    word Word;
  } TMRB_0_CAPT_STR;

  #define TMRB_0_CAPT                   (*((volatile word *)0x0000E182))


  /*** TMRB_0_LOAD - Timer Channel Load Register; 0x0000E183 ***/
  union {
    word Word;
  } TMRB_0_LOAD_STR;

  #define TMRB_0_LOAD                   (*((volatile word *)0x0000E183))


  /*** TMRB_0_HOLD - Timer Channel Hold Register; 0x0000E184 ***/
  union {
    word Word;
  } TMRB_0_HOLD_STR;

  #define TMRB_0_HOLD                   (*((volatile word *)0x0000E184))


  /*** TMRB_0_CNTR - Timer Channel Counter Register; 0x0000E185 ***/
  union {
    word Word;
  } TMRB_0_CNTR_STR;

  #define TMRB_0_CNTR                   (*((volatile word *)0x0000E185))


  /*** TMRB_0_CTRL - Timer Channel Control Register; 0x0000E186 ***/
  union {
    word Word;
  } TMRB_0_CTRL_STR;

  #define TMRB_0_CTRL_OUTMODE0_MASK     0x01U
  #define TMRB_0_CTRL_OUTMODE1_MASK     0x02U
  #define TMRB_0_CTRL_OUTMODE2_MASK     0x04U
  #define TMRB_0_CTRL_COINIT_MASK       0x08U
  #define TMRB_0_CTRL_DIR_MASK          0x10U
  #define TMRB_0_CTRL_LENGTH_MASK       0x20U
  #define TMRB_0_CTRL_ONCE_MASK         0x40U
  #define TMRB_0_CTRL_SCS0_MASK         0x80U
  #define TMRB_0_CTRL_SCS1_MASK         0x0100U
  #define TMRB_0_CTRL_PCS0_MASK         0x0200U
  #define TMRB_0_CTRL_PCS1_MASK         0x0400U
  #define TMRB_0_CTRL_PCS2_MASK         0x0800U
  #define TMRB_0_CTRL_PCS3_MASK         0x1000U
  #define TMRB_0_CTRL_CM0_MASK          0x2000U
  #define TMRB_0_CTRL_CM1_MASK          0x4000U
  #define TMRB_0_CTRL_CM2_MASK          0x8000U
  #define TMRB_0_CTRL_OUTMODE_MASK      0x07U
  #define TMRB_0_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRB_0_CTRL_SCS_MASK          0x0180U
  #define TMRB_0_CTRL_SCS_BITNUM        0x07U
  #define TMRB_0_CTRL_PCS_MASK          0x1E00U
  #define TMRB_0_CTRL_PCS_BITNUM        0x09U
  #define TMRB_0_CTRL_CM_MASK           0xE000U
  #define TMRB_0_CTRL_CM_BITNUM         0x0DU
  #define TMRB_0_CTRL                   (*((volatile word *)0x0000E186))


  /*** TMRB_0_SCTRL - Timer Channel Status and Control Register; 0x0000E187 ***/
  union {
    word Word;
  } TMRB_0_SCTRL_STR;

  #define TMRB_0_SCTRL_OEN_MASK         0x01U
  #define TMRB_0_SCTRL_OPS_MASK         0x02U
  #define TMRB_0_SCTRL_FORCE_MASK       0x04U
  #define TMRB_0_SCTRL_VAL_MASK         0x08U
  #define TMRB_0_SCTRL_EEOF_MASK        0x10U
  #define TMRB_0_SCTRL_MSTR_MASK        0x20U
  #define TMRB_0_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRB_0_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRB_0_SCTRL_INPUT_MASK       0x0100U
  #define TMRB_0_SCTRL_IPS_MASK         0x0200U
  #define TMRB_0_SCTRL_IEFIE_MASK       0x0400U
  #define TMRB_0_SCTRL_IEF_MASK         0x0800U
  #define TMRB_0_SCTRL_TOFIE_MASK       0x1000U
  #define TMRB_0_SCTRL_TOF_MASK         0x2000U
  #define TMRB_0_SCTRL_TCFIE_MASK       0x4000U
  #define TMRB_0_SCTRL_TCF_MASK         0x8000U
  #define TMRB_0_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRB_0_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRB_0_SCTRL                  (*((volatile word *)0x0000E187))


  /*** TMRB_0_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E188 ***/
  union {
    word Word;
  } TMRB_0_CMPLD1_STR;

  #define TMRB_0_CMPLD1                 (*((volatile word *)0x0000E188))


  /*** TMRB_0_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E189 ***/
  union {
    word Word;
  } TMRB_0_CMPLD2_STR;

  #define TMRB_0_CMPLD2                 (*((volatile word *)0x0000E189))


  /*** TMRB_0_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E18A ***/
  union {
    word Word;
  } TMRB_0_CSCTRL_STR;

  #define TMRB_0_CSCTRL_CL10_MASK       0x01U
  #define TMRB_0_CSCTRL_CL11_MASK       0x02U
  #define TMRB_0_CSCTRL_CL20_MASK       0x04U
  #define TMRB_0_CSCTRL_CL21_MASK       0x08U
  #define TMRB_0_CSCTRL_TCF1_MASK       0x10U
  #define TMRB_0_CSCTRL_TCF2_MASK       0x20U
  #define TMRB_0_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRB_0_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRB_0_CSCTRL_UP_MASK         0x0200U
  #define TMRB_0_CSCTRL_TCI_MASK        0x0400U
  #define TMRB_0_CSCTRL_ROC_MASK        0x0800U
  #define TMRB_0_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRB_0_CSCTRL_FAULT_MASK      0x2000U
  #define TMRB_0_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRB_0_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRB_0_CSCTRL_CL1_MASK        0x03U
  #define TMRB_0_CSCTRL_CL1_BITNUM      0x00U
  #define TMRB_0_CSCTRL_CL2_MASK        0x0CU
  #define TMRB_0_CSCTRL_CL2_BITNUM      0x02U
  #define TMRB_0_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRB_0_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRB_0_CSCTRL                 (*((volatile word *)0x0000E18A))


  /*** TMRB_0_FILT - Timer Channel Input Filter Register; 0x0000E18B ***/
  union {
    word Word;
  } TMRB_0_FILT_STR;

  #define TMRB_0_FILT_FILT_PER0_MASK    0x01U
  #define TMRB_0_FILT_FILT_PER1_MASK    0x02U
  #define TMRB_0_FILT_FILT_PER2_MASK    0x04U
  #define TMRB_0_FILT_FILT_PER3_MASK    0x08U
  #define TMRB_0_FILT_FILT_PER4_MASK    0x10U
  #define TMRB_0_FILT_FILT_PER5_MASK    0x20U
  #define TMRB_0_FILT_FILT_PER6_MASK    0x40U
  #define TMRB_0_FILT_FILT_PER7_MASK    0x80U
  #define TMRB_0_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRB_0_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRB_0_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRB_0_FILT_FILT_PER_MASK     0xFFU
  #define TMRB_0_FILT_FILT_PER_BITNUM   0x00U
  #define TMRB_0_FILT_FILT_CNT_MASK     0x0700U
  #define TMRB_0_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRB_0_FILT                   (*((volatile word *)0x0000E18B))


  /*** TMRB_0_DMA - Timer Channel DMA Enable Register; 0x0000E18C ***/
  union {
    word Word;
  } TMRB_0_DMA_STR;

  #define TMRB_0_DMA_IEFDE_MASK         0x01U
  #define TMRB_0_DMA_CMPLD1DE_MASK      0x02U
  #define TMRB_0_DMA_CMPLD2DE_MASK      0x04U
  #define TMRB_0_DMA                    (*((volatile word *)0x0000E18C))


  word Reserved0[2];                   /* Reserved (unused) registers */

  /*** TMRB_0_ENBL - Timer Channel Enable Register; 0x0000E18F ***/
  union {
    word Word;
  } TMRB_0_ENBL_STR;

  #define TMRB_0_ENBL_ENBL0_MASK        0x01U
  #define TMRB_0_ENBL_ENBL1_MASK        0x02U
  #define TMRB_0_ENBL_ENBL2_MASK        0x04U
  #define TMRB_0_ENBL_ENBL3_MASK        0x08U
  #define TMRB_0_ENBL_ENBL_MASK         0x0FU
  #define TMRB_0_ENBL_ENBL_BITNUM       0x00U
  #define TMRB_0_ENBL                   (*((volatile word *)0x0000E18F))


  /*** TMRB_1_COMP1 - Timer Channel Compare Register 1; 0x0000E190 ***/
  union {
    word Word;
  } TMRB_1_COMP1_STR;

  #define TMRB_1_COMP1                  (*((volatile word *)0x0000E190))


  /*** TMRB_1_COMP2 - Timer Channel Compare Register 2; 0x0000E191 ***/
  union {
    word Word;
  } TMRB_1_COMP2_STR;

  #define TMRB_1_COMP2                  (*((volatile word *)0x0000E191))


  /*** TMRB_1_CAPT - Timer Channel Capture Register; 0x0000E192 ***/
  union {
    word Word;
  } TMRB_1_CAPT_STR;

  #define TMRB_1_CAPT                   (*((volatile word *)0x0000E192))


  /*** TMRB_1_LOAD - Timer Channel Load Register; 0x0000E193 ***/
  union {
    word Word;
  } TMRB_1_LOAD_STR;

  #define TMRB_1_LOAD                   (*((volatile word *)0x0000E193))


  /*** TMRB_1_HOLD - Timer Channel Hold Register; 0x0000E194 ***/
  union {
    word Word;
  } TMRB_1_HOLD_STR;

  #define TMRB_1_HOLD                   (*((volatile word *)0x0000E194))


  /*** TMRB_1_CNTR - Timer Channel Counter Register; 0x0000E195 ***/
  union {
    word Word;
  } TMRB_1_CNTR_STR;

  #define TMRB_1_CNTR                   (*((volatile word *)0x0000E195))


  /*** TMRB_1_CTRL - Timer Channel Control Register; 0x0000E196 ***/
  union {
    word Word;
  } TMRB_1_CTRL_STR;

  #define TMRB_1_CTRL_OUTMODE0_MASK     0x01U
  #define TMRB_1_CTRL_OUTMODE1_MASK     0x02U
  #define TMRB_1_CTRL_OUTMODE2_MASK     0x04U
  #define TMRB_1_CTRL_COINIT_MASK       0x08U
  #define TMRB_1_CTRL_DIR_MASK          0x10U
  #define TMRB_1_CTRL_LENGTH_MASK       0x20U
  #define TMRB_1_CTRL_ONCE_MASK         0x40U
  #define TMRB_1_CTRL_SCS0_MASK         0x80U
  #define TMRB_1_CTRL_SCS1_MASK         0x0100U
  #define TMRB_1_CTRL_PCS0_MASK         0x0200U
  #define TMRB_1_CTRL_PCS1_MASK         0x0400U
  #define TMRB_1_CTRL_PCS2_MASK         0x0800U
  #define TMRB_1_CTRL_PCS3_MASK         0x1000U
  #define TMRB_1_CTRL_CM0_MASK          0x2000U
  #define TMRB_1_CTRL_CM1_MASK          0x4000U
  #define TMRB_1_CTRL_CM2_MASK          0x8000U
  #define TMRB_1_CTRL_OUTMODE_MASK      0x07U
  #define TMRB_1_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRB_1_CTRL_SCS_MASK          0x0180U
  #define TMRB_1_CTRL_SCS_BITNUM        0x07U
  #define TMRB_1_CTRL_PCS_MASK          0x1E00U
  #define TMRB_1_CTRL_PCS_BITNUM        0x09U
  #define TMRB_1_CTRL_CM_MASK           0xE000U
  #define TMRB_1_CTRL_CM_BITNUM         0x0DU
  #define TMRB_1_CTRL                   (*((volatile word *)0x0000E196))


  /*** TMRB_1_SCTRL - Timer Channel Status and Control Register; 0x0000E197 ***/
  union {
    word Word;
  } TMRB_1_SCTRL_STR;

  #define TMRB_1_SCTRL_OEN_MASK         0x01U
  #define TMRB_1_SCTRL_OPS_MASK         0x02U
  #define TMRB_1_SCTRL_FORCE_MASK       0x04U
  #define TMRB_1_SCTRL_VAL_MASK         0x08U
  #define TMRB_1_SCTRL_EEOF_MASK        0x10U
  #define TMRB_1_SCTRL_MSTR_MASK        0x20U
  #define TMRB_1_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRB_1_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRB_1_SCTRL_INPUT_MASK       0x0100U
  #define TMRB_1_SCTRL_IPS_MASK         0x0200U
  #define TMRB_1_SCTRL_IEFIE_MASK       0x0400U
  #define TMRB_1_SCTRL_IEF_MASK         0x0800U
  #define TMRB_1_SCTRL_TOFIE_MASK       0x1000U
  #define TMRB_1_SCTRL_TOF_MASK         0x2000U
  #define TMRB_1_SCTRL_TCFIE_MASK       0x4000U
  #define TMRB_1_SCTRL_TCF_MASK         0x8000U
  #define TMRB_1_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRB_1_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRB_1_SCTRL                  (*((volatile word *)0x0000E197))


  /*** TMRB_1_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E198 ***/
  union {
    word Word;
  } TMRB_1_CMPLD1_STR;

  #define TMRB_1_CMPLD1                 (*((volatile word *)0x0000E198))


  /*** TMRB_1_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E199 ***/
  union {
    word Word;
  } TMRB_1_CMPLD2_STR;

  #define TMRB_1_CMPLD2                 (*((volatile word *)0x0000E199))


  /*** TMRB_1_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E19A ***/
  union {
    word Word;
  } TMRB_1_CSCTRL_STR;

  #define TMRB_1_CSCTRL_CL10_MASK       0x01U
  #define TMRB_1_CSCTRL_CL11_MASK       0x02U
  #define TMRB_1_CSCTRL_CL20_MASK       0x04U
  #define TMRB_1_CSCTRL_CL21_MASK       0x08U
  #define TMRB_1_CSCTRL_TCF1_MASK       0x10U
  #define TMRB_1_CSCTRL_TCF2_MASK       0x20U
  #define TMRB_1_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRB_1_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRB_1_CSCTRL_UP_MASK         0x0200U
  #define TMRB_1_CSCTRL_TCI_MASK        0x0400U
  #define TMRB_1_CSCTRL_ROC_MASK        0x0800U
  #define TMRB_1_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRB_1_CSCTRL_FAULT_MASK      0x2000U
  #define TMRB_1_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRB_1_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRB_1_CSCTRL_CL1_MASK        0x03U
  #define TMRB_1_CSCTRL_CL1_BITNUM      0x00U
  #define TMRB_1_CSCTRL_CL2_MASK        0x0CU
  #define TMRB_1_CSCTRL_CL2_BITNUM      0x02U
  #define TMRB_1_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRB_1_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRB_1_CSCTRL                 (*((volatile word *)0x0000E19A))


  /*** TMRB_1_FILT - Timer Channel Input Filter Register; 0x0000E19B ***/
  union {
    word Word;
  } TMRB_1_FILT_STR;

  #define TMRB_1_FILT_FILT_PER0_MASK    0x01U
  #define TMRB_1_FILT_FILT_PER1_MASK    0x02U
  #define TMRB_1_FILT_FILT_PER2_MASK    0x04U
  #define TMRB_1_FILT_FILT_PER3_MASK    0x08U
  #define TMRB_1_FILT_FILT_PER4_MASK    0x10U
  #define TMRB_1_FILT_FILT_PER5_MASK    0x20U
  #define TMRB_1_FILT_FILT_PER6_MASK    0x40U
  #define TMRB_1_FILT_FILT_PER7_MASK    0x80U
  #define TMRB_1_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRB_1_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRB_1_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRB_1_FILT_FILT_PER_MASK     0xFFU
  #define TMRB_1_FILT_FILT_PER_BITNUM   0x00U
  #define TMRB_1_FILT_FILT_CNT_MASK     0x0700U
  #define TMRB_1_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRB_1_FILT                   (*((volatile word *)0x0000E19B))


  /*** TMRB_1_DMA - Timer Channel DMA Enable Register; 0x0000E19C ***/
  union {
    word Word;
  } TMRB_1_DMA_STR;

  #define TMRB_1_DMA_IEFDE_MASK         0x01U
  #define TMRB_1_DMA_CMPLD1DE_MASK      0x02U
  #define TMRB_1_DMA_CMPLD2DE_MASK      0x04U
  #define TMRB_1_DMA                    (*((volatile word *)0x0000E19C))


  word Reserved1[3];                   /* Reserved (unused) registers */

  /*** TMRB_2_COMP1 - Timer Channel Compare Register 1; 0x0000E1A0 ***/
  union {
    word Word;
  } TMRB_2_COMP1_STR;

  #define TMRB_2_COMP1                  (*((volatile word *)0x0000E1A0))


  /*** TMRB_2_COMP2 - Timer Channel Compare Register 2; 0x0000E1A1 ***/
  union {
    word Word;
  } TMRB_2_COMP2_STR;

  #define TMRB_2_COMP2                  (*((volatile word *)0x0000E1A1))


  /*** TMRB_2_CAPT - Timer Channel Capture Register; 0x0000E1A2 ***/
  union {
    word Word;
  } TMRB_2_CAPT_STR;

  #define TMRB_2_CAPT                   (*((volatile word *)0x0000E1A2))


  /*** TMRB_2_LOAD - Timer Channel Load Register; 0x0000E1A3 ***/
  union {
    word Word;
  } TMRB_2_LOAD_STR;

  #define TMRB_2_LOAD                   (*((volatile word *)0x0000E1A3))


  /*** TMRB_2_HOLD - Timer Channel Hold Register; 0x0000E1A4 ***/
  union {
    word Word;
  } TMRB_2_HOLD_STR;

  #define TMRB_2_HOLD                   (*((volatile word *)0x0000E1A4))


  /*** TMRB_2_CNTR - Timer Channel Counter Register; 0x0000E1A5 ***/
  union {
    word Word;
  } TMRB_2_CNTR_STR;

  #define TMRB_2_CNTR                   (*((volatile word *)0x0000E1A5))


  /*** TMRB_2_CTRL - Timer Channel Control Register; 0x0000E1A6 ***/
  union {
    word Word;
  } TMRB_2_CTRL_STR;

  #define TMRB_2_CTRL_OUTMODE0_MASK     0x01U
  #define TMRB_2_CTRL_OUTMODE1_MASK     0x02U
  #define TMRB_2_CTRL_OUTMODE2_MASK     0x04U
  #define TMRB_2_CTRL_COINIT_MASK       0x08U
  #define TMRB_2_CTRL_DIR_MASK          0x10U
  #define TMRB_2_CTRL_LENGTH_MASK       0x20U
  #define TMRB_2_CTRL_ONCE_MASK         0x40U
  #define TMRB_2_CTRL_SCS0_MASK         0x80U
  #define TMRB_2_CTRL_SCS1_MASK         0x0100U
  #define TMRB_2_CTRL_PCS0_MASK         0x0200U
  #define TMRB_2_CTRL_PCS1_MASK         0x0400U
  #define TMRB_2_CTRL_PCS2_MASK         0x0800U
  #define TMRB_2_CTRL_PCS3_MASK         0x1000U
  #define TMRB_2_CTRL_CM0_MASK          0x2000U
  #define TMRB_2_CTRL_CM1_MASK          0x4000U
  #define TMRB_2_CTRL_CM2_MASK          0x8000U
  #define TMRB_2_CTRL_OUTMODE_MASK      0x07U
  #define TMRB_2_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRB_2_CTRL_SCS_MASK          0x0180U
  #define TMRB_2_CTRL_SCS_BITNUM        0x07U
  #define TMRB_2_CTRL_PCS_MASK          0x1E00U
  #define TMRB_2_CTRL_PCS_BITNUM        0x09U
  #define TMRB_2_CTRL_CM_MASK           0xE000U
  #define TMRB_2_CTRL_CM_BITNUM         0x0DU
  #define TMRB_2_CTRL                   (*((volatile word *)0x0000E1A6))


  /*** TMRB_2_SCTRL - Timer Channel Status and Control Register; 0x0000E1A7 ***/
  union {
    word Word;
  } TMRB_2_SCTRL_STR;

  #define TMRB_2_SCTRL_OEN_MASK         0x01U
  #define TMRB_2_SCTRL_OPS_MASK         0x02U
  #define TMRB_2_SCTRL_FORCE_MASK       0x04U
  #define TMRB_2_SCTRL_VAL_MASK         0x08U
  #define TMRB_2_SCTRL_EEOF_MASK        0x10U
  #define TMRB_2_SCTRL_MSTR_MASK        0x20U
  #define TMRB_2_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRB_2_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRB_2_SCTRL_INPUT_MASK       0x0100U
  #define TMRB_2_SCTRL_IPS_MASK         0x0200U
  #define TMRB_2_SCTRL_IEFIE_MASK       0x0400U
  #define TMRB_2_SCTRL_IEF_MASK         0x0800U
  #define TMRB_2_SCTRL_TOFIE_MASK       0x1000U
  #define TMRB_2_SCTRL_TOF_MASK         0x2000U
  #define TMRB_2_SCTRL_TCFIE_MASK       0x4000U
  #define TMRB_2_SCTRL_TCF_MASK         0x8000U
  #define TMRB_2_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRB_2_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRB_2_SCTRL                  (*((volatile word *)0x0000E1A7))


  /*** TMRB_2_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E1A8 ***/
  union {
    word Word;
  } TMRB_2_CMPLD1_STR;

  #define TMRB_2_CMPLD1                 (*((volatile word *)0x0000E1A8))


  /*** TMRB_2_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E1A9 ***/
  union {
    word Word;
  } TMRB_2_CMPLD2_STR;

  #define TMRB_2_CMPLD2                 (*((volatile word *)0x0000E1A9))


  /*** TMRB_2_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E1AA ***/
  union {
    word Word;
  } TMRB_2_CSCTRL_STR;

  #define TMRB_2_CSCTRL_CL10_MASK       0x01U
  #define TMRB_2_CSCTRL_CL11_MASK       0x02U
  #define TMRB_2_CSCTRL_CL20_MASK       0x04U
  #define TMRB_2_CSCTRL_CL21_MASK       0x08U
  #define TMRB_2_CSCTRL_TCF1_MASK       0x10U
  #define TMRB_2_CSCTRL_TCF2_MASK       0x20U
  #define TMRB_2_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRB_2_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRB_2_CSCTRL_UP_MASK         0x0200U
  #define TMRB_2_CSCTRL_TCI_MASK        0x0400U
  #define TMRB_2_CSCTRL_ROC_MASK        0x0800U
  #define TMRB_2_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRB_2_CSCTRL_FAULT_MASK      0x2000U
  #define TMRB_2_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRB_2_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRB_2_CSCTRL_CL1_MASK        0x03U
  #define TMRB_2_CSCTRL_CL1_BITNUM      0x00U
  #define TMRB_2_CSCTRL_CL2_MASK        0x0CU
  #define TMRB_2_CSCTRL_CL2_BITNUM      0x02U
  #define TMRB_2_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRB_2_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRB_2_CSCTRL                 (*((volatile word *)0x0000E1AA))


  /*** TMRB_2_FILT - Timer Channel Input Filter Register; 0x0000E1AB ***/
  union {
    word Word;
  } TMRB_2_FILT_STR;

  #define TMRB_2_FILT_FILT_PER0_MASK    0x01U
  #define TMRB_2_FILT_FILT_PER1_MASK    0x02U
  #define TMRB_2_FILT_FILT_PER2_MASK    0x04U
  #define TMRB_2_FILT_FILT_PER3_MASK    0x08U
  #define TMRB_2_FILT_FILT_PER4_MASK    0x10U
  #define TMRB_2_FILT_FILT_PER5_MASK    0x20U
  #define TMRB_2_FILT_FILT_PER6_MASK    0x40U
  #define TMRB_2_FILT_FILT_PER7_MASK    0x80U
  #define TMRB_2_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRB_2_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRB_2_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRB_2_FILT_FILT_PER_MASK     0xFFU
  #define TMRB_2_FILT_FILT_PER_BITNUM   0x00U
  #define TMRB_2_FILT_FILT_CNT_MASK     0x0700U
  #define TMRB_2_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRB_2_FILT                   (*((volatile word *)0x0000E1AB))


  /*** TMRB_2_DMA - Timer Channel DMA Enable Register; 0x0000E1AC ***/
  union {
    word Word;
  } TMRB_2_DMA_STR;

  #define TMRB_2_DMA_IEFDE_MASK         0x01U
  #define TMRB_2_DMA_CMPLD1DE_MASK      0x02U
  #define TMRB_2_DMA_CMPLD2DE_MASK      0x04U
  #define TMRB_2_DMA                    (*((volatile word *)0x0000E1AC))


  word Reserved2[3];                   /* Reserved (unused) registers */

  /*** TMRB_3_COMP1 - Timer Channel Compare Register 1; 0x0000E1B0 ***/
  union {
    word Word;
  } TMRB_3_COMP1_STR;

  #define TMRB_3_COMP1                  (*((volatile word *)0x0000E1B0))


  /*** TMRB_3_COMP2 - Timer Channel Compare Register 2; 0x0000E1B1 ***/
  union {
    word Word;
  } TMRB_3_COMP2_STR;

  #define TMRB_3_COMP2                  (*((volatile word *)0x0000E1B1))


  /*** TMRB_3_CAPT - Timer Channel Capture Register; 0x0000E1B2 ***/
  union {
    word Word;
  } TMRB_3_CAPT_STR;

  #define TMRB_3_CAPT                   (*((volatile word *)0x0000E1B2))


  /*** TMRB_3_LOAD - Timer Channel Load Register; 0x0000E1B3 ***/
  union {
    word Word;
  } TMRB_3_LOAD_STR;

  #define TMRB_3_LOAD                   (*((volatile word *)0x0000E1B3))


  /*** TMRB_3_HOLD - Timer Channel Hold Register; 0x0000E1B4 ***/
  union {
    word Word;
  } TMRB_3_HOLD_STR;

  #define TMRB_3_HOLD                   (*((volatile word *)0x0000E1B4))


  /*** TMRB_3_CNTR - Timer Channel Counter Register; 0x0000E1B5 ***/
  union {
    word Word;
  } TMRB_3_CNTR_STR;

  #define TMRB_3_CNTR                   (*((volatile word *)0x0000E1B5))


  /*** TMRB_3_CTRL - Timer Channel Control Register; 0x0000E1B6 ***/
  union {
    word Word;
  } TMRB_3_CTRL_STR;

  #define TMRB_3_CTRL_OUTMODE0_MASK     0x01U
  #define TMRB_3_CTRL_OUTMODE1_MASK     0x02U
  #define TMRB_3_CTRL_OUTMODE2_MASK     0x04U
  #define TMRB_3_CTRL_COINIT_MASK       0x08U
  #define TMRB_3_CTRL_DIR_MASK          0x10U
  #define TMRB_3_CTRL_LENGTH_MASK       0x20U
  #define TMRB_3_CTRL_ONCE_MASK         0x40U
  #define TMRB_3_CTRL_SCS0_MASK         0x80U
  #define TMRB_3_CTRL_SCS1_MASK         0x0100U
  #define TMRB_3_CTRL_PCS0_MASK         0x0200U
  #define TMRB_3_CTRL_PCS1_MASK         0x0400U
  #define TMRB_3_CTRL_PCS2_MASK         0x0800U
  #define TMRB_3_CTRL_PCS3_MASK         0x1000U
  #define TMRB_3_CTRL_CM0_MASK          0x2000U
  #define TMRB_3_CTRL_CM1_MASK          0x4000U
  #define TMRB_3_CTRL_CM2_MASK          0x8000U
  #define TMRB_3_CTRL_OUTMODE_MASK      0x07U
  #define TMRB_3_CTRL_OUTMODE_BITNUM    0x00U
  #define TMRB_3_CTRL_SCS_MASK          0x0180U
  #define TMRB_3_CTRL_SCS_BITNUM        0x07U
  #define TMRB_3_CTRL_PCS_MASK          0x1E00U
  #define TMRB_3_CTRL_PCS_BITNUM        0x09U
  #define TMRB_3_CTRL_CM_MASK           0xE000U
  #define TMRB_3_CTRL_CM_BITNUM         0x0DU
  #define TMRB_3_CTRL                   (*((volatile word *)0x0000E1B6))


  /*** TMRB_3_SCTRL - Timer Channel Status and Control Register; 0x0000E1B7 ***/
  union {
    word Word;
  } TMRB_3_SCTRL_STR;

  #define TMRB_3_SCTRL_OEN_MASK         0x01U
  #define TMRB_3_SCTRL_OPS_MASK         0x02U
  #define TMRB_3_SCTRL_FORCE_MASK       0x04U
  #define TMRB_3_SCTRL_VAL_MASK         0x08U
  #define TMRB_3_SCTRL_EEOF_MASK        0x10U
  #define TMRB_3_SCTRL_MSTR_MASK        0x20U
  #define TMRB_3_SCTRL_CAPTURE_MODE0_MASK 0x40U
  #define TMRB_3_SCTRL_CAPTURE_MODE1_MASK 0x80U
  #define TMRB_3_SCTRL_INPUT_MASK       0x0100U
  #define TMRB_3_SCTRL_IPS_MASK         0x0200U
  #define TMRB_3_SCTRL_IEFIE_MASK       0x0400U
  #define TMRB_3_SCTRL_IEF_MASK         0x0800U
  #define TMRB_3_SCTRL_TOFIE_MASK       0x1000U
  #define TMRB_3_SCTRL_TOF_MASK         0x2000U
  #define TMRB_3_SCTRL_TCFIE_MASK       0x4000U
  #define TMRB_3_SCTRL_TCF_MASK         0x8000U
  #define TMRB_3_SCTRL_CAPTURE_MODE_MASK 0xC0U
  #define TMRB_3_SCTRL_CAPTURE_MODE_BITNUM 0x06U
  #define TMRB_3_SCTRL                  (*((volatile word *)0x0000E1B7))


  /*** TMRB_3_CMPLD1 - Timer Channel Comparator Load Register 1; 0x0000E1B8 ***/
  union {
    word Word;
  } TMRB_3_CMPLD1_STR;

  #define TMRB_3_CMPLD1                 (*((volatile word *)0x0000E1B8))


  /*** TMRB_3_CMPLD2 - Timer Channel Comparator Load Register 2; 0x0000E1B9 ***/
  union {
    word Word;
  } TMRB_3_CMPLD2_STR;

  #define TMRB_3_CMPLD2                 (*((volatile word *)0x0000E1B9))


  /*** TMRB_3_CSCTRL - Timer Channel Comparator Status and Control Register; 0x0000E1BA ***/
  union {
    word Word;
  } TMRB_3_CSCTRL_STR;

  #define TMRB_3_CSCTRL_CL10_MASK       0x01U
  #define TMRB_3_CSCTRL_CL11_MASK       0x02U
  #define TMRB_3_CSCTRL_CL20_MASK       0x04U
  #define TMRB_3_CSCTRL_CL21_MASK       0x08U
  #define TMRB_3_CSCTRL_TCF1_MASK       0x10U
  #define TMRB_3_CSCTRL_TCF2_MASK       0x20U
  #define TMRB_3_CSCTRL_TCF1EN_MASK     0x40U
  #define TMRB_3_CSCTRL_TCF2EN_MASK     0x80U
  #define TMRB_3_CSCTRL_UP_MASK         0x0200U
  #define TMRB_3_CSCTRL_TCI_MASK        0x0400U
  #define TMRB_3_CSCTRL_ROC_MASK        0x0800U
  #define TMRB_3_CSCTRL_ALT_LOAD_MASK   0x1000U
  #define TMRB_3_CSCTRL_FAULT_MASK      0x2000U
  #define TMRB_3_CSCTRL_DBG_EN0_MASK    0x4000U
  #define TMRB_3_CSCTRL_DBG_EN1_MASK    0x8000U
  #define TMRB_3_CSCTRL_CL1_MASK        0x03U
  #define TMRB_3_CSCTRL_CL1_BITNUM      0x00U
  #define TMRB_3_CSCTRL_CL2_MASK        0x0CU
  #define TMRB_3_CSCTRL_CL2_BITNUM      0x02U
  #define TMRB_3_CSCTRL_DBG_EN_MASK     0xC000U
  #define TMRB_3_CSCTRL_DBG_EN_BITNUM   0x0EU
  #define TMRB_3_CSCTRL                 (*((volatile word *)0x0000E1BA))


  /*** TMRB_3_FILT - Timer Channel Input Filter Register; 0x0000E1BB ***/
  union {
    word Word;
  } TMRB_3_FILT_STR;

  #define TMRB_3_FILT_FILT_PER0_MASK    0x01U
  #define TMRB_3_FILT_FILT_PER1_MASK    0x02U
  #define TMRB_3_FILT_FILT_PER2_MASK    0x04U
  #define TMRB_3_FILT_FILT_PER3_MASK    0x08U
  #define TMRB_3_FILT_FILT_PER4_MASK    0x10U
  #define TMRB_3_FILT_FILT_PER5_MASK    0x20U
  #define TMRB_3_FILT_FILT_PER6_MASK    0x40U
  #define TMRB_3_FILT_FILT_PER7_MASK    0x80U
  #define TMRB_3_FILT_FILT_CNT0_MASK    0x0100U
  #define TMRB_3_FILT_FILT_CNT1_MASK    0x0200U
  #define TMRB_3_FILT_FILT_CNT2_MASK    0x0400U
  #define TMRB_3_FILT_FILT_PER_MASK     0xFFU
  #define TMRB_3_FILT_FILT_PER_BITNUM   0x00U
  #define TMRB_3_FILT_FILT_CNT_MASK     0x0700U
  #define TMRB_3_FILT_FILT_CNT_BITNUM   0x08U
  #define TMRB_3_FILT                   (*((volatile word *)0x0000E1BB))


  /*** TMRB_3_DMA - Timer Channel DMA Enable Register; 0x0000E1BC ***/
  union {
    word Word;
  } TMRB_3_DMA_STR;

  #define TMRB_3_DMA_IEFDE_MASK         0x01U
  #define TMRB_3_DMA_CMPLD1DE_MASK      0x02U
  #define TMRB_3_DMA_CMPLD2DE_MASK      0x04U
  #define TMRB_3_DMA                    (*((volatile word *)0x0000E1BC))


} TMRB_PRPH;
/******************************************
*** Peripheral CRC
*******************************************/
typedef volatile struct {
  /*** CRC_CRC - CRC Data Register; 0x0000E1C0 ***/
  union {
    dword Dword;
  } CRC_CRC_STR;

  #define CRC_CRC_LL0_MASK              0x01UL
  #define CRC_CRC_LL1_MASK              0x02UL
  #define CRC_CRC_LL2_MASK              0x04UL
  #define CRC_CRC_LL3_MASK              0x08UL
  #define CRC_CRC_LL4_MASK              0x10UL
  #define CRC_CRC_LL5_MASK              0x20UL
  #define CRC_CRC_LL6_MASK              0x40UL
  #define CRC_CRC_LL7_MASK              0x80UL
  #define CRC_CRC_LU0_MASK              0x0100UL
  #define CRC_CRC_LU1_MASK              0x0200UL
  #define CRC_CRC_LU2_MASK              0x0400UL
  #define CRC_CRC_LU3_MASK              0x0800UL
  #define CRC_CRC_LU4_MASK              0x1000UL
  #define CRC_CRC_LU5_MASK              0x2000UL
  #define CRC_CRC_LU6_MASK              0x4000UL
  #define CRC_CRC_LU7_MASK              0x8000UL
  #define CRC_CRC_HL0_MASK              0x00010000UL
  #define CRC_CRC_HL1_MASK              0x00020000UL
  #define CRC_CRC_HL2_MASK              0x00040000UL
  #define CRC_CRC_HL3_MASK              0x00080000UL
  #define CRC_CRC_HL4_MASK              0x00100000UL
  #define CRC_CRC_HL5_MASK              0x00200000UL
  #define CRC_CRC_HL6_MASK              0x00400000UL
  #define CRC_CRC_HL7_MASK              0x00800000UL
  #define CRC_CRC_HU0_MASK              0x01000000UL
  #define CRC_CRC_HU1_MASK              0x02000000UL
  #define CRC_CRC_HU2_MASK              0x04000000UL
  #define CRC_CRC_HU3_MASK              0x08000000UL
  #define CRC_CRC_HU4_MASK              0x10000000UL
  #define CRC_CRC_HU5_MASK              0x20000000UL
  #define CRC_CRC_HU6_MASK              0x40000000UL
  #define CRC_CRC_HU7_MASK              0x80000000UL
  #define CRC_CRC_LL_MASK               0xFFUL
  #define CRC_CRC_LL_BITNUM             0x00U
  #define CRC_CRC_LU_MASK               0xFF00UL
  #define CRC_CRC_LU_BITNUM             0x08U
  #define CRC_CRC_HL_MASK               0x00FF0000UL
  #define CRC_CRC_HL_BITNUM             0x10U
  #define CRC_CRC_HU_MASK               0xFF000000UL
  #define CRC_CRC_HU_BITNUM             0x18U
  #define CRC_CRC                       (*((volatile dword *)0x0000E1C0))


  /*** CRC_GPOLY - CRC Polynomial Register; 0x0000E1C2 ***/
  union {
    dword Dword;
  } CRC_GPOLY_STR;

  #define CRC_GPOLY_LOW0_MASK           0x01UL
  #define CRC_GPOLY_LOW1_MASK           0x02UL
  #define CRC_GPOLY_LOW2_MASK           0x04UL
  #define CRC_GPOLY_LOW3_MASK           0x08UL
  #define CRC_GPOLY_LOW4_MASK           0x10UL
  #define CRC_GPOLY_LOW5_MASK           0x20UL
  #define CRC_GPOLY_LOW6_MASK           0x40UL
  #define CRC_GPOLY_LOW7_MASK           0x80UL
  #define CRC_GPOLY_LOW8_MASK           0x0100UL
  #define CRC_GPOLY_LOW9_MASK           0x0200UL
  #define CRC_GPOLY_LOW10_MASK          0x0400UL
  #define CRC_GPOLY_LOW11_MASK          0x0800UL
  #define CRC_GPOLY_LOW12_MASK          0x1000UL
  #define CRC_GPOLY_LOW13_MASK          0x2000UL
  #define CRC_GPOLY_LOW14_MASK          0x4000UL
  #define CRC_GPOLY_LOW15_MASK          0x8000UL
  #define CRC_GPOLY_HIGH0_MASK          0x00010000UL
  #define CRC_GPOLY_HIGH1_MASK          0x00020000UL
  #define CRC_GPOLY_HIGH2_MASK          0x00040000UL
  #define CRC_GPOLY_HIGH3_MASK          0x00080000UL
  #define CRC_GPOLY_HIGH4_MASK          0x00100000UL
  #define CRC_GPOLY_HIGH5_MASK          0x00200000UL
  #define CRC_GPOLY_HIGH6_MASK          0x00400000UL
  #define CRC_GPOLY_HIGH7_MASK          0x00800000UL
  #define CRC_GPOLY_HIGH8_MASK          0x01000000UL
  #define CRC_GPOLY_HIGH9_MASK          0x02000000UL
  #define CRC_GPOLY_HIGH10_MASK         0x04000000UL
  #define CRC_GPOLY_HIGH11_MASK         0x08000000UL
  #define CRC_GPOLY_HIGH12_MASK         0x10000000UL
  #define CRC_GPOLY_HIGH13_MASK         0x20000000UL
  #define CRC_GPOLY_HIGH14_MASK         0x40000000UL
  #define CRC_GPOLY_HIGH15_MASK         0x80000000UL
  #define CRC_GPOLY_LOW_MASK            0xFFFFUL
  #define CRC_GPOLY_LOW_BITNUM          0x00U
  #define CRC_GPOLY_HIGH_MASK           0xFFFF0000UL
  #define CRC_GPOLY_HIGH_BITNUM         0x10U
  #define CRC_GPOLY                     (*((volatile dword *)0x0000E1C2))


  /*** CRC_CTRL - CRC Control Register; 0x0000E1C4 ***/
  union {
    dword Dword;
  } CRC_CTRL_STR;

  #define CRC_CTRL_TCRC_MASK            0x01000000UL
  #define CRC_CTRL_WAS_MASK             0x02000000UL
  #define CRC_CTRL_FXOR_MASK            0x04000000UL
  #define CRC_CTRL_TOTR0_MASK           0x10000000UL
  #define CRC_CTRL_TOTR1_MASK           0x20000000UL
  #define CRC_CTRL_TOT0_MASK            0x40000000UL
  #define CRC_CTRL_TOT1_MASK            0x80000000UL
  #define CRC_CTRL_TOTR_MASK            0x30000000UL
  #define CRC_CTRL_TOTR_BITNUM          0x1CU
  #define CRC_CTRL_TOT_MASK             0xC0000000UL
  #define CRC_CTRL_TOT_BITNUM           0x1EU
  #define CRC_CTRL                      (*((volatile dword *)0x0000E1C4))


} CRC_PRPH;
/******************************************
*** Peripheral ENC
*******************************************/
typedef volatile struct {
  /*** ENC_CTRL - Control Register; 0x0000E1E0 ***/
  union {
    word Word;
  } ENC_CTRL_STR;

  #define ENC_CTRL_CMPIE_MASK           0x01U
  #define ENC_CTRL_CMPIRQ_MASK          0x02U
  #define ENC_CTRL_WDE_MASK             0x04U
  #define ENC_CTRL_DIE_MASK             0x08U
  #define ENC_CTRL_DIRQ_MASK            0x10U
  #define ENC_CTRL_XNE_MASK             0x20U
  #define ENC_CTRL_XIP_MASK             0x40U
  #define ENC_CTRL_XIE_MASK             0x80U
  #define ENC_CTRL_XIRQ_MASK            0x0100U
  #define ENC_CTRL_PH1_MASK             0x0200U
  #define ENC_CTRL_REV_MASK             0x0400U
  #define ENC_CTRL_SWIP_MASK            0x0800U
  #define ENC_CTRL_HNE_MASK             0x1000U
  #define ENC_CTRL_HIP_MASK             0x2000U
  #define ENC_CTRL_HIE_MASK             0x4000U
  #define ENC_CTRL_HIRQ_MASK            0x8000U
  #define ENC_CTRL                      (*((volatile word *)0x0000E1E0))


  /*** ENC_FILT - Input Filter Register; 0x0000E1E1 ***/
  union {
    word Word;
  } ENC_FILT_STR;

  #define ENC_FILT_FILT_PER0_MASK       0x01U
  #define ENC_FILT_FILT_PER1_MASK       0x02U
  #define ENC_FILT_FILT_PER2_MASK       0x04U
  #define ENC_FILT_FILT_PER3_MASK       0x08U
  #define ENC_FILT_FILT_PER4_MASK       0x10U
  #define ENC_FILT_FILT_PER5_MASK       0x20U
  #define ENC_FILT_FILT_PER6_MASK       0x40U
  #define ENC_FILT_FILT_PER7_MASK       0x80U
  #define ENC_FILT_FILT_CNT0_MASK       0x0100U
  #define ENC_FILT_FILT_CNT1_MASK       0x0200U
  #define ENC_FILT_FILT_CNT2_MASK       0x0400U
  #define ENC_FILT_FILT_PER_MASK        0xFFU
  #define ENC_FILT_FILT_PER_BITNUM      0x00U
  #define ENC_FILT_FILT_CNT_MASK        0x0700U
  #define ENC_FILT_FILT_CNT_BITNUM      0x08U
  #define ENC_FILT                      (*((volatile word *)0x0000E1E1))


  /*** ENC_WTR - Watchdog Timeout Register; 0x0000E1E2 ***/
  union {
    word Word;
  } ENC_WTR_STR;

  #define ENC_WTR                       (*((volatile word *)0x0000E1E2))


  /*** ENC_POSD - Position Difference Counter Register; 0x0000E1E3 ***/
  union {
    word Word;
  } ENC_POSD_STR;

  #define ENC_POSD                      (*((volatile word *)0x0000E1E3))


  /*** ENC_POSDH - Position Difference Hold Register; 0x0000E1E4 ***/
  union {
    word Word;
  } ENC_POSDH_STR;

  #define ENC_POSDH                     (*((volatile word *)0x0000E1E4))


  /*** ENC_REV - Revolution Counter Register; 0x0000E1E5 ***/
  union {
    word Word;
  } ENC_REV_STR;

  #define ENC_REV                       (*((volatile word *)0x0000E1E5))


  /*** ENC_REVH - Revolution Hold Register; 0x0000E1E6 ***/
  union {
    word Word;
  } ENC_REVH_STR;

  #define ENC_REVH                      (*((volatile word *)0x0000E1E6))


  /*** ENC_UPOS - Upper Position Counter Register; 0x0000E1E7 ***/
  union {
    word Word;
  } ENC_UPOS_STR;

  #define ENC_UPOS                      (*((volatile word *)0x0000E1E7))


  /*** ENC_LPOS - Lower Position Counter Register; 0x0000E1E8 ***/
  union {
    word Word;
  } ENC_LPOS_STR;

  #define ENC_LPOS                      (*((volatile word *)0x0000E1E8))


  /*** ENC_UPOSH - Upper Position Hold Register; 0x0000E1E9 ***/
  union {
    word Word;
  } ENC_UPOSH_STR;

  #define ENC_UPOSH                     (*((volatile word *)0x0000E1E9))


  /*** ENC_LPOSH - Lower Position Hold Register; 0x0000E1EA ***/
  union {
    word Word;
  } ENC_LPOSH_STR;

  #define ENC_LPOSH                     (*((volatile word *)0x0000E1EA))


  /*** ENC_UINIT - Upper Initialization Register; 0x0000E1EB ***/
  union {
    word Word;
  } ENC_UINIT_STR;

  #define ENC_UINIT                     (*((volatile word *)0x0000E1EB))


  /*** ENC_LINIT - Lower Initialization Register; 0x0000E1EC ***/
  union {
    word Word;
  } ENC_LINIT_STR;

  #define ENC_LINIT                     (*((volatile word *)0x0000E1EC))


  /*** ENC_IMR - Input Monitor Register; 0x0000E1ED ***/
  union {
    word Word;
  } ENC_IMR_STR;

  #define ENC_IMR_HOME_MASK             0x01U
  #define ENC_IMR_INDEX_MASK            0x02U
  #define ENC_IMR_PHB_MASK              0x04U
  #define ENC_IMR_PHA_MASK              0x08U
  #define ENC_IMR_FHOM_MASK             0x10U
  #define ENC_IMR_FIND_MASK             0x20U
  #define ENC_IMR_FPHB_MASK             0x40U
  #define ENC_IMR_FPHA_MASK             0x80U
  #define ENC_IMR                       (*((volatile word *)0x0000E1ED))


  /*** ENC_TST - Test Register; 0x0000E1EE ***/
  union {
    word Word;
  } ENC_TST_STR;

  #define ENC_TST_TEST_COUNT0_MASK      0x01U
  #define ENC_TST_TEST_COUNT1_MASK      0x02U
  #define ENC_TST_TEST_COUNT2_MASK      0x04U
  #define ENC_TST_TEST_COUNT3_MASK      0x08U
  #define ENC_TST_TEST_COUNT4_MASK      0x10U
  #define ENC_TST_TEST_COUNT5_MASK      0x20U
  #define ENC_TST_TEST_COUNT6_MASK      0x40U
  #define ENC_TST_TEST_COUNT7_MASK      0x80U
  #define ENC_TST_TEST_PERIOD0_MASK     0x0100U
  #define ENC_TST_TEST_PERIOD1_MASK     0x0200U
  #define ENC_TST_TEST_PERIOD2_MASK     0x0400U
  #define ENC_TST_TEST_PERIOD3_MASK     0x0800U
  #define ENC_TST_TEST_PERIOD4_MASK     0x1000U
  #define ENC_TST_QDN_MASK              0x2000U
  #define ENC_TST_TCE_MASK              0x4000U
  #define ENC_TST_TEN_MASK              0x8000U
  #define ENC_TST_TEST_COUNT_MASK       0xFFU
  #define ENC_TST_TEST_COUNT_BITNUM     0x00U
  #define ENC_TST_TEST_PERIOD_MASK      0x1F00U
  #define ENC_TST_TEST_PERIOD_BITNUM    0x08U
  #define ENC_TST                       (*((volatile word *)0x0000E1EE))


  /*** ENC_CTRL2 - Control 2 Register; 0x0000E1EF ***/
  union {
    word Word;
  } ENC_CTRL2_STR;

  #define ENC_CTRL2_UPDHLD_MASK         0x01U
  #define ENC_CTRL2_UPDPOS_MASK         0x02U
  #define ENC_CTRL2_MOD_MASK            0x04U
  #define ENC_CTRL2_DIR_MASK            0x08U
  #define ENC_CTRL2_RUIE_MASK           0x10U
  #define ENC_CTRL2_RUIRQ_MASK          0x20U
  #define ENC_CTRL2_ROIE_MASK           0x40U
  #define ENC_CTRL2_ROIRQ_MASK          0x80U
  #define ENC_CTRL2_REVMOD_MASK         0x0100U
  #define ENC_CTRL2_OUTCTL_MASK         0x0200U
  #define ENC_CTRL2                     (*((volatile word *)0x0000E1EF))


  /*** ENC_UMOD - Upper Modulus Register; 0x0000E1F0 ***/
  union {
    word Word;
  } ENC_UMOD_STR;

  #define ENC_UMOD                      (*((volatile word *)0x0000E1F0))


  /*** ENC_LMOD - Lower Modulus Register; 0x0000E1F1 ***/
  union {
    word Word;
  } ENC_LMOD_STR;

  #define ENC_LMOD                      (*((volatile word *)0x0000E1F1))


  /*** ENC_UCOMP - Upper Position Compare Register; 0x0000E1F2 ***/
  union {
    word Word;
  } ENC_UCOMP_STR;

  #define ENC_UCOMP                     (*((volatile word *)0x0000E1F2))


  /*** ENC_LCOMP - Lower Position Compare Register; 0x0000E1F3 ***/
  union {
    word Word;
  } ENC_LCOMP_STR;

  #define ENC_LCOMP                     (*((volatile word *)0x0000E1F3))


} ENC_PRPH;
/******************************************
*** Peripheral GPIOA
*******************************************/
typedef volatile struct {
  /*** GPIOA_PUR - GPIO Pull Resistor Enable Register; 0x0000E200 ***/
  union {
    word Word;
  } GPIOA_PUR_STR;

  #define GPIOA_PUR_PU0_MASK            0x01U
  #define GPIOA_PUR_PU1_MASK            0x02U
  #define GPIOA_PUR_PU2_MASK            0x04U
  #define GPIOA_PUR_PU3_MASK            0x08U
  #define GPIOA_PUR_PU4_MASK            0x10U
  #define GPIOA_PUR_PU5_MASK            0x20U
  #define GPIOA_PUR_PU6_MASK            0x40U
  #define GPIOA_PUR_PU7_MASK            0x80U
  #define GPIOA_PUR_PU8_MASK            0x0100U
  #define GPIOA_PUR_PU9_MASK            0x0200U
  #define GPIOA_PUR_PU10_MASK           0x0400U
  #define GPIOA_PUR_PU11_MASK           0x0800U
  #define GPIOA_PUR_PU12_MASK           0x1000U
  #define GPIOA_PUR_PU13_MASK           0x2000U
  #define GPIOA_PUR_PU14_MASK           0x4000U
  #define GPIOA_PUR_PU15_MASK           0x8000U
  #define GPIOA_PUR                     (*((volatile word *)0x0000E200))


  /*** GPIOA_DR - GPIO Data Register; 0x0000E201 ***/
  union {
    word Word;
  } GPIOA_DR_STR;

  #define GPIOA_DR_D0_MASK              0x01U
  #define GPIOA_DR_D1_MASK              0x02U
  #define GPIOA_DR_D2_MASK              0x04U
  #define GPIOA_DR_D3_MASK              0x08U
  #define GPIOA_DR_D4_MASK              0x10U
  #define GPIOA_DR_D5_MASK              0x20U
  #define GPIOA_DR_D6_MASK              0x40U
  #define GPIOA_DR_D7_MASK              0x80U
  #define GPIOA_DR_D8_MASK              0x0100U
  #define GPIOA_DR_D9_MASK              0x0200U
  #define GPIOA_DR_D10_MASK             0x0400U
  #define GPIOA_DR_D11_MASK             0x0800U
  #define GPIOA_DR_D12_MASK             0x1000U
  #define GPIOA_DR_D13_MASK             0x2000U
  #define GPIOA_DR_D14_MASK             0x4000U
  #define GPIOA_DR_D15_MASK             0x8000U
  #define GPIOA_DR                      (*((volatile word *)0x0000E201))


  /*** GPIOA_DDR - GPIO Data Direction Register; 0x0000E202 ***/
  union {
    word Word;
  } GPIOA_DDR_STR;

  #define GPIOA_DDR_DD0_MASK            0x01U
  #define GPIOA_DDR_DD1_MASK            0x02U
  #define GPIOA_DDR_DD2_MASK            0x04U
  #define GPIOA_DDR_DD3_MASK            0x08U
  #define GPIOA_DDR_DD4_MASK            0x10U
  #define GPIOA_DDR_DD5_MASK            0x20U
  #define GPIOA_DDR_DD6_MASK            0x40U
  #define GPIOA_DDR_DD7_MASK            0x80U
  #define GPIOA_DDR_DD8_MASK            0x0100U
  #define GPIOA_DDR_DD9_MASK            0x0200U
  #define GPIOA_DDR_DD10_MASK           0x0400U
  #define GPIOA_DDR_DD11_MASK           0x0800U
  #define GPIOA_DDR_DD12_MASK           0x1000U
  #define GPIOA_DDR_DD13_MASK           0x2000U
  #define GPIOA_DDR_DD14_MASK           0x4000U
  #define GPIOA_DDR_DD15_MASK           0x8000U
  #define GPIOA_DDR                     (*((volatile word *)0x0000E202))


  /*** GPIOA_PER - GPIO Peripheral Enable Register; 0x0000E203 ***/
  union {
    word Word;
  } GPIOA_PER_STR;

  #define GPIOA_PER_PE0_MASK            0x01U
  #define GPIOA_PER_PE1_MASK            0x02U
  #define GPIOA_PER_PE2_MASK            0x04U
  #define GPIOA_PER_PE3_MASK            0x08U
  #define GPIOA_PER_PE4_MASK            0x10U
  #define GPIOA_PER_PE5_MASK            0x20U
  #define GPIOA_PER_PE6_MASK            0x40U
  #define GPIOA_PER_PE7_MASK            0x80U
  #define GPIOA_PER_PE8_MASK            0x0100U
  #define GPIOA_PER_PE9_MASK            0x0200U
  #define GPIOA_PER_PE10_MASK           0x0400U
  #define GPIOA_PER_PE11_MASK           0x0800U
  #define GPIOA_PER_PE12_MASK           0x1000U
  #define GPIOA_PER_PE13_MASK           0x2000U
  #define GPIOA_PER_PE14_MASK           0x4000U
  #define GPIOA_PER_PE15_MASK           0x8000U
  #define GPIOA_PER                     (*((volatile word *)0x0000E203))


  /*** GPIOA_IAR - GPIO Interrupt Assert Register; 0x0000E204 ***/
  union {
    word Word;
  } GPIOA_IAR_STR;

  #define GPIOA_IAR_IA0_MASK            0x01U
  #define GPIOA_IAR_IA1_MASK            0x02U
  #define GPIOA_IAR_IA2_MASK            0x04U
  #define GPIOA_IAR_IA3_MASK            0x08U
  #define GPIOA_IAR_IA4_MASK            0x10U
  #define GPIOA_IAR_IA5_MASK            0x20U
  #define GPIOA_IAR_IA6_MASK            0x40U
  #define GPIOA_IAR_IA7_MASK            0x80U
  #define GPIOA_IAR_IA8_MASK            0x0100U
  #define GPIOA_IAR_IA9_MASK            0x0200U
  #define GPIOA_IAR_IA10_MASK           0x0400U
  #define GPIOA_IAR_IA11_MASK           0x0800U
  #define GPIOA_IAR_IA12_MASK           0x1000U
  #define GPIOA_IAR_IA13_MASK           0x2000U
  #define GPIOA_IAR_IA14_MASK           0x4000U
  #define GPIOA_IAR_IA15_MASK           0x8000U
  #define GPIOA_IAR                     (*((volatile word *)0x0000E204))


  /*** GPIOA_IENR - GPIO Interrupt Enable Register; 0x0000E205 ***/
  union {
    word Word;
  } GPIOA_IENR_STR;

  #define GPIOA_IENR_IEN0_MASK          0x01U
  #define GPIOA_IENR_IEN1_MASK          0x02U
  #define GPIOA_IENR_IEN2_MASK          0x04U
  #define GPIOA_IENR_IEN3_MASK          0x08U
  #define GPIOA_IENR_IEN4_MASK          0x10U
  #define GPIOA_IENR_IEN5_MASK          0x20U
  #define GPIOA_IENR_IEN6_MASK          0x40U
  #define GPIOA_IENR_IEN7_MASK          0x80U
  #define GPIOA_IENR_IEN8_MASK          0x0100U
  #define GPIOA_IENR_IEN9_MASK          0x0200U
  #define GPIOA_IENR_IEN10_MASK         0x0400U
  #define GPIOA_IENR_IEN11_MASK         0x0800U
  #define GPIOA_IENR_IEN12_MASK         0x1000U
  #define GPIOA_IENR_IEN13_MASK         0x2000U
  #define GPIOA_IENR_IEN14_MASK         0x4000U
  #define GPIOA_IENR_IEN15_MASK         0x8000U
  #define GPIOA_IENR                    (*((volatile word *)0x0000E205))


  /*** GPIOA_IPOLR - GPIO Interrupt Polarity Register; 0x0000E206 ***/
  union {
    word Word;
  } GPIOA_IPOLR_STR;

  #define GPIOA_IPOLR_IPOL0_MASK        0x01U
  #define GPIOA_IPOLR_IPOL1_MASK        0x02U
  #define GPIOA_IPOLR_IPOL2_MASK        0x04U
  #define GPIOA_IPOLR_IPOL3_MASK        0x08U
  #define GPIOA_IPOLR_IPOL4_MASK        0x10U
  #define GPIOA_IPOLR_IPOL5_MASK        0x20U
  #define GPIOA_IPOLR_IPOL6_MASK        0x40U
  #define GPIOA_IPOLR_IPOL7_MASK        0x80U
  #define GPIOA_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOA_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOA_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOA_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOA_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOA_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOA_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOA_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOA_IPOLR                   (*((volatile word *)0x0000E206))


  /*** GPIOA_IPR - GPIO Interrupt Pending Register; 0x0000E207 ***/
  union {
    word Word;
  } GPIOA_IPR_STR;

  #define GPIOA_IPR_IP0_MASK            0x01U
  #define GPIOA_IPR_IP1_MASK            0x02U
  #define GPIOA_IPR_IP2_MASK            0x04U
  #define GPIOA_IPR_IP3_MASK            0x08U
  #define GPIOA_IPR_IP4_MASK            0x10U
  #define GPIOA_IPR_IP5_MASK            0x20U
  #define GPIOA_IPR_IP6_MASK            0x40U
  #define GPIOA_IPR_IP7_MASK            0x80U
  #define GPIOA_IPR_IP8_MASK            0x0100U
  #define GPIOA_IPR_IP9_MASK            0x0200U
  #define GPIOA_IPR_IP10_MASK           0x0400U
  #define GPIOA_IPR_IP11_MASK           0x0800U
  #define GPIOA_IPR_IP12_MASK           0x1000U
  #define GPIOA_IPR_IP13_MASK           0x2000U
  #define GPIOA_IPR_IP14_MASK           0x4000U
  #define GPIOA_IPR_IP15_MASK           0x8000U
  #define GPIOA_IPR                     (*((volatile word *)0x0000E207))


  /*** GPIOA_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E208 ***/
  union {
    word Word;
  } GPIOA_IESR_STR;

  #define GPIOA_IESR_IES0_MASK          0x01U
  #define GPIOA_IESR_IES1_MASK          0x02U
  #define GPIOA_IESR_IES2_MASK          0x04U
  #define GPIOA_IESR_IES3_MASK          0x08U
  #define GPIOA_IESR_IES4_MASK          0x10U
  #define GPIOA_IESR_IES5_MASK          0x20U
  #define GPIOA_IESR_IES6_MASK          0x40U
  #define GPIOA_IESR_IES7_MASK          0x80U
  #define GPIOA_IESR_IES8_MASK          0x0100U
  #define GPIOA_IESR_IES9_MASK          0x0200U
  #define GPIOA_IESR_IES10_MASK         0x0400U
  #define GPIOA_IESR_IES11_MASK         0x0800U
  #define GPIOA_IESR_IES12_MASK         0x1000U
  #define GPIOA_IESR_IES13_MASK         0x2000U
  #define GPIOA_IESR_IES14_MASK         0x4000U
  #define GPIOA_IESR_IES15_MASK         0x8000U
  #define GPIOA_IESR                    (*((volatile word *)0x0000E208))


  /*** GPIOA_PPMODE - GPIO Push-Pull Mode Register; 0x0000E209 ***/
  union {
    word Word;
  } GPIOA_PPMODE_STR;

  #define GPIOA_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOA_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOA_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOA_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOA_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOA_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOA_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOA_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOA_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOA_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOA_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOA_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOA_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOA_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOA_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOA_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOA_PPMODE                  (*((volatile word *)0x0000E209))


  /*** GPIOA_RAWDATA - GPIO Raw Data Register; 0x0000E20A ***/
  union {
    word Word;
  } GPIOA_RAWDATA_STR;

  #define GPIOA_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOA_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOA_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOA_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOA_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOA_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOA_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOA_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOA_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOA_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOA_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOA_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOA_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOA_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOA_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOA_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOA_RAWDATA                 (*((volatile word *)0x0000E20A))


  /*** GPIOA_DRIVE - GPIO Drive Strength Control Register; 0x0000E20B ***/
  union {
    word Word;
  } GPIOA_DRIVE_STR;

  #define GPIOA_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOA_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOA_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOA_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOA_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOA_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOA_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOA_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOA_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOA_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOA_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOA_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOA_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOA_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOA_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOA_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOA_DRIVE                   (*((volatile word *)0x0000E20B))


  /*** GPIOA_PUS - GPIO Pull Resistor Type Select; 0x0000E20C ***/
  union {
    word Word;
  } GPIOA_PUS_STR;

  #define GPIOA_PUS_PUS0_MASK           0x01U
  #define GPIOA_PUS_PUS1_MASK           0x02U
  #define GPIOA_PUS_PUS2_MASK           0x04U
  #define GPIOA_PUS_PUS3_MASK           0x08U
  #define GPIOA_PUS_PUS4_MASK           0x10U
  #define GPIOA_PUS_PUS5_MASK           0x20U
  #define GPIOA_PUS_PUS6_MASK           0x40U
  #define GPIOA_PUS_PUS7_MASK           0x80U
  #define GPIOA_PUS_PUS8_MASK           0x0100U
  #define GPIOA_PUS_PUS9_MASK           0x0200U
  #define GPIOA_PUS_PUS10_MASK          0x0400U
  #define GPIOA_PUS_PUS11_MASK          0x0800U
  #define GPIOA_PUS_PUS12_MASK          0x1000U
  #define GPIOA_PUS_PUS13_MASK          0x2000U
  #define GPIOA_PUS_PUS14_MASK          0x4000U
  #define GPIOA_PUS_PUS15_MASK          0x8000U
  #define GPIOA_PUS                     (*((volatile word *)0x0000E20C))


  /*** GPIOA_SRE - Slew Rate Control Register; 0x0000E20D ***/
  union {
    word Word;
  } GPIOA_SRE_STR;

  #define GPIOA_SRE_SRE0_MASK           0x01U
  #define GPIOA_SRE_SRE1_MASK           0x02U
  #define GPIOA_SRE_SRE2_MASK           0x04U
  #define GPIOA_SRE_SRE3_MASK           0x08U
  #define GPIOA_SRE_SRE4_MASK           0x10U
  #define GPIOA_SRE_SRE5_MASK           0x20U
  #define GPIOA_SRE_SRE6_MASK           0x40U
  #define GPIOA_SRE_SRE7_MASK           0x80U
  #define GPIOA_SRE_SRE8_MASK           0x0100U
  #define GPIOA_SRE_SRE9_MASK           0x0200U
  #define GPIOA_SRE_SRE10_MASK          0x0400U
  #define GPIOA_SRE_SRE11_MASK          0x0800U
  #define GPIOA_SRE_SRE12_MASK          0x1000U
  #define GPIOA_SRE_SRE13_MASK          0x2000U
  #define GPIOA_SRE_SRE14_MASK          0x4000U
  #define GPIOA_SRE_SRE15_MASK          0x8000U
  #define GPIOA_SRE                     (*((volatile word *)0x0000E20D))


} GPIOA_PRPH;
/******************************************
*** Peripheral GPIOB
*******************************************/
typedef volatile struct {
  /*** GPIOB_PUR - GPIO Pull Resistor Enable Register; 0x0000E210 ***/
  union {
    word Word;
  } GPIOB_PUR_STR;

  #define GPIOB_PUR_PU0_MASK            0x01U
  #define GPIOB_PUR_PU1_MASK            0x02U
  #define GPIOB_PUR_PU2_MASK            0x04U
  #define GPIOB_PUR_PU3_MASK            0x08U
  #define GPIOB_PUR_PU4_MASK            0x10U
  #define GPIOB_PUR_PU5_MASK            0x20U
  #define GPIOB_PUR_PU6_MASK            0x40U
  #define GPIOB_PUR_PU7_MASK            0x80U
  #define GPIOB_PUR_PU8_MASK            0x0100U
  #define GPIOB_PUR_PU9_MASK            0x0200U
  #define GPIOB_PUR_PU10_MASK           0x0400U
  #define GPIOB_PUR_PU11_MASK           0x0800U
  #define GPIOB_PUR_PU12_MASK           0x1000U
  #define GPIOB_PUR_PU13_MASK           0x2000U
  #define GPIOB_PUR_PU14_MASK           0x4000U
  #define GPIOB_PUR_PU15_MASK           0x8000U
  #define GPIOB_PUR                     (*((volatile word *)0x0000E210))


  /*** GPIOB_DR - GPIO Data Register; 0x0000E211 ***/
  union {
    word Word;
  } GPIOB_DR_STR;

  #define GPIOB_DR_D0_MASK              0x01U
  #define GPIOB_DR_D1_MASK              0x02U
  #define GPIOB_DR_D2_MASK              0x04U
  #define GPIOB_DR_D3_MASK              0x08U
  #define GPIOB_DR_D4_MASK              0x10U
  #define GPIOB_DR_D5_MASK              0x20U
  #define GPIOB_DR_D6_MASK              0x40U
  #define GPIOB_DR_D7_MASK              0x80U
  #define GPIOB_DR_D8_MASK              0x0100U
  #define GPIOB_DR_D9_MASK              0x0200U
  #define GPIOB_DR_D10_MASK             0x0400U
  #define GPIOB_DR_D11_MASK             0x0800U
  #define GPIOB_DR_D12_MASK             0x1000U
  #define GPIOB_DR_D13_MASK             0x2000U
  #define GPIOB_DR_D14_MASK             0x4000U
  #define GPIOB_DR_D15_MASK             0x8000U
  #define GPIOB_DR                      (*((volatile word *)0x0000E211))


  /*** GPIOB_DDR - GPIO Data Direction Register; 0x0000E212 ***/
  union {
    word Word;
  } GPIOB_DDR_STR;

  #define GPIOB_DDR_DD0_MASK            0x01U
  #define GPIOB_DDR_DD1_MASK            0x02U
  #define GPIOB_DDR_DD2_MASK            0x04U
  #define GPIOB_DDR_DD3_MASK            0x08U
  #define GPIOB_DDR_DD4_MASK            0x10U
  #define GPIOB_DDR_DD5_MASK            0x20U
  #define GPIOB_DDR_DD6_MASK            0x40U
  #define GPIOB_DDR_DD7_MASK            0x80U
  #define GPIOB_DDR_DD8_MASK            0x0100U
  #define GPIOB_DDR_DD9_MASK            0x0200U
  #define GPIOB_DDR_DD10_MASK           0x0400U
  #define GPIOB_DDR_DD11_MASK           0x0800U
  #define GPIOB_DDR_DD12_MASK           0x1000U
  #define GPIOB_DDR_DD13_MASK           0x2000U
  #define GPIOB_DDR_DD14_MASK           0x4000U
  #define GPIOB_DDR_DD15_MASK           0x8000U
  #define GPIOB_DDR                     (*((volatile word *)0x0000E212))


  /*** GPIOB_PER - GPIO Peripheral Enable Register; 0x0000E213 ***/
  union {
    word Word;
  } GPIOB_PER_STR;

  #define GPIOB_PER_PE0_MASK            0x01U
  #define GPIOB_PER_PE1_MASK            0x02U
  #define GPIOB_PER_PE2_MASK            0x04U
  #define GPIOB_PER_PE3_MASK            0x08U
  #define GPIOB_PER_PE4_MASK            0x10U
  #define GPIOB_PER_PE5_MASK            0x20U
  #define GPIOB_PER_PE6_MASK            0x40U
  #define GPIOB_PER_PE7_MASK            0x80U
  #define GPIOB_PER_PE8_MASK            0x0100U
  #define GPIOB_PER_PE9_MASK            0x0200U
  #define GPIOB_PER_PE10_MASK           0x0400U
  #define GPIOB_PER_PE11_MASK           0x0800U
  #define GPIOB_PER_PE12_MASK           0x1000U
  #define GPIOB_PER_PE13_MASK           0x2000U
  #define GPIOB_PER_PE14_MASK           0x4000U
  #define GPIOB_PER_PE15_MASK           0x8000U
  #define GPIOB_PER                     (*((volatile word *)0x0000E213))


  /*** GPIOB_IAR - GPIO Interrupt Assert Register; 0x0000E214 ***/
  union {
    word Word;
  } GPIOB_IAR_STR;

  #define GPIOB_IAR_IA0_MASK            0x01U
  #define GPIOB_IAR_IA1_MASK            0x02U
  #define GPIOB_IAR_IA2_MASK            0x04U
  #define GPIOB_IAR_IA3_MASK            0x08U
  #define GPIOB_IAR_IA4_MASK            0x10U
  #define GPIOB_IAR_IA5_MASK            0x20U
  #define GPIOB_IAR_IA6_MASK            0x40U
  #define GPIOB_IAR_IA7_MASK            0x80U
  #define GPIOB_IAR_IA8_MASK            0x0100U
  #define GPIOB_IAR_IA9_MASK            0x0200U
  #define GPIOB_IAR_IA10_MASK           0x0400U
  #define GPIOB_IAR_IA11_MASK           0x0800U
  #define GPIOB_IAR_IA12_MASK           0x1000U
  #define GPIOB_IAR_IA13_MASK           0x2000U
  #define GPIOB_IAR_IA14_MASK           0x4000U
  #define GPIOB_IAR_IA15_MASK           0x8000U
  #define GPIOB_IAR                     (*((volatile word *)0x0000E214))


  /*** GPIOB_IENR - GPIO Interrupt Enable Register; 0x0000E215 ***/
  union {
    word Word;
  } GPIOB_IENR_STR;

  #define GPIOB_IENR_IEN0_MASK          0x01U
  #define GPIOB_IENR_IEN1_MASK          0x02U
  #define GPIOB_IENR_IEN2_MASK          0x04U
  #define GPIOB_IENR_IEN3_MASK          0x08U
  #define GPIOB_IENR_IEN4_MASK          0x10U
  #define GPIOB_IENR_IEN5_MASK          0x20U
  #define GPIOB_IENR_IEN6_MASK          0x40U
  #define GPIOB_IENR_IEN7_MASK          0x80U
  #define GPIOB_IENR_IEN8_MASK          0x0100U
  #define GPIOB_IENR_IEN9_MASK          0x0200U
  #define GPIOB_IENR_IEN10_MASK         0x0400U
  #define GPIOB_IENR_IEN11_MASK         0x0800U
  #define GPIOB_IENR_IEN12_MASK         0x1000U
  #define GPIOB_IENR_IEN13_MASK         0x2000U
  #define GPIOB_IENR_IEN14_MASK         0x4000U
  #define GPIOB_IENR_IEN15_MASK         0x8000U
  #define GPIOB_IENR                    (*((volatile word *)0x0000E215))


  /*** GPIOB_IPOLR - GPIO Interrupt Polarity Register; 0x0000E216 ***/
  union {
    word Word;
  } GPIOB_IPOLR_STR;

  #define GPIOB_IPOLR_IPOL0_MASK        0x01U
  #define GPIOB_IPOLR_IPOL1_MASK        0x02U
  #define GPIOB_IPOLR_IPOL2_MASK        0x04U
  #define GPIOB_IPOLR_IPOL3_MASK        0x08U
  #define GPIOB_IPOLR_IPOL4_MASK        0x10U
  #define GPIOB_IPOLR_IPOL5_MASK        0x20U
  #define GPIOB_IPOLR_IPOL6_MASK        0x40U
  #define GPIOB_IPOLR_IPOL7_MASK        0x80U
  #define GPIOB_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOB_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOB_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOB_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOB_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOB_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOB_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOB_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOB_IPOLR                   (*((volatile word *)0x0000E216))


  /*** GPIOB_IPR - GPIO Interrupt Pending Register; 0x0000E217 ***/
  union {
    word Word;
  } GPIOB_IPR_STR;

  #define GPIOB_IPR_IP0_MASK            0x01U
  #define GPIOB_IPR_IP1_MASK            0x02U
  #define GPIOB_IPR_IP2_MASK            0x04U
  #define GPIOB_IPR_IP3_MASK            0x08U
  #define GPIOB_IPR_IP4_MASK            0x10U
  #define GPIOB_IPR_IP5_MASK            0x20U
  #define GPIOB_IPR_IP6_MASK            0x40U
  #define GPIOB_IPR_IP7_MASK            0x80U
  #define GPIOB_IPR_IP8_MASK            0x0100U
  #define GPIOB_IPR_IP9_MASK            0x0200U
  #define GPIOB_IPR_IP10_MASK           0x0400U
  #define GPIOB_IPR_IP11_MASK           0x0800U
  #define GPIOB_IPR_IP12_MASK           0x1000U
  #define GPIOB_IPR_IP13_MASK           0x2000U
  #define GPIOB_IPR_IP14_MASK           0x4000U
  #define GPIOB_IPR_IP15_MASK           0x8000U
  #define GPIOB_IPR                     (*((volatile word *)0x0000E217))


  /*** GPIOB_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E218 ***/
  union {
    word Word;
  } GPIOB_IESR_STR;

  #define GPIOB_IESR_IES0_MASK          0x01U
  #define GPIOB_IESR_IES1_MASK          0x02U
  #define GPIOB_IESR_IES2_MASK          0x04U
  #define GPIOB_IESR_IES3_MASK          0x08U
  #define GPIOB_IESR_IES4_MASK          0x10U
  #define GPIOB_IESR_IES5_MASK          0x20U
  #define GPIOB_IESR_IES6_MASK          0x40U
  #define GPIOB_IESR_IES7_MASK          0x80U
  #define GPIOB_IESR_IES8_MASK          0x0100U
  #define GPIOB_IESR_IES9_MASK          0x0200U
  #define GPIOB_IESR_IES10_MASK         0x0400U
  #define GPIOB_IESR_IES11_MASK         0x0800U
  #define GPIOB_IESR_IES12_MASK         0x1000U
  #define GPIOB_IESR_IES13_MASK         0x2000U
  #define GPIOB_IESR_IES14_MASK         0x4000U
  #define GPIOB_IESR_IES15_MASK         0x8000U
  #define GPIOB_IESR                    (*((volatile word *)0x0000E218))


  /*** GPIOB_PPMODE - GPIO Push-Pull Mode Register; 0x0000E219 ***/
  union {
    word Word;
  } GPIOB_PPMODE_STR;

  #define GPIOB_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOB_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOB_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOB_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOB_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOB_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOB_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOB_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOB_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOB_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOB_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOB_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOB_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOB_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOB_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOB_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOB_PPMODE                  (*((volatile word *)0x0000E219))


  /*** GPIOB_RAWDATA - GPIO Raw Data Register; 0x0000E21A ***/
  union {
    word Word;
  } GPIOB_RAWDATA_STR;

  #define GPIOB_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOB_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOB_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOB_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOB_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOB_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOB_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOB_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOB_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOB_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOB_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOB_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOB_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOB_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOB_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOB_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOB_RAWDATA                 (*((volatile word *)0x0000E21A))


  /*** GPIOB_DRIVE - GPIO Drive Strength Control Register; 0x0000E21B ***/
  union {
    word Word;
  } GPIOB_DRIVE_STR;

  #define GPIOB_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOB_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOB_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOB_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOB_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOB_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOB_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOB_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOB_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOB_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOB_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOB_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOB_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOB_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOB_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOB_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOB_DRIVE                   (*((volatile word *)0x0000E21B))


  /*** GPIOB_PUS - GPIO Pull Resistor Type Select; 0x0000E21C ***/
  union {
    word Word;
  } GPIOB_PUS_STR;

  #define GPIOB_PUS_PUS0_MASK           0x01U
  #define GPIOB_PUS_PUS1_MASK           0x02U
  #define GPIOB_PUS_PUS2_MASK           0x04U
  #define GPIOB_PUS_PUS3_MASK           0x08U
  #define GPIOB_PUS_PUS4_MASK           0x10U
  #define GPIOB_PUS_PUS5_MASK           0x20U
  #define GPIOB_PUS_PUS6_MASK           0x40U
  #define GPIOB_PUS_PUS7_MASK           0x80U
  #define GPIOB_PUS_PUS8_MASK           0x0100U
  #define GPIOB_PUS_PUS9_MASK           0x0200U
  #define GPIOB_PUS_PUS10_MASK          0x0400U
  #define GPIOB_PUS_PUS11_MASK          0x0800U
  #define GPIOB_PUS_PUS12_MASK          0x1000U
  #define GPIOB_PUS_PUS13_MASK          0x2000U
  #define GPIOB_PUS_PUS14_MASK          0x4000U
  #define GPIOB_PUS_PUS15_MASK          0x8000U
  #define GPIOB_PUS                     (*((volatile word *)0x0000E21C))


  /*** GPIOB_SRE - Slew Rate Control Register; 0x0000E21D ***/
  union {
    word Word;
  } GPIOB_SRE_STR;

  #define GPIOB_SRE_SRE0_MASK           0x01U
  #define GPIOB_SRE_SRE1_MASK           0x02U
  #define GPIOB_SRE_SRE2_MASK           0x04U
  #define GPIOB_SRE_SRE3_MASK           0x08U
  #define GPIOB_SRE_SRE4_MASK           0x10U
  #define GPIOB_SRE_SRE5_MASK           0x20U
  #define GPIOB_SRE_SRE6_MASK           0x40U
  #define GPIOB_SRE_SRE7_MASK           0x80U
  #define GPIOB_SRE_SRE8_MASK           0x0100U
  #define GPIOB_SRE_SRE9_MASK           0x0200U
  #define GPIOB_SRE_SRE10_MASK          0x0400U
  #define GPIOB_SRE_SRE11_MASK          0x0800U
  #define GPIOB_SRE_SRE12_MASK          0x1000U
  #define GPIOB_SRE_SRE13_MASK          0x2000U
  #define GPIOB_SRE_SRE14_MASK          0x4000U
  #define GPIOB_SRE_SRE15_MASK          0x8000U
  #define GPIOB_SRE                     (*((volatile word *)0x0000E21D))


} GPIOB_PRPH;
/******************************************
*** Peripheral GPIOC
*******************************************/
typedef volatile struct {
  /*** GPIOC_PUR - GPIO Pull Resistor Enable Register; 0x0000E220 ***/
  union {
    word Word;
  } GPIOC_PUR_STR;

  #define GPIOC_PUR_PU0_MASK            0x01U
  #define GPIOC_PUR_PU1_MASK            0x02U
  #define GPIOC_PUR_PU2_MASK            0x04U
  #define GPIOC_PUR_PU3_MASK            0x08U
  #define GPIOC_PUR_PU4_MASK            0x10U
  #define GPIOC_PUR_PU5_MASK            0x20U
  #define GPIOC_PUR_PU6_MASK            0x40U
  #define GPIOC_PUR_PU7_MASK            0x80U
  #define GPIOC_PUR_PU8_MASK            0x0100U
  #define GPIOC_PUR_PU9_MASK            0x0200U
  #define GPIOC_PUR_PU10_MASK           0x0400U
  #define GPIOC_PUR_PU11_MASK           0x0800U
  #define GPIOC_PUR_PU12_MASK           0x1000U
  #define GPIOC_PUR_PU13_MASK           0x2000U
  #define GPIOC_PUR_PU14_MASK           0x4000U
  #define GPIOC_PUR_PU15_MASK           0x8000U
  #define GPIOC_PUR                     (*((volatile word *)0x0000E220))


  /*** GPIOC_DR - GPIO Data Register; 0x0000E221 ***/
  union {
    word Word;
  } GPIOC_DR_STR;

  #define GPIOC_DR_D0_MASK              0x01U
  #define GPIOC_DR_D1_MASK              0x02U
  #define GPIOC_DR_D2_MASK              0x04U
  #define GPIOC_DR_D3_MASK              0x08U
  #define GPIOC_DR_D4_MASK              0x10U
  #define GPIOC_DR_D5_MASK              0x20U
  #define GPIOC_DR_D6_MASK              0x40U
  #define GPIOC_DR_D7_MASK              0x80U
  #define GPIOC_DR_D8_MASK              0x0100U
  #define GPIOC_DR_D9_MASK              0x0200U
  #define GPIOC_DR_D10_MASK             0x0400U
  #define GPIOC_DR_D11_MASK             0x0800U
  #define GPIOC_DR_D12_MASK             0x1000U
  #define GPIOC_DR_D13_MASK             0x2000U
  #define GPIOC_DR_D14_MASK             0x4000U
  #define GPIOC_DR_D15_MASK             0x8000U
  #define GPIOC_DR                      (*((volatile word *)0x0000E221))


  /*** GPIOC_DDR - GPIO Data Direction Register; 0x0000E222 ***/
  union {
    word Word;
  } GPIOC_DDR_STR;

  #define GPIOC_DDR_DD0_MASK            0x01U
  #define GPIOC_DDR_DD1_MASK            0x02U
  #define GPIOC_DDR_DD2_MASK            0x04U
  #define GPIOC_DDR_DD3_MASK            0x08U
  #define GPIOC_DDR_DD4_MASK            0x10U
  #define GPIOC_DDR_DD5_MASK            0x20U
  #define GPIOC_DDR_DD6_MASK            0x40U
  #define GPIOC_DDR_DD7_MASK            0x80U
  #define GPIOC_DDR_DD8_MASK            0x0100U
  #define GPIOC_DDR_DD9_MASK            0x0200U
  #define GPIOC_DDR_DD10_MASK           0x0400U
  #define GPIOC_DDR_DD11_MASK           0x0800U
  #define GPIOC_DDR_DD12_MASK           0x1000U
  #define GPIOC_DDR_DD13_MASK           0x2000U
  #define GPIOC_DDR_DD14_MASK           0x4000U
  #define GPIOC_DDR_DD15_MASK           0x8000U
  #define GPIOC_DDR                     (*((volatile word *)0x0000E222))


  /*** GPIOC_PER - GPIO Peripheral Enable Register; 0x0000E223 ***/
  union {
    word Word;
  } GPIOC_PER_STR;

  #define GPIOC_PER_PE0_MASK            0x01U
  #define GPIOC_PER_PE1_MASK            0x02U
  #define GPIOC_PER_PE2_MASK            0x04U
  #define GPIOC_PER_PE3_MASK            0x08U
  #define GPIOC_PER_PE4_MASK            0x10U
  #define GPIOC_PER_PE5_MASK            0x20U
  #define GPIOC_PER_PE6_MASK            0x40U
  #define GPIOC_PER_PE7_MASK            0x80U
  #define GPIOC_PER_PE8_MASK            0x0100U
  #define GPIOC_PER_PE9_MASK            0x0200U
  #define GPIOC_PER_PE10_MASK           0x0400U
  #define GPIOC_PER_PE11_MASK           0x0800U
  #define GPIOC_PER_PE12_MASK           0x1000U
  #define GPIOC_PER_PE13_MASK           0x2000U
  #define GPIOC_PER_PE14_MASK           0x4000U
  #define GPIOC_PER_PE15_MASK           0x8000U
  #define GPIOC_PER                     (*((volatile word *)0x0000E223))


  /*** GPIOC_IAR - GPIO Interrupt Assert Register; 0x0000E224 ***/
  union {
    word Word;
  } GPIOC_IAR_STR;

  #define GPIOC_IAR_IA0_MASK            0x01U
  #define GPIOC_IAR_IA1_MASK            0x02U
  #define GPIOC_IAR_IA2_MASK            0x04U
  #define GPIOC_IAR_IA3_MASK            0x08U
  #define GPIOC_IAR_IA4_MASK            0x10U
  #define GPIOC_IAR_IA5_MASK            0x20U
  #define GPIOC_IAR_IA6_MASK            0x40U
  #define GPIOC_IAR_IA7_MASK            0x80U
  #define GPIOC_IAR_IA8_MASK            0x0100U
  #define GPIOC_IAR_IA9_MASK            0x0200U
  #define GPIOC_IAR_IA10_MASK           0x0400U
  #define GPIOC_IAR_IA11_MASK           0x0800U
  #define GPIOC_IAR_IA12_MASK           0x1000U
  #define GPIOC_IAR_IA13_MASK           0x2000U
  #define GPIOC_IAR_IA14_MASK           0x4000U
  #define GPIOC_IAR_IA15_MASK           0x8000U
  #define GPIOC_IAR                     (*((volatile word *)0x0000E224))


  /*** GPIOC_IENR - GPIO Interrupt Enable Register; 0x0000E225 ***/
  union {
    word Word;
  } GPIOC_IENR_STR;

  #define GPIOC_IENR_IEN0_MASK          0x01U
  #define GPIOC_IENR_IEN1_MASK          0x02U
  #define GPIOC_IENR_IEN2_MASK          0x04U
  #define GPIOC_IENR_IEN3_MASK          0x08U
  #define GPIOC_IENR_IEN4_MASK          0x10U
  #define GPIOC_IENR_IEN5_MASK          0x20U
  #define GPIOC_IENR_IEN6_MASK          0x40U
  #define GPIOC_IENR_IEN7_MASK          0x80U
  #define GPIOC_IENR_IEN8_MASK          0x0100U
  #define GPIOC_IENR_IEN9_MASK          0x0200U
  #define GPIOC_IENR_IEN10_MASK         0x0400U
  #define GPIOC_IENR_IEN11_MASK         0x0800U
  #define GPIOC_IENR_IEN12_MASK         0x1000U
  #define GPIOC_IENR_IEN13_MASK         0x2000U
  #define GPIOC_IENR_IEN14_MASK         0x4000U
  #define GPIOC_IENR_IEN15_MASK         0x8000U
  #define GPIOC_IENR                    (*((volatile word *)0x0000E225))


  /*** GPIOC_IPOLR - GPIO Interrupt Polarity Register; 0x0000E226 ***/
  union {
    word Word;
  } GPIOC_IPOLR_STR;

  #define GPIOC_IPOLR_IPOL0_MASK        0x01U
  #define GPIOC_IPOLR_IPOL1_MASK        0x02U
  #define GPIOC_IPOLR_IPOL2_MASK        0x04U
  #define GPIOC_IPOLR_IPOL3_MASK        0x08U
  #define GPIOC_IPOLR_IPOL4_MASK        0x10U
  #define GPIOC_IPOLR_IPOL5_MASK        0x20U
  #define GPIOC_IPOLR_IPOL6_MASK        0x40U
  #define GPIOC_IPOLR_IPOL7_MASK        0x80U
  #define GPIOC_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOC_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOC_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOC_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOC_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOC_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOC_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOC_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOC_IPOLR                   (*((volatile word *)0x0000E226))


  /*** GPIOC_IPR - GPIO Interrupt Pending Register; 0x0000E227 ***/
  union {
    word Word;
  } GPIOC_IPR_STR;

  #define GPIOC_IPR_IP0_MASK            0x01U
  #define GPIOC_IPR_IP1_MASK            0x02U
  #define GPIOC_IPR_IP2_MASK            0x04U
  #define GPIOC_IPR_IP3_MASK            0x08U
  #define GPIOC_IPR_IP4_MASK            0x10U
  #define GPIOC_IPR_IP5_MASK            0x20U
  #define GPIOC_IPR_IP6_MASK            0x40U
  #define GPIOC_IPR_IP7_MASK            0x80U
  #define GPIOC_IPR_IP8_MASK            0x0100U
  #define GPIOC_IPR_IP9_MASK            0x0200U
  #define GPIOC_IPR_IP10_MASK           0x0400U
  #define GPIOC_IPR_IP11_MASK           0x0800U
  #define GPIOC_IPR_IP12_MASK           0x1000U
  #define GPIOC_IPR_IP13_MASK           0x2000U
  #define GPIOC_IPR_IP14_MASK           0x4000U
  #define GPIOC_IPR_IP15_MASK           0x8000U
  #define GPIOC_IPR                     (*((volatile word *)0x0000E227))


  /*** GPIOC_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E228 ***/
  union {
    word Word;
  } GPIOC_IESR_STR;

  #define GPIOC_IESR_IES0_MASK          0x01U
  #define GPIOC_IESR_IES1_MASK          0x02U
  #define GPIOC_IESR_IES2_MASK          0x04U
  #define GPIOC_IESR_IES3_MASK          0x08U
  #define GPIOC_IESR_IES4_MASK          0x10U
  #define GPIOC_IESR_IES5_MASK          0x20U
  #define GPIOC_IESR_IES6_MASK          0x40U
  #define GPIOC_IESR_IES7_MASK          0x80U
  #define GPIOC_IESR_IES8_MASK          0x0100U
  #define GPIOC_IESR_IES9_MASK          0x0200U
  #define GPIOC_IESR_IES10_MASK         0x0400U
  #define GPIOC_IESR_IES11_MASK         0x0800U
  #define GPIOC_IESR_IES12_MASK         0x1000U
  #define GPIOC_IESR_IES13_MASK         0x2000U
  #define GPIOC_IESR_IES14_MASK         0x4000U
  #define GPIOC_IESR_IES15_MASK         0x8000U
  #define GPIOC_IESR                    (*((volatile word *)0x0000E228))


  /*** GPIOC_PPMODE - GPIO Push-Pull Mode Register; 0x0000E229 ***/
  union {
    word Word;
  } GPIOC_PPMODE_STR;

  #define GPIOC_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOC_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOC_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOC_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOC_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOC_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOC_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOC_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOC_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOC_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOC_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOC_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOC_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOC_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOC_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOC_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOC_PPMODE                  (*((volatile word *)0x0000E229))


  /*** GPIOC_RAWDATA - GPIO Raw Data Register; 0x0000E22A ***/
  union {
    word Word;
  } GPIOC_RAWDATA_STR;

  #define GPIOC_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOC_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOC_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOC_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOC_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOC_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOC_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOC_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOC_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOC_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOC_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOC_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOC_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOC_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOC_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOC_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOC_RAWDATA                 (*((volatile word *)0x0000E22A))


  /*** GPIOC_DRIVE - GPIO Drive Strength Control Register; 0x0000E22B ***/
  union {
    word Word;
  } GPIOC_DRIVE_STR;

  #define GPIOC_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOC_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOC_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOC_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOC_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOC_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOC_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOC_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOC_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOC_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOC_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOC_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOC_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOC_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOC_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOC_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOC_DRIVE                   (*((volatile word *)0x0000E22B))


  /*** GPIOC_PUS - GPIO Pull Resistor Type Select; 0x0000E22C ***/
  union {
    word Word;
  } GPIOC_PUS_STR;

  #define GPIOC_PUS_PUS0_MASK           0x01U
  #define GPIOC_PUS_PUS1_MASK           0x02U
  #define GPIOC_PUS_PUS2_MASK           0x04U
  #define GPIOC_PUS_PUS3_MASK           0x08U
  #define GPIOC_PUS_PUS4_MASK           0x10U
  #define GPIOC_PUS_PUS5_MASK           0x20U
  #define GPIOC_PUS_PUS6_MASK           0x40U
  #define GPIOC_PUS_PUS7_MASK           0x80U
  #define GPIOC_PUS_PUS8_MASK           0x0100U
  #define GPIOC_PUS_PUS9_MASK           0x0200U
  #define GPIOC_PUS_PUS10_MASK          0x0400U
  #define GPIOC_PUS_PUS11_MASK          0x0800U
  #define GPIOC_PUS_PUS12_MASK          0x1000U
  #define GPIOC_PUS_PUS13_MASK          0x2000U
  #define GPIOC_PUS_PUS14_MASK          0x4000U
  #define GPIOC_PUS_PUS15_MASK          0x8000U
  #define GPIOC_PUS                     (*((volatile word *)0x0000E22C))


  /*** GPIOC_SRE - Slew Rate Control Register; 0x0000E22D ***/
  union {
    word Word;
  } GPIOC_SRE_STR;

  #define GPIOC_SRE_SRE0_MASK           0x01U
  #define GPIOC_SRE_SRE1_MASK           0x02U
  #define GPIOC_SRE_SRE2_MASK           0x04U
  #define GPIOC_SRE_SRE3_MASK           0x08U
  #define GPIOC_SRE_SRE4_MASK           0x10U
  #define GPIOC_SRE_SRE5_MASK           0x20U
  #define GPIOC_SRE_SRE6_MASK           0x40U
  #define GPIOC_SRE_SRE7_MASK           0x80U
  #define GPIOC_SRE_SRE8_MASK           0x0100U
  #define GPIOC_SRE_SRE9_MASK           0x0200U
  #define GPIOC_SRE_SRE10_MASK          0x0400U
  #define GPIOC_SRE_SRE11_MASK          0x0800U
  #define GPIOC_SRE_SRE12_MASK          0x1000U
  #define GPIOC_SRE_SRE13_MASK          0x2000U
  #define GPIOC_SRE_SRE14_MASK          0x4000U
  #define GPIOC_SRE_SRE15_MASK          0x8000U
  #define GPIOC_SRE                     (*((volatile word *)0x0000E22D))


} GPIOC_PRPH;
/******************************************
*** Peripheral GPIOD
*******************************************/
typedef volatile struct {
  /*** GPIOD_PUR - GPIO Pull Resistor Enable Register; 0x0000E230 ***/
  union {
    word Word;
  } GPIOD_PUR_STR;

  #define GPIOD_PUR_PU0_MASK            0x01U
  #define GPIOD_PUR_PU1_MASK            0x02U
  #define GPIOD_PUR_PU2_MASK            0x04U
  #define GPIOD_PUR_PU3_MASK            0x08U
  #define GPIOD_PUR_PU4_MASK            0x10U
  #define GPIOD_PUR_PU5_MASK            0x20U
  #define GPIOD_PUR_PU6_MASK            0x40U
  #define GPIOD_PUR_PU7_MASK            0x80U
  #define GPIOD_PUR_PU8_MASK            0x0100U
  #define GPIOD_PUR_PU9_MASK            0x0200U
  #define GPIOD_PUR_PU10_MASK           0x0400U
  #define GPIOD_PUR_PU11_MASK           0x0800U
  #define GPIOD_PUR_PU12_MASK           0x1000U
  #define GPIOD_PUR_PU13_MASK           0x2000U
  #define GPIOD_PUR_PU14_MASK           0x4000U
  #define GPIOD_PUR_PU15_MASK           0x8000U
  #define GPIOD_PUR                     (*((volatile word *)0x0000E230))


  /*** GPIOD_DR - GPIO Data Register; 0x0000E231 ***/
  union {
    word Word;
  } GPIOD_DR_STR;

  #define GPIOD_DR_D0_MASK              0x01U
  #define GPIOD_DR_D1_MASK              0x02U
  #define GPIOD_DR_D2_MASK              0x04U
  #define GPIOD_DR_D3_MASK              0x08U
  #define GPIOD_DR_D4_MASK              0x10U
  #define GPIOD_DR_D5_MASK              0x20U
  #define GPIOD_DR_D6_MASK              0x40U
  #define GPIOD_DR_D7_MASK              0x80U
  #define GPIOD_DR_D8_MASK              0x0100U
  #define GPIOD_DR_D9_MASK              0x0200U
  #define GPIOD_DR_D10_MASK             0x0400U
  #define GPIOD_DR_D11_MASK             0x0800U
  #define GPIOD_DR_D12_MASK             0x1000U
  #define GPIOD_DR_D13_MASK             0x2000U
  #define GPIOD_DR_D14_MASK             0x4000U
  #define GPIOD_DR_D15_MASK             0x8000U
  #define GPIOD_DR                      (*((volatile word *)0x0000E231))


  /*** GPIOD_DDR - GPIO Data Direction Register; 0x0000E232 ***/
  union {
    word Word;
  } GPIOD_DDR_STR;

  #define GPIOD_DDR_DD0_MASK            0x01U
  #define GPIOD_DDR_DD1_MASK            0x02U
  #define GPIOD_DDR_DD2_MASK            0x04U
  #define GPIOD_DDR_DD3_MASK            0x08U
  #define GPIOD_DDR_DD4_MASK            0x10U
  #define GPIOD_DDR_DD5_MASK            0x20U
  #define GPIOD_DDR_DD6_MASK            0x40U
  #define GPIOD_DDR_DD7_MASK            0x80U
  #define GPIOD_DDR_DD8_MASK            0x0100U
  #define GPIOD_DDR_DD9_MASK            0x0200U
  #define GPIOD_DDR_DD10_MASK           0x0400U
  #define GPIOD_DDR_DD11_MASK           0x0800U
  #define GPIOD_DDR_DD12_MASK           0x1000U
  #define GPIOD_DDR_DD13_MASK           0x2000U
  #define GPIOD_DDR_DD14_MASK           0x4000U
  #define GPIOD_DDR_DD15_MASK           0x8000U
  #define GPIOD_DDR                     (*((volatile word *)0x0000E232))


  /*** GPIOD_PER - GPIO Peripheral Enable Register; 0x0000E233 ***/
  union {
    word Word;
  } GPIOD_PER_STR;

  #define GPIOD_PER_PE0_MASK            0x01U
  #define GPIOD_PER_PE1_MASK            0x02U
  #define GPIOD_PER_PE2_MASK            0x04U
  #define GPIOD_PER_PE3_MASK            0x08U
  #define GPIOD_PER_PE4_MASK            0x10U
  #define GPIOD_PER_PE5_MASK            0x20U
  #define GPIOD_PER_PE6_MASK            0x40U
  #define GPIOD_PER_PE7_MASK            0x80U
  #define GPIOD_PER_PE8_MASK            0x0100U
  #define GPIOD_PER_PE9_MASK            0x0200U
  #define GPIOD_PER_PE10_MASK           0x0400U
  #define GPIOD_PER_PE11_MASK           0x0800U
  #define GPIOD_PER_PE12_MASK           0x1000U
  #define GPIOD_PER_PE13_MASK           0x2000U
  #define GPIOD_PER_PE14_MASK           0x4000U
  #define GPIOD_PER_PE15_MASK           0x8000U
  #define GPIOD_PER                     (*((volatile word *)0x0000E233))


  /*** GPIOD_IAR - GPIO Interrupt Assert Register; 0x0000E234 ***/
  union {
    word Word;
  } GPIOD_IAR_STR;

  #define GPIOD_IAR_IA0_MASK            0x01U
  #define GPIOD_IAR_IA1_MASK            0x02U
  #define GPIOD_IAR_IA2_MASK            0x04U
  #define GPIOD_IAR_IA3_MASK            0x08U
  #define GPIOD_IAR_IA4_MASK            0x10U
  #define GPIOD_IAR_IA5_MASK            0x20U
  #define GPIOD_IAR_IA6_MASK            0x40U
  #define GPIOD_IAR_IA7_MASK            0x80U
  #define GPIOD_IAR_IA8_MASK            0x0100U
  #define GPIOD_IAR_IA9_MASK            0x0200U
  #define GPIOD_IAR_IA10_MASK           0x0400U
  #define GPIOD_IAR_IA11_MASK           0x0800U
  #define GPIOD_IAR_IA12_MASK           0x1000U
  #define GPIOD_IAR_IA13_MASK           0x2000U
  #define GPIOD_IAR_IA14_MASK           0x4000U
  #define GPIOD_IAR_IA15_MASK           0x8000U
  #define GPIOD_IAR                     (*((volatile word *)0x0000E234))


  /*** GPIOD_IENR - GPIO Interrupt Enable Register; 0x0000E235 ***/
  union {
    word Word;
  } GPIOD_IENR_STR;

  #define GPIOD_IENR_IEN0_MASK          0x01U
  #define GPIOD_IENR_IEN1_MASK          0x02U
  #define GPIOD_IENR_IEN2_MASK          0x04U
  #define GPIOD_IENR_IEN3_MASK          0x08U
  #define GPIOD_IENR_IEN4_MASK          0x10U
  #define GPIOD_IENR_IEN5_MASK          0x20U
  #define GPIOD_IENR_IEN6_MASK          0x40U
  #define GPIOD_IENR_IEN7_MASK          0x80U
  #define GPIOD_IENR_IEN8_MASK          0x0100U
  #define GPIOD_IENR_IEN9_MASK          0x0200U
  #define GPIOD_IENR_IEN10_MASK         0x0400U
  #define GPIOD_IENR_IEN11_MASK         0x0800U
  #define GPIOD_IENR_IEN12_MASK         0x1000U
  #define GPIOD_IENR_IEN13_MASK         0x2000U
  #define GPIOD_IENR_IEN14_MASK         0x4000U
  #define GPIOD_IENR_IEN15_MASK         0x8000U
  #define GPIOD_IENR                    (*((volatile word *)0x0000E235))


  /*** GPIOD_IPOLR - GPIO Interrupt Polarity Register; 0x0000E236 ***/
  union {
    word Word;
  } GPIOD_IPOLR_STR;

  #define GPIOD_IPOLR_IPOL0_MASK        0x01U
  #define GPIOD_IPOLR_IPOL1_MASK        0x02U
  #define GPIOD_IPOLR_IPOL2_MASK        0x04U
  #define GPIOD_IPOLR_IPOL3_MASK        0x08U
  #define GPIOD_IPOLR_IPOL4_MASK        0x10U
  #define GPIOD_IPOLR_IPOL5_MASK        0x20U
  #define GPIOD_IPOLR_IPOL6_MASK        0x40U
  #define GPIOD_IPOLR_IPOL7_MASK        0x80U
  #define GPIOD_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOD_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOD_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOD_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOD_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOD_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOD_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOD_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOD_IPOLR                   (*((volatile word *)0x0000E236))


  /*** GPIOD_IPR - GPIO Interrupt Pending Register; 0x0000E237 ***/
  union {
    word Word;
  } GPIOD_IPR_STR;

  #define GPIOD_IPR_IP0_MASK            0x01U
  #define GPIOD_IPR_IP1_MASK            0x02U
  #define GPIOD_IPR_IP2_MASK            0x04U
  #define GPIOD_IPR_IP3_MASK            0x08U
  #define GPIOD_IPR_IP4_MASK            0x10U
  #define GPIOD_IPR_IP5_MASK            0x20U
  #define GPIOD_IPR_IP6_MASK            0x40U
  #define GPIOD_IPR_IP7_MASK            0x80U
  #define GPIOD_IPR_IP8_MASK            0x0100U
  #define GPIOD_IPR_IP9_MASK            0x0200U
  #define GPIOD_IPR_IP10_MASK           0x0400U
  #define GPIOD_IPR_IP11_MASK           0x0800U
  #define GPIOD_IPR_IP12_MASK           0x1000U
  #define GPIOD_IPR_IP13_MASK           0x2000U
  #define GPIOD_IPR_IP14_MASK           0x4000U
  #define GPIOD_IPR_IP15_MASK           0x8000U
  #define GPIOD_IPR                     (*((volatile word *)0x0000E237))


  /*** GPIOD_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E238 ***/
  union {
    word Word;
  } GPIOD_IESR_STR;

  #define GPIOD_IESR_IES0_MASK          0x01U
  #define GPIOD_IESR_IES1_MASK          0x02U
  #define GPIOD_IESR_IES2_MASK          0x04U
  #define GPIOD_IESR_IES3_MASK          0x08U
  #define GPIOD_IESR_IES4_MASK          0x10U
  #define GPIOD_IESR_IES5_MASK          0x20U
  #define GPIOD_IESR_IES6_MASK          0x40U
  #define GPIOD_IESR_IES7_MASK          0x80U
  #define GPIOD_IESR_IES8_MASK          0x0100U
  #define GPIOD_IESR_IES9_MASK          0x0200U
  #define GPIOD_IESR_IES10_MASK         0x0400U
  #define GPIOD_IESR_IES11_MASK         0x0800U
  #define GPIOD_IESR_IES12_MASK         0x1000U
  #define GPIOD_IESR_IES13_MASK         0x2000U
  #define GPIOD_IESR_IES14_MASK         0x4000U
  #define GPIOD_IESR_IES15_MASK         0x8000U
  #define GPIOD_IESR                    (*((volatile word *)0x0000E238))


  /*** GPIOD_PPMODE - GPIO Push-Pull Mode Register; 0x0000E239 ***/
  union {
    word Word;
  } GPIOD_PPMODE_STR;

  #define GPIOD_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOD_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOD_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOD_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOD_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOD_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOD_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOD_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOD_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOD_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOD_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOD_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOD_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOD_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOD_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOD_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOD_PPMODE                  (*((volatile word *)0x0000E239))


  /*** GPIOD_RAWDATA - GPIO Raw Data Register; 0x0000E23A ***/
  union {
    word Word;
  } GPIOD_RAWDATA_STR;

  #define GPIOD_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOD_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOD_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOD_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOD_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOD_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOD_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOD_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOD_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOD_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOD_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOD_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOD_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOD_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOD_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOD_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOD_RAWDATA                 (*((volatile word *)0x0000E23A))


  /*** GPIOD_DRIVE - GPIO Drive Strength Control Register; 0x0000E23B ***/
  union {
    word Word;
  } GPIOD_DRIVE_STR;

  #define GPIOD_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOD_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOD_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOD_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOD_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOD_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOD_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOD_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOD_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOD_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOD_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOD_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOD_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOD_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOD_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOD_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOD_DRIVE                   (*((volatile word *)0x0000E23B))


  /*** GPIOD_PUS - GPIO Pull Resistor Type Select; 0x0000E23C ***/
  union {
    word Word;
  } GPIOD_PUS_STR;

  #define GPIOD_PUS_PUS0_MASK           0x01U
  #define GPIOD_PUS_PUS1_MASK           0x02U
  #define GPIOD_PUS_PUS2_MASK           0x04U
  #define GPIOD_PUS_PUS3_MASK           0x08U
  #define GPIOD_PUS_PUS4_MASK           0x10U
  #define GPIOD_PUS_PUS5_MASK           0x20U
  #define GPIOD_PUS_PUS6_MASK           0x40U
  #define GPIOD_PUS_PUS7_MASK           0x80U
  #define GPIOD_PUS_PUS8_MASK           0x0100U
  #define GPIOD_PUS_PUS9_MASK           0x0200U
  #define GPIOD_PUS_PUS10_MASK          0x0400U
  #define GPIOD_PUS_PUS11_MASK          0x0800U
  #define GPIOD_PUS_PUS12_MASK          0x1000U
  #define GPIOD_PUS_PUS13_MASK          0x2000U
  #define GPIOD_PUS_PUS14_MASK          0x4000U
  #define GPIOD_PUS_PUS15_MASK          0x8000U
  #define GPIOD_PUS                     (*((volatile word *)0x0000E23C))


  /*** GPIOD_SRE - Slew Rate Control Register; 0x0000E23D ***/
  union {
    word Word;
  } GPIOD_SRE_STR;

  #define GPIOD_SRE_SRE0_MASK           0x01U
  #define GPIOD_SRE_SRE1_MASK           0x02U
  #define GPIOD_SRE_SRE2_MASK           0x04U
  #define GPIOD_SRE_SRE3_MASK           0x08U
  #define GPIOD_SRE_SRE4_MASK           0x10U
  #define GPIOD_SRE_SRE5_MASK           0x20U
  #define GPIOD_SRE_SRE6_MASK           0x40U
  #define GPIOD_SRE_SRE7_MASK           0x80U
  #define GPIOD_SRE_SRE8_MASK           0x0100U
  #define GPIOD_SRE_SRE9_MASK           0x0200U
  #define GPIOD_SRE_SRE10_MASK          0x0400U
  #define GPIOD_SRE_SRE11_MASK          0x0800U
  #define GPIOD_SRE_SRE12_MASK          0x1000U
  #define GPIOD_SRE_SRE13_MASK          0x2000U
  #define GPIOD_SRE_SRE14_MASK          0x4000U
  #define GPIOD_SRE_SRE15_MASK          0x8000U
  #define GPIOD_SRE                     (*((volatile word *)0x0000E23D))


} GPIOD_PRPH;
/******************************************
*** Peripheral GPIOE
*******************************************/
typedef volatile struct {
  /*** GPIOE_PUR - GPIO Pull Resistor Enable Register; 0x0000E240 ***/
  union {
    word Word;
  } GPIOE_PUR_STR;

  #define GPIOE_PUR_PU0_MASK            0x01U
  #define GPIOE_PUR_PU1_MASK            0x02U
  #define GPIOE_PUR_PU2_MASK            0x04U
  #define GPIOE_PUR_PU3_MASK            0x08U
  #define GPIOE_PUR_PU4_MASK            0x10U
  #define GPIOE_PUR_PU5_MASK            0x20U
  #define GPIOE_PUR_PU6_MASK            0x40U
  #define GPIOE_PUR_PU7_MASK            0x80U
  #define GPIOE_PUR_PU8_MASK            0x0100U
  #define GPIOE_PUR_PU9_MASK            0x0200U
  #define GPIOE_PUR_PU10_MASK           0x0400U
  #define GPIOE_PUR_PU11_MASK           0x0800U
  #define GPIOE_PUR_PU12_MASK           0x1000U
  #define GPIOE_PUR_PU13_MASK           0x2000U
  #define GPIOE_PUR_PU14_MASK           0x4000U
  #define GPIOE_PUR_PU15_MASK           0x8000U
  #define GPIOE_PUR                     (*((volatile word *)0x0000E240))


  /*** GPIOE_DR - GPIO Data Register; 0x0000E241 ***/
  union {
    word Word;
  } GPIOE_DR_STR;

  #define GPIOE_DR_D0_MASK              0x01U
  #define GPIOE_DR_D1_MASK              0x02U
  #define GPIOE_DR_D2_MASK              0x04U
  #define GPIOE_DR_D3_MASK              0x08U
  #define GPIOE_DR_D4_MASK              0x10U
  #define GPIOE_DR_D5_MASK              0x20U
  #define GPIOE_DR_D6_MASK              0x40U
  #define GPIOE_DR_D7_MASK              0x80U
  #define GPIOE_DR_D8_MASK              0x0100U
  #define GPIOE_DR_D9_MASK              0x0200U
  #define GPIOE_DR_D10_MASK             0x0400U
  #define GPIOE_DR_D11_MASK             0x0800U
  #define GPIOE_DR_D12_MASK             0x1000U
  #define GPIOE_DR_D13_MASK             0x2000U
  #define GPIOE_DR_D14_MASK             0x4000U
  #define GPIOE_DR_D15_MASK             0x8000U
  #define GPIOE_DR                      (*((volatile word *)0x0000E241))


  /*** GPIOE_DDR - GPIO Data Direction Register; 0x0000E242 ***/
  union {
    word Word;
  } GPIOE_DDR_STR;

  #define GPIOE_DDR_DD0_MASK            0x01U
  #define GPIOE_DDR_DD1_MASK            0x02U
  #define GPIOE_DDR_DD2_MASK            0x04U
  #define GPIOE_DDR_DD3_MASK            0x08U
  #define GPIOE_DDR_DD4_MASK            0x10U
  #define GPIOE_DDR_DD5_MASK            0x20U
  #define GPIOE_DDR_DD6_MASK            0x40U
  #define GPIOE_DDR_DD7_MASK            0x80U
  #define GPIOE_DDR_DD8_MASK            0x0100U
  #define GPIOE_DDR_DD9_MASK            0x0200U
  #define GPIOE_DDR_DD10_MASK           0x0400U
  #define GPIOE_DDR_DD11_MASK           0x0800U
  #define GPIOE_DDR_DD12_MASK           0x1000U
  #define GPIOE_DDR_DD13_MASK           0x2000U
  #define GPIOE_DDR_DD14_MASK           0x4000U
  #define GPIOE_DDR_DD15_MASK           0x8000U
  #define GPIOE_DDR                     (*((volatile word *)0x0000E242))


  /*** GPIOE_PER - GPIO Peripheral Enable Register; 0x0000E243 ***/
  union {
    word Word;
  } GPIOE_PER_STR;

  #define GPIOE_PER_PE0_MASK            0x01U
  #define GPIOE_PER_PE1_MASK            0x02U
  #define GPIOE_PER_PE2_MASK            0x04U
  #define GPIOE_PER_PE3_MASK            0x08U
  #define GPIOE_PER_PE4_MASK            0x10U
  #define GPIOE_PER_PE5_MASK            0x20U
  #define GPIOE_PER_PE6_MASK            0x40U
  #define GPIOE_PER_PE7_MASK            0x80U
  #define GPIOE_PER_PE8_MASK            0x0100U
  #define GPIOE_PER_PE9_MASK            0x0200U
  #define GPIOE_PER_PE10_MASK           0x0400U
  #define GPIOE_PER_PE11_MASK           0x0800U
  #define GPIOE_PER_PE12_MASK           0x1000U
  #define GPIOE_PER_PE13_MASK           0x2000U
  #define GPIOE_PER_PE14_MASK           0x4000U
  #define GPIOE_PER_PE15_MASK           0x8000U
  #define GPIOE_PER                     (*((volatile word *)0x0000E243))


  /*** GPIOE_IAR - GPIO Interrupt Assert Register; 0x0000E244 ***/
  union {
    word Word;
  } GPIOE_IAR_STR;

  #define GPIOE_IAR_IA0_MASK            0x01U
  #define GPIOE_IAR_IA1_MASK            0x02U
  #define GPIOE_IAR_IA2_MASK            0x04U
  #define GPIOE_IAR_IA3_MASK            0x08U
  #define GPIOE_IAR_IA4_MASK            0x10U
  #define GPIOE_IAR_IA5_MASK            0x20U
  #define GPIOE_IAR_IA6_MASK            0x40U
  #define GPIOE_IAR_IA7_MASK            0x80U
  #define GPIOE_IAR_IA8_MASK            0x0100U
  #define GPIOE_IAR_IA9_MASK            0x0200U
  #define GPIOE_IAR_IA10_MASK           0x0400U
  #define GPIOE_IAR_IA11_MASK           0x0800U
  #define GPIOE_IAR_IA12_MASK           0x1000U
  #define GPIOE_IAR_IA13_MASK           0x2000U
  #define GPIOE_IAR_IA14_MASK           0x4000U
  #define GPIOE_IAR_IA15_MASK           0x8000U
  #define GPIOE_IAR                     (*((volatile word *)0x0000E244))


  /*** GPIOE_IENR - GPIO Interrupt Enable Register; 0x0000E245 ***/
  union {
    word Word;
  } GPIOE_IENR_STR;

  #define GPIOE_IENR_IEN0_MASK          0x01U
  #define GPIOE_IENR_IEN1_MASK          0x02U
  #define GPIOE_IENR_IEN2_MASK          0x04U
  #define GPIOE_IENR_IEN3_MASK          0x08U
  #define GPIOE_IENR_IEN4_MASK          0x10U
  #define GPIOE_IENR_IEN5_MASK          0x20U
  #define GPIOE_IENR_IEN6_MASK          0x40U
  #define GPIOE_IENR_IEN7_MASK          0x80U
  #define GPIOE_IENR_IEN8_MASK          0x0100U
  #define GPIOE_IENR_IEN9_MASK          0x0200U
  #define GPIOE_IENR_IEN10_MASK         0x0400U
  #define GPIOE_IENR_IEN11_MASK         0x0800U
  #define GPIOE_IENR_IEN12_MASK         0x1000U
  #define GPIOE_IENR_IEN13_MASK         0x2000U
  #define GPIOE_IENR_IEN14_MASK         0x4000U
  #define GPIOE_IENR_IEN15_MASK         0x8000U
  #define GPIOE_IENR                    (*((volatile word *)0x0000E245))


  /*** GPIOE_IPOLR - GPIO Interrupt Polarity Register; 0x0000E246 ***/
  union {
    word Word;
  } GPIOE_IPOLR_STR;

  #define GPIOE_IPOLR_IPOL0_MASK        0x01U
  #define GPIOE_IPOLR_IPOL1_MASK        0x02U
  #define GPIOE_IPOLR_IPOL2_MASK        0x04U
  #define GPIOE_IPOLR_IPOL3_MASK        0x08U
  #define GPIOE_IPOLR_IPOL4_MASK        0x10U
  #define GPIOE_IPOLR_IPOL5_MASK        0x20U
  #define GPIOE_IPOLR_IPOL6_MASK        0x40U
  #define GPIOE_IPOLR_IPOL7_MASK        0x80U
  #define GPIOE_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOE_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOE_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOE_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOE_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOE_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOE_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOE_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOE_IPOLR                   (*((volatile word *)0x0000E246))


  /*** GPIOE_IPR - GPIO Interrupt Pending Register; 0x0000E247 ***/
  union {
    word Word;
  } GPIOE_IPR_STR;

  #define GPIOE_IPR_IP0_MASK            0x01U
  #define GPIOE_IPR_IP1_MASK            0x02U
  #define GPIOE_IPR_IP2_MASK            0x04U
  #define GPIOE_IPR_IP3_MASK            0x08U
  #define GPIOE_IPR_IP4_MASK            0x10U
  #define GPIOE_IPR_IP5_MASK            0x20U
  #define GPIOE_IPR_IP6_MASK            0x40U
  #define GPIOE_IPR_IP7_MASK            0x80U
  #define GPIOE_IPR_IP8_MASK            0x0100U
  #define GPIOE_IPR_IP9_MASK            0x0200U
  #define GPIOE_IPR_IP10_MASK           0x0400U
  #define GPIOE_IPR_IP11_MASK           0x0800U
  #define GPIOE_IPR_IP12_MASK           0x1000U
  #define GPIOE_IPR_IP13_MASK           0x2000U
  #define GPIOE_IPR_IP14_MASK           0x4000U
  #define GPIOE_IPR_IP15_MASK           0x8000U
  #define GPIOE_IPR                     (*((volatile word *)0x0000E247))


  /*** GPIOE_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E248 ***/
  union {
    word Word;
  } GPIOE_IESR_STR;

  #define GPIOE_IESR_IES0_MASK          0x01U
  #define GPIOE_IESR_IES1_MASK          0x02U
  #define GPIOE_IESR_IES2_MASK          0x04U
  #define GPIOE_IESR_IES3_MASK          0x08U
  #define GPIOE_IESR_IES4_MASK          0x10U
  #define GPIOE_IESR_IES5_MASK          0x20U
  #define GPIOE_IESR_IES6_MASK          0x40U
  #define GPIOE_IESR_IES7_MASK          0x80U
  #define GPIOE_IESR_IES8_MASK          0x0100U
  #define GPIOE_IESR_IES9_MASK          0x0200U
  #define GPIOE_IESR_IES10_MASK         0x0400U
  #define GPIOE_IESR_IES11_MASK         0x0800U
  #define GPIOE_IESR_IES12_MASK         0x1000U
  #define GPIOE_IESR_IES13_MASK         0x2000U
  #define GPIOE_IESR_IES14_MASK         0x4000U
  #define GPIOE_IESR_IES15_MASK         0x8000U
  #define GPIOE_IESR                    (*((volatile word *)0x0000E248))


  /*** GPIOE_PPMODE - GPIO Push-Pull Mode Register; 0x0000E249 ***/
  union {
    word Word;
  } GPIOE_PPMODE_STR;

  #define GPIOE_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOE_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOE_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOE_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOE_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOE_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOE_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOE_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOE_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOE_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOE_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOE_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOE_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOE_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOE_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOE_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOE_PPMODE                  (*((volatile word *)0x0000E249))


  /*** GPIOE_RAWDATA - GPIO Raw Data Register; 0x0000E24A ***/
  union {
    word Word;
  } GPIOE_RAWDATA_STR;

  #define GPIOE_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOE_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOE_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOE_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOE_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOE_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOE_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOE_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOE_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOE_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOE_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOE_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOE_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOE_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOE_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOE_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOE_RAWDATA                 (*((volatile word *)0x0000E24A))


  /*** GPIOE_DRIVE - GPIO Drive Strength Control Register; 0x0000E24B ***/
  union {
    word Word;
  } GPIOE_DRIVE_STR;

  #define GPIOE_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOE_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOE_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOE_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOE_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOE_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOE_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOE_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOE_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOE_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOE_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOE_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOE_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOE_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOE_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOE_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOE_DRIVE                   (*((volatile word *)0x0000E24B))


  /*** GPIOE_PUS - GPIO Pull Resistor Type Select; 0x0000E24C ***/
  union {
    word Word;
  } GPIOE_PUS_STR;

  #define GPIOE_PUS_PUS0_MASK           0x01U
  #define GPIOE_PUS_PUS1_MASK           0x02U
  #define GPIOE_PUS_PUS2_MASK           0x04U
  #define GPIOE_PUS_PUS3_MASK           0x08U
  #define GPIOE_PUS_PUS4_MASK           0x10U
  #define GPIOE_PUS_PUS5_MASK           0x20U
  #define GPIOE_PUS_PUS6_MASK           0x40U
  #define GPIOE_PUS_PUS7_MASK           0x80U
  #define GPIOE_PUS_PUS8_MASK           0x0100U
  #define GPIOE_PUS_PUS9_MASK           0x0200U
  #define GPIOE_PUS_PUS10_MASK          0x0400U
  #define GPIOE_PUS_PUS11_MASK          0x0800U
  #define GPIOE_PUS_PUS12_MASK          0x1000U
  #define GPIOE_PUS_PUS13_MASK          0x2000U
  #define GPIOE_PUS_PUS14_MASK          0x4000U
  #define GPIOE_PUS_PUS15_MASK          0x8000U
  #define GPIOE_PUS                     (*((volatile word *)0x0000E24C))


  /*** GPIOE_SRE - Slew Rate Control Register; 0x0000E24D ***/
  union {
    word Word;
  } GPIOE_SRE_STR;

  #define GPIOE_SRE_SRE0_MASK           0x01U
  #define GPIOE_SRE_SRE1_MASK           0x02U
  #define GPIOE_SRE_SRE2_MASK           0x04U
  #define GPIOE_SRE_SRE3_MASK           0x08U
  #define GPIOE_SRE_SRE4_MASK           0x10U
  #define GPIOE_SRE_SRE5_MASK           0x20U
  #define GPIOE_SRE_SRE6_MASK           0x40U
  #define GPIOE_SRE_SRE7_MASK           0x80U
  #define GPIOE_SRE_SRE8_MASK           0x0100U
  #define GPIOE_SRE_SRE9_MASK           0x0200U
  #define GPIOE_SRE_SRE10_MASK          0x0400U
  #define GPIOE_SRE_SRE11_MASK          0x0800U
  #define GPIOE_SRE_SRE12_MASK          0x1000U
  #define GPIOE_SRE_SRE13_MASK          0x2000U
  #define GPIOE_SRE_SRE14_MASK          0x4000U
  #define GPIOE_SRE_SRE15_MASK          0x8000U
  #define GPIOE_SRE                     (*((volatile word *)0x0000E24D))


} GPIOE_PRPH;
/******************************************
*** Peripheral GPIOF
*******************************************/
typedef volatile struct {
  /*** GPIOF_PUR - GPIO Pull Resistor Enable Register; 0x0000E250 ***/
  union {
    word Word;
  } GPIOF_PUR_STR;

  #define GPIOF_PUR_PU0_MASK            0x01U
  #define GPIOF_PUR_PU1_MASK            0x02U
  #define GPIOF_PUR_PU2_MASK            0x04U
  #define GPIOF_PUR_PU3_MASK            0x08U
  #define GPIOF_PUR_PU4_MASK            0x10U
  #define GPIOF_PUR_PU5_MASK            0x20U
  #define GPIOF_PUR_PU6_MASK            0x40U
  #define GPIOF_PUR_PU7_MASK            0x80U
  #define GPIOF_PUR_PU8_MASK            0x0100U
  #define GPIOF_PUR_PU9_MASK            0x0200U
  #define GPIOF_PUR_PU10_MASK           0x0400U
  #define GPIOF_PUR_PU11_MASK           0x0800U
  #define GPIOF_PUR_PU12_MASK           0x1000U
  #define GPIOF_PUR_PU13_MASK           0x2000U
  #define GPIOF_PUR_PU14_MASK           0x4000U
  #define GPIOF_PUR_PU15_MASK           0x8000U
  #define GPIOF_PUR                     (*((volatile word *)0x0000E250))


  /*** GPIOF_DR - GPIO Data Register; 0x0000E251 ***/
  union {
    word Word;
  } GPIOF_DR_STR;

  #define GPIOF_DR_D0_MASK              0x01U
  #define GPIOF_DR_D1_MASK              0x02U
  #define GPIOF_DR_D2_MASK              0x04U
  #define GPIOF_DR_D3_MASK              0x08U
  #define GPIOF_DR_D4_MASK              0x10U
  #define GPIOF_DR_D5_MASK              0x20U
  #define GPIOF_DR_D6_MASK              0x40U
  #define GPIOF_DR_D7_MASK              0x80U
  #define GPIOF_DR_D8_MASK              0x0100U
  #define GPIOF_DR_D9_MASK              0x0200U
  #define GPIOF_DR_D10_MASK             0x0400U
  #define GPIOF_DR_D11_MASK             0x0800U
  #define GPIOF_DR_D12_MASK             0x1000U
  #define GPIOF_DR_D13_MASK             0x2000U
  #define GPIOF_DR_D14_MASK             0x4000U
  #define GPIOF_DR_D15_MASK             0x8000U
  #define GPIOF_DR                      (*((volatile word *)0x0000E251))


  /*** GPIOF_DDR - GPIO Data Direction Register; 0x0000E252 ***/
  union {
    word Word;
  } GPIOF_DDR_STR;

  #define GPIOF_DDR_DD0_MASK            0x01U
  #define GPIOF_DDR_DD1_MASK            0x02U
  #define GPIOF_DDR_DD2_MASK            0x04U
  #define GPIOF_DDR_DD3_MASK            0x08U
  #define GPIOF_DDR_DD4_MASK            0x10U
  #define GPIOF_DDR_DD5_MASK            0x20U
  #define GPIOF_DDR_DD6_MASK            0x40U
  #define GPIOF_DDR_DD7_MASK            0x80U
  #define GPIOF_DDR_DD8_MASK            0x0100U
  #define GPIOF_DDR_DD9_MASK            0x0200U
  #define GPIOF_DDR_DD10_MASK           0x0400U
  #define GPIOF_DDR_DD11_MASK           0x0800U
  #define GPIOF_DDR_DD12_MASK           0x1000U
  #define GPIOF_DDR_DD13_MASK           0x2000U
  #define GPIOF_DDR_DD14_MASK           0x4000U
  #define GPIOF_DDR_DD15_MASK           0x8000U
  #define GPIOF_DDR                     (*((volatile word *)0x0000E252))


  /*** GPIOF_PER - GPIO Peripheral Enable Register; 0x0000E253 ***/
  union {
    word Word;
  } GPIOF_PER_STR;

  #define GPIOF_PER_PE0_MASK            0x01U
  #define GPIOF_PER_PE1_MASK            0x02U
  #define GPIOF_PER_PE2_MASK            0x04U
  #define GPIOF_PER_PE3_MASK            0x08U
  #define GPIOF_PER_PE4_MASK            0x10U
  #define GPIOF_PER_PE5_MASK            0x20U
  #define GPIOF_PER_PE6_MASK            0x40U
  #define GPIOF_PER_PE7_MASK            0x80U
  #define GPIOF_PER_PE8_MASK            0x0100U
  #define GPIOF_PER_PE9_MASK            0x0200U
  #define GPIOF_PER_PE10_MASK           0x0400U
  #define GPIOF_PER_PE11_MASK           0x0800U
  #define GPIOF_PER_PE12_MASK           0x1000U
  #define GPIOF_PER_PE13_MASK           0x2000U
  #define GPIOF_PER_PE14_MASK           0x4000U
  #define GPIOF_PER_PE15_MASK           0x8000U
  #define GPIOF_PER                     (*((volatile word *)0x0000E253))


  /*** GPIOF_IAR - GPIO Interrupt Assert Register; 0x0000E254 ***/
  union {
    word Word;
  } GPIOF_IAR_STR;

  #define GPIOF_IAR_IA0_MASK            0x01U
  #define GPIOF_IAR_IA1_MASK            0x02U
  #define GPIOF_IAR_IA2_MASK            0x04U
  #define GPIOF_IAR_IA3_MASK            0x08U
  #define GPIOF_IAR_IA4_MASK            0x10U
  #define GPIOF_IAR_IA5_MASK            0x20U
  #define GPIOF_IAR_IA6_MASK            0x40U
  #define GPIOF_IAR_IA7_MASK            0x80U
  #define GPIOF_IAR_IA8_MASK            0x0100U
  #define GPIOF_IAR_IA9_MASK            0x0200U
  #define GPIOF_IAR_IA10_MASK           0x0400U
  #define GPIOF_IAR_IA11_MASK           0x0800U
  #define GPIOF_IAR_IA12_MASK           0x1000U
  #define GPIOF_IAR_IA13_MASK           0x2000U
  #define GPIOF_IAR_IA14_MASK           0x4000U
  #define GPIOF_IAR_IA15_MASK           0x8000U
  #define GPIOF_IAR                     (*((volatile word *)0x0000E254))


  /*** GPIOF_IENR - GPIO Interrupt Enable Register; 0x0000E255 ***/
  union {
    word Word;
  } GPIOF_IENR_STR;

  #define GPIOF_IENR_IEN0_MASK          0x01U
  #define GPIOF_IENR_IEN1_MASK          0x02U
  #define GPIOF_IENR_IEN2_MASK          0x04U
  #define GPIOF_IENR_IEN3_MASK          0x08U
  #define GPIOF_IENR_IEN4_MASK          0x10U
  #define GPIOF_IENR_IEN5_MASK          0x20U
  #define GPIOF_IENR_IEN6_MASK          0x40U
  #define GPIOF_IENR_IEN7_MASK          0x80U
  #define GPIOF_IENR_IEN8_MASK          0x0100U
  #define GPIOF_IENR_IEN9_MASK          0x0200U
  #define GPIOF_IENR_IEN10_MASK         0x0400U
  #define GPIOF_IENR_IEN11_MASK         0x0800U
  #define GPIOF_IENR_IEN12_MASK         0x1000U
  #define GPIOF_IENR_IEN13_MASK         0x2000U
  #define GPIOF_IENR_IEN14_MASK         0x4000U
  #define GPIOF_IENR_IEN15_MASK         0x8000U
  #define GPIOF_IENR                    (*((volatile word *)0x0000E255))


  /*** GPIOF_IPOLR - GPIO Interrupt Polarity Register; 0x0000E256 ***/
  union {
    word Word;
  } GPIOF_IPOLR_STR;

  #define GPIOF_IPOLR_IPOL0_MASK        0x01U
  #define GPIOF_IPOLR_IPOL1_MASK        0x02U
  #define GPIOF_IPOLR_IPOL2_MASK        0x04U
  #define GPIOF_IPOLR_IPOL3_MASK        0x08U
  #define GPIOF_IPOLR_IPOL4_MASK        0x10U
  #define GPIOF_IPOLR_IPOL5_MASK        0x20U
  #define GPIOF_IPOLR_IPOL6_MASK        0x40U
  #define GPIOF_IPOLR_IPOL7_MASK        0x80U
  #define GPIOF_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOF_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOF_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOF_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOF_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOF_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOF_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOF_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOF_IPOLR                   (*((volatile word *)0x0000E256))


  /*** GPIOF_IPR - GPIO Interrupt Pending Register; 0x0000E257 ***/
  union {
    word Word;
  } GPIOF_IPR_STR;

  #define GPIOF_IPR_IP0_MASK            0x01U
  #define GPIOF_IPR_IP1_MASK            0x02U
  #define GPIOF_IPR_IP2_MASK            0x04U
  #define GPIOF_IPR_IP3_MASK            0x08U
  #define GPIOF_IPR_IP4_MASK            0x10U
  #define GPIOF_IPR_IP5_MASK            0x20U
  #define GPIOF_IPR_IP6_MASK            0x40U
  #define GPIOF_IPR_IP7_MASK            0x80U
  #define GPIOF_IPR_IP8_MASK            0x0100U
  #define GPIOF_IPR_IP9_MASK            0x0200U
  #define GPIOF_IPR_IP10_MASK           0x0400U
  #define GPIOF_IPR_IP11_MASK           0x0800U
  #define GPIOF_IPR_IP12_MASK           0x1000U
  #define GPIOF_IPR_IP13_MASK           0x2000U
  #define GPIOF_IPR_IP14_MASK           0x4000U
  #define GPIOF_IPR_IP15_MASK           0x8000U
  #define GPIOF_IPR                     (*((volatile word *)0x0000E257))


  /*** GPIOF_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E258 ***/
  union {
    word Word;
  } GPIOF_IESR_STR;

  #define GPIOF_IESR_IES0_MASK          0x01U
  #define GPIOF_IESR_IES1_MASK          0x02U
  #define GPIOF_IESR_IES2_MASK          0x04U
  #define GPIOF_IESR_IES3_MASK          0x08U
  #define GPIOF_IESR_IES4_MASK          0x10U
  #define GPIOF_IESR_IES5_MASK          0x20U
  #define GPIOF_IESR_IES6_MASK          0x40U
  #define GPIOF_IESR_IES7_MASK          0x80U
  #define GPIOF_IESR_IES8_MASK          0x0100U
  #define GPIOF_IESR_IES9_MASK          0x0200U
  #define GPIOF_IESR_IES10_MASK         0x0400U
  #define GPIOF_IESR_IES11_MASK         0x0800U
  #define GPIOF_IESR_IES12_MASK         0x1000U
  #define GPIOF_IESR_IES13_MASK         0x2000U
  #define GPIOF_IESR_IES14_MASK         0x4000U
  #define GPIOF_IESR_IES15_MASK         0x8000U
  #define GPIOF_IESR                    (*((volatile word *)0x0000E258))


  /*** GPIOF_PPMODE - GPIO Push-Pull Mode Register; 0x0000E259 ***/
  union {
    word Word;
  } GPIOF_PPMODE_STR;

  #define GPIOF_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOF_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOF_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOF_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOF_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOF_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOF_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOF_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOF_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOF_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOF_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOF_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOF_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOF_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOF_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOF_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOF_PPMODE                  (*((volatile word *)0x0000E259))


  /*** GPIOF_RAWDATA - GPIO Raw Data Register; 0x0000E25A ***/
  union {
    word Word;
  } GPIOF_RAWDATA_STR;

  #define GPIOF_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOF_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOF_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOF_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOF_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOF_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOF_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOF_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOF_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOF_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOF_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOF_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOF_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOF_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOF_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOF_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOF_RAWDATA                 (*((volatile word *)0x0000E25A))


  /*** GPIOF_DRIVE - GPIO Drive Strength Control Register; 0x0000E25B ***/
  union {
    word Word;
  } GPIOF_DRIVE_STR;

  #define GPIOF_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOF_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOF_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOF_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOF_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOF_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOF_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOF_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOF_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOF_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOF_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOF_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOF_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOF_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOF_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOF_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOF_DRIVE                   (*((volatile word *)0x0000E25B))


  /*** GPIOF_PUS - GPIO Pull Resistor Type Select; 0x0000E25C ***/
  union {
    word Word;
  } GPIOF_PUS_STR;

  #define GPIOF_PUS_PUS0_MASK           0x01U
  #define GPIOF_PUS_PUS1_MASK           0x02U
  #define GPIOF_PUS_PUS2_MASK           0x04U
  #define GPIOF_PUS_PUS3_MASK           0x08U
  #define GPIOF_PUS_PUS4_MASK           0x10U
  #define GPIOF_PUS_PUS5_MASK           0x20U
  #define GPIOF_PUS_PUS6_MASK           0x40U
  #define GPIOF_PUS_PUS7_MASK           0x80U
  #define GPIOF_PUS_PUS8_MASK           0x0100U
  #define GPIOF_PUS_PUS9_MASK           0x0200U
  #define GPIOF_PUS_PUS10_MASK          0x0400U
  #define GPIOF_PUS_PUS11_MASK          0x0800U
  #define GPIOF_PUS_PUS12_MASK          0x1000U
  #define GPIOF_PUS_PUS13_MASK          0x2000U
  #define GPIOF_PUS_PUS14_MASK          0x4000U
  #define GPIOF_PUS_PUS15_MASK          0x8000U
  #define GPIOF_PUS                     (*((volatile word *)0x0000E25C))


  /*** GPIOF_SRE - Slew Rate Control Register; 0x0000E25D ***/
  union {
    word Word;
  } GPIOF_SRE_STR;

  #define GPIOF_SRE_SRE0_MASK           0x01U
  #define GPIOF_SRE_SRE1_MASK           0x02U
  #define GPIOF_SRE_SRE2_MASK           0x04U
  #define GPIOF_SRE_SRE3_MASK           0x08U
  #define GPIOF_SRE_SRE4_MASK           0x10U
  #define GPIOF_SRE_SRE5_MASK           0x20U
  #define GPIOF_SRE_SRE6_MASK           0x40U
  #define GPIOF_SRE_SRE7_MASK           0x80U
  #define GPIOF_SRE_SRE8_MASK           0x0100U
  #define GPIOF_SRE_SRE9_MASK           0x0200U
  #define GPIOF_SRE_SRE10_MASK          0x0400U
  #define GPIOF_SRE_SRE11_MASK          0x0800U
  #define GPIOF_SRE_SRE12_MASK          0x1000U
  #define GPIOF_SRE_SRE13_MASK          0x2000U
  #define GPIOF_SRE_SRE14_MASK          0x4000U
  #define GPIOF_SRE_SRE15_MASK          0x8000U
  #define GPIOF_SRE                     (*((volatile word *)0x0000E25D))


} GPIOF_PRPH;
/******************************************
*** Peripheral GPIOG
*******************************************/
typedef volatile struct {
  /*** GPIOG_PUR - GPIO Pull Resistor Enable Register; 0x0000E260 ***/
  union {
    word Word;
  } GPIOG_PUR_STR;

  #define GPIOG_PUR_PU0_MASK            0x01U
  #define GPIOG_PUR_PU1_MASK            0x02U
  #define GPIOG_PUR_PU2_MASK            0x04U
  #define GPIOG_PUR_PU3_MASK            0x08U
  #define GPIOG_PUR_PU4_MASK            0x10U
  #define GPIOG_PUR_PU5_MASK            0x20U
  #define GPIOG_PUR_PU6_MASK            0x40U
  #define GPIOG_PUR_PU7_MASK            0x80U
  #define GPIOG_PUR_PU8_MASK            0x0100U
  #define GPIOG_PUR_PU9_MASK            0x0200U
  #define GPIOG_PUR_PU10_MASK           0x0400U
  #define GPIOG_PUR_PU11_MASK           0x0800U
  #define GPIOG_PUR_PU12_MASK           0x1000U
  #define GPIOG_PUR_PU13_MASK           0x2000U
  #define GPIOG_PUR_PU14_MASK           0x4000U
  #define GPIOG_PUR_PU15_MASK           0x8000U
  #define GPIOG_PUR                     (*((volatile word *)0x0000E260))


  /*** GPIOG_DR - GPIO Data Register; 0x0000E261 ***/
  union {
    word Word;
  } GPIOG_DR_STR;

  #define GPIOG_DR_D0_MASK              0x01U
  #define GPIOG_DR_D1_MASK              0x02U
  #define GPIOG_DR_D2_MASK              0x04U
  #define GPIOG_DR_D3_MASK              0x08U
  #define GPIOG_DR_D4_MASK              0x10U
  #define GPIOG_DR_D5_MASK              0x20U
  #define GPIOG_DR_D6_MASK              0x40U
  #define GPIOG_DR_D7_MASK              0x80U
  #define GPIOG_DR_D8_MASK              0x0100U
  #define GPIOG_DR_D9_MASK              0x0200U
  #define GPIOG_DR_D10_MASK             0x0400U
  #define GPIOG_DR_D11_MASK             0x0800U
  #define GPIOG_DR_D12_MASK             0x1000U
  #define GPIOG_DR_D13_MASK             0x2000U
  #define GPIOG_DR_D14_MASK             0x4000U
  #define GPIOG_DR_D15_MASK             0x8000U
  #define GPIOG_DR                      (*((volatile word *)0x0000E261))


  /*** GPIOG_DDR - GPIO Data Direction Register; 0x0000E262 ***/
  union {
    word Word;
  } GPIOG_DDR_STR;

  #define GPIOG_DDR_DD0_MASK            0x01U
  #define GPIOG_DDR_DD1_MASK            0x02U
  #define GPIOG_DDR_DD2_MASK            0x04U
  #define GPIOG_DDR_DD3_MASK            0x08U
  #define GPIOG_DDR_DD4_MASK            0x10U
  #define GPIOG_DDR_DD5_MASK            0x20U
  #define GPIOG_DDR_DD6_MASK            0x40U
  #define GPIOG_DDR_DD7_MASK            0x80U
  #define GPIOG_DDR_DD8_MASK            0x0100U
  #define GPIOG_DDR_DD9_MASK            0x0200U
  #define GPIOG_DDR_DD10_MASK           0x0400U
  #define GPIOG_DDR_DD11_MASK           0x0800U
  #define GPIOG_DDR_DD12_MASK           0x1000U
  #define GPIOG_DDR_DD13_MASK           0x2000U
  #define GPIOG_DDR_DD14_MASK           0x4000U
  #define GPIOG_DDR_DD15_MASK           0x8000U
  #define GPIOG_DDR                     (*((volatile word *)0x0000E262))


  /*** GPIOG_PER - GPIO Peripheral Enable Register; 0x0000E263 ***/
  union {
    word Word;
  } GPIOG_PER_STR;

  #define GPIOG_PER_PE0_MASK            0x01U
  #define GPIOG_PER_PE1_MASK            0x02U
  #define GPIOG_PER_PE2_MASK            0x04U
  #define GPIOG_PER_PE3_MASK            0x08U
  #define GPIOG_PER_PE4_MASK            0x10U
  #define GPIOG_PER_PE5_MASK            0x20U
  #define GPIOG_PER_PE6_MASK            0x40U
  #define GPIOG_PER_PE7_MASK            0x80U
  #define GPIOG_PER_PE8_MASK            0x0100U
  #define GPIOG_PER_PE9_MASK            0x0200U
  #define GPIOG_PER_PE10_MASK           0x0400U
  #define GPIOG_PER_PE11_MASK           0x0800U
  #define GPIOG_PER_PE12_MASK           0x1000U
  #define GPIOG_PER_PE13_MASK           0x2000U
  #define GPIOG_PER_PE14_MASK           0x4000U
  #define GPIOG_PER_PE15_MASK           0x8000U
  #define GPIOG_PER                     (*((volatile word *)0x0000E263))


  /*** GPIOG_IAR - GPIO Interrupt Assert Register; 0x0000E264 ***/
  union {
    word Word;
  } GPIOG_IAR_STR;

  #define GPIOG_IAR_IA0_MASK            0x01U
  #define GPIOG_IAR_IA1_MASK            0x02U
  #define GPIOG_IAR_IA2_MASK            0x04U
  #define GPIOG_IAR_IA3_MASK            0x08U
  #define GPIOG_IAR_IA4_MASK            0x10U
  #define GPIOG_IAR_IA5_MASK            0x20U
  #define GPIOG_IAR_IA6_MASK            0x40U
  #define GPIOG_IAR_IA7_MASK            0x80U
  #define GPIOG_IAR_IA8_MASK            0x0100U
  #define GPIOG_IAR_IA9_MASK            0x0200U
  #define GPIOG_IAR_IA10_MASK           0x0400U
  #define GPIOG_IAR_IA11_MASK           0x0800U
  #define GPIOG_IAR_IA12_MASK           0x1000U
  #define GPIOG_IAR_IA13_MASK           0x2000U
  #define GPIOG_IAR_IA14_MASK           0x4000U
  #define GPIOG_IAR_IA15_MASK           0x8000U
  #define GPIOG_IAR                     (*((volatile word *)0x0000E264))


  /*** GPIOG_IENR - GPIO Interrupt Enable Register; 0x0000E265 ***/
  union {
    word Word;
  } GPIOG_IENR_STR;

  #define GPIOG_IENR_IEN0_MASK          0x01U
  #define GPIOG_IENR_IEN1_MASK          0x02U
  #define GPIOG_IENR_IEN2_MASK          0x04U
  #define GPIOG_IENR_IEN3_MASK          0x08U
  #define GPIOG_IENR_IEN4_MASK          0x10U
  #define GPIOG_IENR_IEN5_MASK          0x20U
  #define GPIOG_IENR_IEN6_MASK          0x40U
  #define GPIOG_IENR_IEN7_MASK          0x80U
  #define GPIOG_IENR_IEN8_MASK          0x0100U
  #define GPIOG_IENR_IEN9_MASK          0x0200U
  #define GPIOG_IENR_IEN10_MASK         0x0400U
  #define GPIOG_IENR_IEN11_MASK         0x0800U
  #define GPIOG_IENR_IEN12_MASK         0x1000U
  #define GPIOG_IENR_IEN13_MASK         0x2000U
  #define GPIOG_IENR_IEN14_MASK         0x4000U
  #define GPIOG_IENR_IEN15_MASK         0x8000U
  #define GPIOG_IENR                    (*((volatile word *)0x0000E265))


  /*** GPIOG_IPOLR - GPIO Interrupt Polarity Register; 0x0000E266 ***/
  union {
    word Word;
  } GPIOG_IPOLR_STR;

  #define GPIOG_IPOLR_IPOL0_MASK        0x01U
  #define GPIOG_IPOLR_IPOL1_MASK        0x02U
  #define GPIOG_IPOLR_IPOL2_MASK        0x04U
  #define GPIOG_IPOLR_IPOL3_MASK        0x08U
  #define GPIOG_IPOLR_IPOL4_MASK        0x10U
  #define GPIOG_IPOLR_IPOL5_MASK        0x20U
  #define GPIOG_IPOLR_IPOL6_MASK        0x40U
  #define GPIOG_IPOLR_IPOL7_MASK        0x80U
  #define GPIOG_IPOLR_IPOL8_MASK        0x0100U
  #define GPIOG_IPOLR_IPOL9_MASK        0x0200U
  #define GPIOG_IPOLR_IPOL10_MASK       0x0400U
  #define GPIOG_IPOLR_IPOL11_MASK       0x0800U
  #define GPIOG_IPOLR_IPOL12_MASK       0x1000U
  #define GPIOG_IPOLR_IPOL13_MASK       0x2000U
  #define GPIOG_IPOLR_IPOL14_MASK       0x4000U
  #define GPIOG_IPOLR_IPOL15_MASK       0x8000U
  #define GPIOG_IPOLR                   (*((volatile word *)0x0000E266))


  /*** GPIOG_IPR - GPIO Interrupt Pending Register; 0x0000E267 ***/
  union {
    word Word;
  } GPIOG_IPR_STR;

  #define GPIOG_IPR_IP0_MASK            0x01U
  #define GPIOG_IPR_IP1_MASK            0x02U
  #define GPIOG_IPR_IP2_MASK            0x04U
  #define GPIOG_IPR_IP3_MASK            0x08U
  #define GPIOG_IPR_IP4_MASK            0x10U
  #define GPIOG_IPR_IP5_MASK            0x20U
  #define GPIOG_IPR_IP6_MASK            0x40U
  #define GPIOG_IPR_IP7_MASK            0x80U
  #define GPIOG_IPR_IP8_MASK            0x0100U
  #define GPIOG_IPR_IP9_MASK            0x0200U
  #define GPIOG_IPR_IP10_MASK           0x0400U
  #define GPIOG_IPR_IP11_MASK           0x0800U
  #define GPIOG_IPR_IP12_MASK           0x1000U
  #define GPIOG_IPR_IP13_MASK           0x2000U
  #define GPIOG_IPR_IP14_MASK           0x4000U
  #define GPIOG_IPR_IP15_MASK           0x8000U
  #define GPIOG_IPR                     (*((volatile word *)0x0000E267))


  /*** GPIOG_IESR - GPIO Interrupt Edge Sensitive Register; 0x0000E268 ***/
  union {
    word Word;
  } GPIOG_IESR_STR;

  #define GPIOG_IESR_IES0_MASK          0x01U
  #define GPIOG_IESR_IES1_MASK          0x02U
  #define GPIOG_IESR_IES2_MASK          0x04U
  #define GPIOG_IESR_IES3_MASK          0x08U
  #define GPIOG_IESR_IES4_MASK          0x10U
  #define GPIOG_IESR_IES5_MASK          0x20U
  #define GPIOG_IESR_IES6_MASK          0x40U
  #define GPIOG_IESR_IES7_MASK          0x80U
  #define GPIOG_IESR_IES8_MASK          0x0100U
  #define GPIOG_IESR_IES9_MASK          0x0200U
  #define GPIOG_IESR_IES10_MASK         0x0400U
  #define GPIOG_IESR_IES11_MASK         0x0800U
  #define GPIOG_IESR_IES12_MASK         0x1000U
  #define GPIOG_IESR_IES13_MASK         0x2000U
  #define GPIOG_IESR_IES14_MASK         0x4000U
  #define GPIOG_IESR_IES15_MASK         0x8000U
  #define GPIOG_IESR                    (*((volatile word *)0x0000E268))


  /*** GPIOG_PPMODE - GPIO Push-Pull Mode Register; 0x0000E269 ***/
  union {
    word Word;
  } GPIOG_PPMODE_STR;

  #define GPIOG_PPMODE_PPMODE0_MASK     0x01U
  #define GPIOG_PPMODE_PPMODE1_MASK     0x02U
  #define GPIOG_PPMODE_PPMODE2_MASK     0x04U
  #define GPIOG_PPMODE_PPMODE3_MASK     0x08U
  #define GPIOG_PPMODE_PPMODE4_MASK     0x10U
  #define GPIOG_PPMODE_PPMODE5_MASK     0x20U
  #define GPIOG_PPMODE_PPMODE6_MASK     0x40U
  #define GPIOG_PPMODE_PPMODE7_MASK     0x80U
  #define GPIOG_PPMODE_PPMODE8_MASK     0x0100U
  #define GPIOG_PPMODE_PPMODE9_MASK     0x0200U
  #define GPIOG_PPMODE_PPMODE10_MASK    0x0400U
  #define GPIOG_PPMODE_PPMODE11_MASK    0x0800U
  #define GPIOG_PPMODE_PPMODE12_MASK    0x1000U
  #define GPIOG_PPMODE_PPMODE13_MASK    0x2000U
  #define GPIOG_PPMODE_PPMODE14_MASK    0x4000U
  #define GPIOG_PPMODE_PPMODE15_MASK    0x8000U
  #define GPIOG_PPMODE                  (*((volatile word *)0x0000E269))


  /*** GPIOG_RAWDATA - GPIO Raw Data Register; 0x0000E26A ***/
  union {
    word Word;
  } GPIOG_RAWDATA_STR;

  #define GPIOG_RAWDATA_RAW_DATA0_MASK  0x01U
  #define GPIOG_RAWDATA_RAW_DATA1_MASK  0x02U
  #define GPIOG_RAWDATA_RAW_DATA2_MASK  0x04U
  #define GPIOG_RAWDATA_RAW_DATA3_MASK  0x08U
  #define GPIOG_RAWDATA_RAW_DATA4_MASK  0x10U
  #define GPIOG_RAWDATA_RAW_DATA5_MASK  0x20U
  #define GPIOG_RAWDATA_RAW_DATA6_MASK  0x40U
  #define GPIOG_RAWDATA_RAW_DATA7_MASK  0x80U
  #define GPIOG_RAWDATA_RAW_DATA8_MASK  0x0100U
  #define GPIOG_RAWDATA_RAW_DATA9_MASK  0x0200U
  #define GPIOG_RAWDATA_RAW_DATA10_MASK 0x0400U
  #define GPIOG_RAWDATA_RAW_DATA11_MASK 0x0800U
  #define GPIOG_RAWDATA_RAW_DATA12_MASK 0x1000U
  #define GPIOG_RAWDATA_RAW_DATA13_MASK 0x2000U
  #define GPIOG_RAWDATA_RAW_DATA14_MASK 0x4000U
  #define GPIOG_RAWDATA_RAW_DATA15_MASK 0x8000U
  #define GPIOG_RAWDATA                 (*((volatile word *)0x0000E26A))


  /*** GPIOG_DRIVE - GPIO Drive Strength Control Register; 0x0000E26B ***/
  union {
    word Word;
  } GPIOG_DRIVE_STR;

  #define GPIOG_DRIVE_DRIVE0_MASK       0x01U
  #define GPIOG_DRIVE_DRIVE1_MASK       0x02U
  #define GPIOG_DRIVE_DRIVE2_MASK       0x04U
  #define GPIOG_DRIVE_DRIVE3_MASK       0x08U
  #define GPIOG_DRIVE_DRIVE4_MASK       0x10U
  #define GPIOG_DRIVE_DRIVE5_MASK       0x20U
  #define GPIOG_DRIVE_DRIVE6_MASK       0x40U
  #define GPIOG_DRIVE_DRIVE7_MASK       0x80U
  #define GPIOG_DRIVE_DRIVE8_MASK       0x0100U
  #define GPIOG_DRIVE_DRIVE9_MASK       0x0200U
  #define GPIOG_DRIVE_DRIVE10_MASK      0x0400U
  #define GPIOG_DRIVE_DRIVE11_MASK      0x0800U
  #define GPIOG_DRIVE_DRIVE12_MASK      0x1000U
  #define GPIOG_DRIVE_DRIVE13_MASK      0x2000U
  #define GPIOG_DRIVE_DRIVE14_MASK      0x4000U
  #define GPIOG_DRIVE_DRIVE15_MASK      0x8000U
  #define GPIOG_DRIVE                   (*((volatile word *)0x0000E26B))


  /*** GPIOG_PUS - GPIO Pull Resistor Type Select; 0x0000E26C ***/
  union {
    word Word;
  } GPIOG_PUS_STR;

  #define GPIOG_PUS_PUS0_MASK           0x01U
  #define GPIOG_PUS_PUS1_MASK           0x02U
  #define GPIOG_PUS_PUS2_MASK           0x04U
  #define GPIOG_PUS_PUS3_MASK           0x08U
  #define GPIOG_PUS_PUS4_MASK           0x10U
  #define GPIOG_PUS_PUS5_MASK           0x20U
  #define GPIOG_PUS_PUS6_MASK           0x40U
  #define GPIOG_PUS_PUS7_MASK           0x80U
  #define GPIOG_PUS_PUS8_MASK           0x0100U
  #define GPIOG_PUS_PUS9_MASK           0x0200U
  #define GPIOG_PUS_PUS10_MASK          0x0400U
  #define GPIOG_PUS_PUS11_MASK          0x0800U
  #define GPIOG_PUS_PUS12_MASK          0x1000U
  #define GPIOG_PUS_PUS13_MASK          0x2000U
  #define GPIOG_PUS_PUS14_MASK          0x4000U
  #define GPIOG_PUS_PUS15_MASK          0x8000U
  #define GPIOG_PUS                     (*((volatile word *)0x0000E26C))


  /*** GPIOG_SRE - Slew Rate Control Register; 0x0000E26D ***/
  union {
    word Word;
  } GPIOG_SRE_STR;

  #define GPIOG_SRE_SRE0_MASK           0x01U
  #define GPIOG_SRE_SRE1_MASK           0x02U
  #define GPIOG_SRE_SRE2_MASK           0x04U
  #define GPIOG_SRE_SRE3_MASK           0x08U
  #define GPIOG_SRE_SRE4_MASK           0x10U
  #define GPIOG_SRE_SRE5_MASK           0x20U
  #define GPIOG_SRE_SRE6_MASK           0x40U
  #define GPIOG_SRE_SRE7_MASK           0x80U
  #define GPIOG_SRE_SRE8_MASK           0x0100U
  #define GPIOG_SRE_SRE9_MASK           0x0200U
  #define GPIOG_SRE_SRE10_MASK          0x0400U
  #define GPIOG_SRE_SRE11_MASK          0x0800U
  #define GPIOG_SRE_SRE12_MASK          0x1000U
  #define GPIOG_SRE_SRE13_MASK          0x2000U
  #define GPIOG_SRE_SRE14_MASK          0x4000U
  #define GPIOG_SRE_SRE15_MASK          0x8000U
  #define GPIOG_SRE                     (*((volatile word *)0x0000E26D))


} GPIOG_PRPH;
/******************************************
*** Peripheral PMC
*******************************************/
typedef volatile struct {
  /*** PMC_CTRL - Control Register; 0x0000E2A0 ***/
  union {
    word Word;
  } PMC_CTRL_STR;

  #define PMC_CTRL_LV22IE_MASK          0x01U
  #define PMC_CTRL_LV27IE_MASK          0x02U
  #define PMC_CTRL_HV22IE_MASK          0x04U
  #define PMC_CTRL_HV27IE_MASK          0x08U
  #define PMC_CTRL_VRBEN_MASK           0x80U
  #define PMC_CTRL_TRIM0_MASK           0x1000U
  #define PMC_CTRL_TRIM1_MASK           0x2000U
  #define PMC_CTRL_TRIM2_MASK           0x4000U
  #define PMC_CTRL_TRIM3_MASK           0x8000U
  #define PMC_CTRL_TRIM_MASK            0xF000U
  #define PMC_CTRL_TRIM_BITNUM          0x0CU
  #define PMC_CTRL                      (*((volatile word *)0x0000E2A0))


  /*** PMC_STS - Status Register; 0x0000E2A1 ***/
  union {
    word Word;
  } PMC_STS_STR;

  #define PMC_STS_LV22F_MASK            0x01U
  #define PMC_STS_LV27F_MASK            0x02U
  #define PMC_STS_SLV22F_MASK           0x04U
  #define PMC_STS_SLV27F_MASK           0x08U
  #define PMC_STS_LVI_MASK              0x10U
  #define PMC_STS_SR27_MASK             0x20U
  #define PMC_STS                       (*((volatile word *)0x0000E2A1))


} PMC_PRPH;
/******************************************
*** Peripheral OCCS
*******************************************/
typedef volatile struct {
  /*** OCCS_CTRL - PLL Control Register; 0x0000E2B0 ***/
  union {
    word Word;
  } OCCS_CTRL_STR;

  #define OCCS_CTRL_ZSRC_MASK           0x01U
  #define OCCS_CTRL_PRECS0_MASK         0x04U
  #define OCCS_CTRL_PRECS1_MASK         0x08U
  #define OCCS_CTRL_PLLPD_MASK          0x10U
  #define OCCS_CTRL_LCKON_MASK          0x80U
  #define OCCS_CTRL_LOCIE_MASK          0x0800U
  #define OCCS_CTRL_PLLIE00_MASK        0x1000U
  #define OCCS_CTRL_PLLIE01_MASK        0x2000U
  #define OCCS_CTRL_PLLIE10_MASK        0x4000U
  #define OCCS_CTRL_PLLIE11_MASK        0x8000U
  #define OCCS_CTRL_PRECS_MASK          0x0CU
  #define OCCS_CTRL_PRECS_BITNUM        0x02U
  #define OCCS_CTRL_PLLIE0_MASK         0x3000U
  #define OCCS_CTRL_PLLIE0_BITNUM       0x0CU
  #define OCCS_CTRL_PLLIE1_MASK         0xC000U
  #define OCCS_CTRL_PLLIE1_BITNUM       0x0EU
  #define OCCS_CTRL                     (*((volatile word *)0x0000E2B0))


  /*** OCCS_DIVBY - PLL Divide-By Register; 0x0000E2B1 ***/
  union {
    word Word;
  } OCCS_DIVBY_STR;

  #define OCCS_DIVBY_PLLDB0_MASK        0x01U
  #define OCCS_DIVBY_PLLDB1_MASK        0x02U
  #define OCCS_DIVBY_PLLDB2_MASK        0x04U
  #define OCCS_DIVBY_PLLDB3_MASK        0x08U
  #define OCCS_DIVBY_PLLDB4_MASK        0x10U
  #define OCCS_DIVBY_PLLDB5_MASK        0x20U
  #define OCCS_DIVBY_COD0_MASK          0x0100U
  #define OCCS_DIVBY_COD1_MASK          0x0200U
  #define OCCS_DIVBY_COD2_MASK          0x0400U
  #define OCCS_DIVBY_COD3_MASK          0x0800U
  #define OCCS_DIVBY_LORTP0_MASK        0x1000U
  #define OCCS_DIVBY_LORTP1_MASK        0x2000U
  #define OCCS_DIVBY_LORTP2_MASK        0x4000U
  #define OCCS_DIVBY_LORTP3_MASK        0x8000U
  #define OCCS_DIVBY_PLLDB_MASK         0x3FU
  #define OCCS_DIVBY_PLLDB_BITNUM       0x00U
  #define OCCS_DIVBY_COD_MASK           0x0F00U
  #define OCCS_DIVBY_COD_BITNUM         0x08U
  #define OCCS_DIVBY_LORTP_MASK         0xF000U
  #define OCCS_DIVBY_LORTP_BITNUM       0x0CU
  #define OCCS_DIVBY                    (*((volatile word *)0x0000E2B1))


  /*** OCCS_STAT - OCCS Status Register; 0x0000E2B2 ***/
  union {
    word Word;
  } OCCS_STAT_STR;

  #define OCCS_STAT_ZSRCS0_MASK         0x01U
  #define OCCS_STAT_ZSRCS1_MASK         0x02U
  #define OCCS_STAT_PLLPDN_MASK         0x10U
  #define OCCS_STAT_LCK0_MASK           0x20U
  #define OCCS_STAT_LCK1_MASK           0x40U
  #define OCCS_STAT_OSC_OK_MASK         0x80U
  #define OCCS_STAT_MON_FAILURE_MASK    0x0100U
  #define OCCS_STAT_LOCI_MASK           0x2000U
  #define OCCS_STAT_LOLI0_MASK          0x4000U
  #define OCCS_STAT_LOLI1_MASK          0x8000U
  #define OCCS_STAT_ZSRCS_MASK          0x03U
  #define OCCS_STAT_ZSRCS_BITNUM        0x00U
  #define OCCS_STAT                     (*((volatile word *)0x0000E2B2))


  word Reserved0[1];                   /* Reserved (unused) registers */

  /*** OCCS_OSCTL1 - Oscillator Control Register 1; 0x0000E2B4 ***/
  union {
    word Word;
  } OCCS_OSCTL1_STR;

  #define OCCS_OSCTL1_FREQ_TRIM8M0_MASK 0x01U
  #define OCCS_OSCTL1_FREQ_TRIM8M1_MASK 0x02U
  #define OCCS_OSCTL1_FREQ_TRIM8M2_MASK 0x04U
  #define OCCS_OSCTL1_FREQ_TRIM8M3_MASK 0x08U
  #define OCCS_OSCTL1_FREQ_TRIM8M4_MASK 0x10U
  #define OCCS_OSCTL1_FREQ_TRIM8M5_MASK 0x20U
  #define OCCS_OSCTL1_FREQ_TRIM8M6_MASK 0x40U
  #define OCCS_OSCTL1_FREQ_TRIM8M7_MASK 0x80U
  #define OCCS_OSCTL1_FREQ_TRIM8M8_MASK 0x0100U
  #define OCCS_OSCTL1_FREQ_TRIM8M9_MASK 0x0200U
  #define OCCS_OSCTL1_EXT_SEL_MASK      0x0400U
  #define OCCS_OSCTL1_OSC_DIV2_MASK     0x0800U
  #define OCCS_OSCTL1_CLK_MODE_MASK     0x1000U
  #define OCCS_OSCTL1_COHL_MASK         0x2000U
  #define OCCS_OSCTL1_ROSB_MASK         0x4000U
  #define OCCS_OSCTL1_ROPD_MASK         0x8000U
  #define OCCS_OSCTL1_FREQ_TRIM8M_MASK  0x03FFU
  #define OCCS_OSCTL1_FREQ_TRIM8M_BITNUM 0x00U
  #define OCCS_OSCTL1                   (*((volatile word *)0x0000E2B4))


  /*** OCCS_OSCTL2 - Oscillator Control Register 2; 0x0000E2B5 ***/
  union {
    word Word;
  } OCCS_OSCTL2_STR;

  #define OCCS_OSCTL2_FREQ_TRIM32K0_MASK 0x01U
  #define OCCS_OSCTL2_FREQ_TRIM32K1_MASK 0x02U
  #define OCCS_OSCTL2_FREQ_TRIM32K2_MASK 0x04U
  #define OCCS_OSCTL2_FREQ_TRIM32K3_MASK 0x08U
  #define OCCS_OSCTL2_FREQ_TRIM32K4_MASK 0x10U
  #define OCCS_OSCTL2_FREQ_TRIM32K5_MASK 0x20U
  #define OCCS_OSCTL2_FREQ_TRIM32K6_MASK 0x40U
  #define OCCS_OSCTL2_FREQ_TRIM32K7_MASK 0x80U
  #define OCCS_OSCTL2_FREQ_TRIM32K8_MASK 0x0100U
  #define OCCS_OSCTL2_MON_ENABLE_MASK   0x0200U
  #define OCCS_OSCTL2_TEMP_TRIM8M0_MASK 0x0400U
  #define OCCS_OSCTL2_TEMP_TRIM8M1_MASK 0x0800U
  #define OCCS_OSCTL2_TEMP_TRIM8M2_MASK 0x1000U
  #define OCCS_OSCTL2_TEMP_TRIM8M3_MASK 0x2000U
  #define OCCS_OSCTL2_COPD_MASK         0x4000U
  #define OCCS_OSCTL2_ROPD32K_MASK      0x8000U
  #define OCCS_OSCTL2_FREQ_TRIM32K_MASK 0x01FFU
  #define OCCS_OSCTL2_FREQ_TRIM32K_BITNUM 0x00U
  #define OCCS_OSCTL2_TEMP_TRIM8M_MASK  0x3C00U
  #define OCCS_OSCTL2_TEMP_TRIM8M_BITNUM 0x0AU
  #define OCCS_OSCTL2                   (*((volatile word *)0x0000E2B5))


  /*** OCCS_CLKCHKR - External Clock Check Reference; 0x0000E2B6 ***/
  union {
    word Word;
  } OCCS_CLKCHKR_STR;

  #define OCCS_CLKCHKR_REF_CNT0_MASK    0x01U
  #define OCCS_CLKCHKR_REF_CNT1_MASK    0x02U
  #define OCCS_CLKCHKR_REF_CNT2_MASK    0x04U
  #define OCCS_CLKCHKR_REF_CNT3_MASK    0x08U
  #define OCCS_CLKCHKR_REF_CNT4_MASK    0x10U
  #define OCCS_CLKCHKR_REF_CNT5_MASK    0x20U
  #define OCCS_CLKCHKR_REF_CNT6_MASK    0x40U
  #define OCCS_CLKCHKR_CHK_ENA_MASK     0x8000U
  #define OCCS_CLKCHKR_REF_CNT_MASK     0x7FU
  #define OCCS_CLKCHKR_REF_CNT_BITNUM   0x00U
  #define OCCS_CLKCHKR                  (*((volatile word *)0x0000E2B6))


  /*** OCCS_CLKCHKT - External Clock Check Target; 0x0000E2B7 ***/
  union {
    word Word;
  } OCCS_CLKCHKT_STR;

  #define OCCS_CLKCHKT_TARGET_CNT0_MASK 0x01U
  #define OCCS_CLKCHKT_TARGET_CNT1_MASK 0x02U
  #define OCCS_CLKCHKT_TARGET_CNT2_MASK 0x04U
  #define OCCS_CLKCHKT_TARGET_CNT3_MASK 0x08U
  #define OCCS_CLKCHKT_TARGET_CNT4_MASK 0x10U
  #define OCCS_CLKCHKT_TARGET_CNT5_MASK 0x20U
  #define OCCS_CLKCHKT_TARGET_CNT6_MASK 0x40U
  #define OCCS_CLKCHKT_TARGET_CNT7_MASK 0x80U
  #define OCCS_CLKCHKT_TARGET_CNT8_MASK 0x0100U
  #define OCCS_CLKCHKT_TARGET_CNT9_MASK 0x0200U
  #define OCCS_CLKCHKT_TARGET_CNT10_MASK 0x0400U
  #define OCCS_CLKCHKT_TARGET_CNT_MASK  0x07FFU
  #define OCCS_CLKCHKT_TARGET_CNT_BITNUM 0x00U
  #define OCCS_CLKCHKT                  (*((volatile word *)0x0000E2B7))


  /*** OCCS_PROT - Protection Register; 0x0000E2B8 ***/
  union {
    word Word;
  } OCCS_PROT_STR;

  #define OCCS_PROT_PLLEP0_MASK         0x01U
  #define OCCS_PROT_PLLEP1_MASK         0x02U
  #define OCCS_PROT_OSCEP0_MASK         0x04U
  #define OCCS_PROT_OSCEP1_MASK         0x08U
  #define OCCS_PROT_FRQEP0_MASK         0x10U
  #define OCCS_PROT_FRQEP1_MASK         0x20U
  #define OCCS_PROT_PLLEP_MASK          0x03U
  #define OCCS_PROT_PLLEP_BITNUM        0x00U
  #define OCCS_PROT_OSCEP_MASK          0x0CU
  #define OCCS_PROT_OSCEP_BITNUM        0x02U
  #define OCCS_PROT_FRQEP_MASK          0x30U
  #define OCCS_PROT_FRQEP_BITNUM        0x04U
  #define OCCS_PROT                     (*((volatile word *)0x0000E2B8))


} OCCS_PRPH;
/******************************************
*** Peripheral INTC
*******************************************/
typedef volatile struct {
  /*** INTC_IPR0 - Interrupt Priority Register 0; 0x0000E300 ***/
  union {
    word Word;
  } INTC_IPR0_STR;

  #define INTC_IPR0_STPCNT0_MASK        0x01U
  #define INTC_IPR0_STPCNT1_MASK        0x02U
  #define INTC_IPR0_BKPT0_MASK          0x04U
  #define INTC_IPR0_BKPT1_MASK          0x08U
  #define INTC_IPR0_TRBUF0_MASK         0x10U
  #define INTC_IPR0_TRBUF1_MASK         0x20U
  #define INTC_IPR0_TX_REG0_MASK        0x40U
  #define INTC_IPR0_TX_REG1_MASK        0x80U
  #define INTC_IPR0_RX_REG0_MASK        0x0100U
  #define INTC_IPR0_RX_REG1_MASK        0x0200U
  #define INTC_IPR0_BUS_ERR0_MASK       0x0400U
  #define INTC_IPR0_BUS_ERR1_MASK       0x0800U
  #define INTC_IPR0_STPCNT_MASK         0x03U
  #define INTC_IPR0_STPCNT_BITNUM       0x00U
  #define INTC_IPR0_BKPT_MASK           0x0CU
  #define INTC_IPR0_BKPT_BITNUM         0x02U
  #define INTC_IPR0_TRBUF_MASK          0x30U
  #define INTC_IPR0_TRBUF_BITNUM        0x04U
  #define INTC_IPR0_TX_REG_MASK         0xC0U
  #define INTC_IPR0_TX_REG_BITNUM       0x06U
  #define INTC_IPR0_RX_REG_MASK         0x0300U
  #define INTC_IPR0_RX_REG_BITNUM       0x08U
  #define INTC_IPR0_BUS_ERR_MASK        0x0C00U
  #define INTC_IPR0_BUS_ERR_BITNUM      0x0AU
  #define INTC_IPR0                     (*((volatile word *)0x0000E300))


  /*** INTC_IPR1 - Interrupt Priority Register 1; 0x0000E301 ***/
  union {
    word Word;
  } INTC_IPR1_STR;

  #define INTC_IPR1_XBARA0_MASK         0x04U
  #define INTC_IPR1_XBARA1_MASK         0x08U
  #define INTC_IPR1_LVI10_MASK          0x10U
  #define INTC_IPR1_LVI11_MASK          0x20U
  #define INTC_IPR1_OCCS0_MASK          0x40U
  #define INTC_IPR1_OCCS1_MASK          0x80U
  #define INTC_IPR1_TMRB_30_MASK        0x0100U
  #define INTC_IPR1_TMRB_31_MASK        0x0200U
  #define INTC_IPR1_TMRB_20_MASK        0x0400U
  #define INTC_IPR1_TMRB_21_MASK        0x0800U
  #define INTC_IPR1_TMRB_10_MASK        0x1000U
  #define INTC_IPR1_TMRB_11_MASK        0x2000U
  #define INTC_IPR1_TMRB_00_MASK        0x4000U
  #define INTC_IPR1_TMRB_01_MASK        0x8000U
  #define INTC_IPR1_XBARA_MASK          0x0CU
  #define INTC_IPR1_XBARA_BITNUM        0x02U
  #define INTC_IPR1_LVI1_MASK           0x30U
  #define INTC_IPR1_LVI1_BITNUM         0x04U
  #define INTC_IPR1_OCCS_MASK           0xC0U
  #define INTC_IPR1_OCCS_BITNUM         0x06U
  #define INTC_IPR1_TMRB_3_MASK         0x0300U
  #define INTC_IPR1_TMRB_3_BITNUM       0x08U
  #define INTC_IPR1_TMRB_2_MASK         0x0C00U
  #define INTC_IPR1_TMRB_2_BITNUM       0x0AU
  #define INTC_IPR1_TMRB_1_MASK         0x3000U
  #define INTC_IPR1_TMRB_1_BITNUM       0x0CU
  #define INTC_IPR1_TMRB_0_MASK         0xC000U
  #define INTC_IPR1_TMRB_0_BITNUM       0x0EU
  #define INTC_IPR1                     (*((volatile word *)0x0000E301))


  /*** INTC_IPR2 - Interrupt Priority Register 2; 0x0000E302 ***/
  union {
    word Word;
  } INTC_IPR2_STR;

  #define INTC_IPR2_TMRA_30_MASK        0x01U
  #define INTC_IPR2_TMRA_31_MASK        0x02U
  #define INTC_IPR2_TMRA_20_MASK        0x04U
  #define INTC_IPR2_TMRA_21_MASK        0x08U
  #define INTC_IPR2_TMRA_10_MASK        0x10U
  #define INTC_IPR2_TMRA_11_MASK        0x20U
  #define INTC_IPR2_TMRA_00_MASK        0x40U
  #define INTC_IPR2_TMRA_01_MASK        0x80U
  #define INTC_IPR2_ADC_CC10_MASK       0x0100U
  #define INTC_IPR2_ADC_CC11_MASK       0x0200U
  #define INTC_IPR2_ADC_CC00_MASK       0x0400U
  #define INTC_IPR2_ADC_CC01_MASK       0x0800U
  #define INTC_IPR2_ADC_ERR0_MASK       0x1000U
  #define INTC_IPR2_ADC_ERR1_MASK       0x2000U
  #define INTC_IPR2_ADC_COCO0_MASK      0x4000U
  #define INTC_IPR2_ADC_COCO1_MASK      0x8000U
  #define INTC_IPR2_TMRA_3_MASK         0x03U
  #define INTC_IPR2_TMRA_3_BITNUM       0x00U
  #define INTC_IPR2_TMRA_2_MASK         0x0CU
  #define INTC_IPR2_TMRA_2_BITNUM       0x02U
  #define INTC_IPR2_TMRA_1_MASK         0x30U
  #define INTC_IPR2_TMRA_1_BITNUM       0x04U
  #define INTC_IPR2_TMRA_0_MASK         0xC0U
  #define INTC_IPR2_TMRA_0_BITNUM       0x06U
  #define INTC_IPR2_ADC_CC1_MASK        0x0300U
  #define INTC_IPR2_ADC_CC1_BITNUM      0x08U
  #define INTC_IPR2_ADC_CC0_MASK        0x0C00U
  #define INTC_IPR2_ADC_CC0_BITNUM      0x0AU
  #define INTC_IPR2_ADC_ERR_MASK        0x3000U
  #define INTC_IPR2_ADC_ERR_BITNUM      0x0CU
  #define INTC_IPR2_ADC_COCO_MASK       0xC000U
  #define INTC_IPR2_ADC_COCO_BITNUM     0x0EU
  #define INTC_IPR2                     (*((volatile word *)0x0000E302))


  /*** INTC_IPR3 - Interrupt Priority Register 3; 0x0000E303 ***/
  union {
    word Word;
  } INTC_IPR3_STR;

  #define INTC_IPR3_DMACH30_MASK        0x01U
  #define INTC_IPR3_DMACH31_MASK        0x02U
  #define INTC_IPR3_DMACH20_MASK        0x04U
  #define INTC_IPR3_DMACH21_MASK        0x08U
  #define INTC_IPR3_DMACH10_MASK        0x10U
  #define INTC_IPR3_DMACH11_MASK        0x20U
  #define INTC_IPR3_DMACH00_MASK        0x40U
  #define INTC_IPR3_DMACH01_MASK        0x80U
  #define INTC_IPR3_CAN_MB_OR0_MASK     0x0100U
  #define INTC_IPR3_CAN_MB_OR1_MASK     0x0200U
  #define INTC_IPR3_CAN_BUS_OFF0_MASK   0x0400U
  #define INTC_IPR3_CAN_BUS_OFF1_MASK   0x0800U
  #define INTC_IPR3_CAN_ERROR0_MASK     0x1000U
  #define INTC_IPR3_CAN_ERROR1_MASK     0x2000U
  #define INTC_IPR3_CAN_TX_WARN0_MASK   0x4000U
  #define INTC_IPR3_CAN_TX_WARN1_MASK   0x8000U
  #define INTC_IPR3_DMACH3_MASK         0x03U
  #define INTC_IPR3_DMACH3_BITNUM       0x00U
  #define INTC_IPR3_DMACH2_MASK         0x0CU
  #define INTC_IPR3_DMACH2_BITNUM       0x02U
  #define INTC_IPR3_DMACH1_MASK         0x30U
  #define INTC_IPR3_DMACH1_BITNUM       0x04U
  #define INTC_IPR3_DMACH0_MASK         0xC0U
  #define INTC_IPR3_DMACH0_BITNUM       0x06U
  #define INTC_IPR3_CAN_MB_OR_MASK      0x0300U
  #define INTC_IPR3_CAN_MB_OR_BITNUM    0x08U
  #define INTC_IPR3_CAN_BUS_OFF_MASK    0x0C00U
  #define INTC_IPR3_CAN_BUS_OFF_BITNUM  0x0AU
  #define INTC_IPR3_CAN_ERROR_MASK      0x3000U
  #define INTC_IPR3_CAN_ERROR_BITNUM    0x0CU
  #define INTC_IPR3_CAN_TX_WARN_MASK    0xC000U
  #define INTC_IPR3_CAN_TX_WARN_BITNUM  0x0EU
  #define INTC_IPR3                     (*((volatile word *)0x0000E303))


  /*** INTC_IPR4 - Interrupt Priority Register 4; 0x0000E304 ***/
  union {
    word Word;
  } INTC_IPR4_STR;

  #define INTC_IPR4_CAN_RX_WARN0_MASK   0x01U
  #define INTC_IPR4_CAN_RX_WARN1_MASK   0x02U
  #define INTC_IPR4_CAN_WAKEUP0_MASK    0x04U
  #define INTC_IPR4_CAN_WAKEUP1_MASK    0x08U
  #define INTC_IPR4_QSCI2_RERR0_MASK    0x10U
  #define INTC_IPR4_QSCI2_RERR1_MASK    0x20U
  #define INTC_IPR4_QSCI2_RCV0_MASK     0x40U
  #define INTC_IPR4_QSCI2_RCV1_MASK     0x80U
  #define INTC_IPR4_QSCI2_TIDLE0_MASK   0x0100U
  #define INTC_IPR4_QSCI2_TIDLE1_MASK   0x0200U
  #define INTC_IPR4_QSCI2_TDRE0_MASK    0x0400U
  #define INTC_IPR4_QSCI2_TDRE1_MASK    0x0800U
  #define INTC_IPR4_QSCI1_RERR0_MASK    0x1000U
  #define INTC_IPR4_QSCI1_RERR1_MASK    0x2000U
  #define INTC_IPR4_QSCI1_RCV0_MASK     0x4000U
  #define INTC_IPR4_QSCI1_RCV1_MASK     0x8000U
  #define INTC_IPR4_CAN_RX_WARN_MASK    0x03U
  #define INTC_IPR4_CAN_RX_WARN_BITNUM  0x00U
  #define INTC_IPR4_CAN_WAKEUP_MASK     0x0CU
  #define INTC_IPR4_CAN_WAKEUP_BITNUM   0x02U
  #define INTC_IPR4_QSCI2_RERR_MASK     0x30U
  #define INTC_IPR4_QSCI2_RERR_BITNUM   0x04U
  #define INTC_IPR4_QSCI2_RCV_MASK      0xC0U
  #define INTC_IPR4_QSCI2_RCV_BITNUM    0x06U
  #define INTC_IPR4_QSCI2_TIDLE_MASK    0x0300U
  #define INTC_IPR4_QSCI2_TIDLE_BITNUM  0x08U
  #define INTC_IPR4_QSCI2_TDRE_MASK     0x0C00U
  #define INTC_IPR4_QSCI2_TDRE_BITNUM   0x0AU
  #define INTC_IPR4_QSCI1_RERR_MASK     0x3000U
  #define INTC_IPR4_QSCI1_RERR_BITNUM   0x0CU
  #define INTC_IPR4_QSCI1_RCV_MASK      0xC000U
  #define INTC_IPR4_QSCI1_RCV_BITNUM    0x0EU
  #define INTC_IPR4                     (*((volatile word *)0x0000E304))


  /*** INTC_IPR5 - Interrupt Priority Register 5; 0x0000E305 ***/
  union {
    word Word;
  } INTC_IPR5_STR;

  #define INTC_IPR5_QSCI1_TIDLE0_MASK   0x01U
  #define INTC_IPR5_QSCI1_TIDLE1_MASK   0x02U
  #define INTC_IPR5_QSCI1_TDRE0_MASK    0x04U
  #define INTC_IPR5_QSCI1_TDRE1_MASK    0x08U
  #define INTC_IPR5_QSCI0_RERR0_MASK    0x10U
  #define INTC_IPR5_QSCI0_RERR1_MASK    0x20U
  #define INTC_IPR5_QSCI0_RCV0_MASK     0x40U
  #define INTC_IPR5_QSCI0_RCV1_MASK     0x80U
  #define INTC_IPR5_QSCI0_TIDLE0_MASK   0x0100U
  #define INTC_IPR5_QSCI0_TIDLE1_MASK   0x0200U
  #define INTC_IPR5_QSCI0_TDRE0_MASK    0x0400U
  #define INTC_IPR5_QSCI0_TDRE1_MASK    0x0800U
  #define INTC_IPR5_QSPI2_XMIT0_MASK    0x1000U
  #define INTC_IPR5_QSPI2_XMIT1_MASK    0x2000U
  #define INTC_IPR5_QSPI2_RCV0_MASK     0x4000U
  #define INTC_IPR5_QSPI2_RCV1_MASK     0x8000U
  #define INTC_IPR5_QSCI1_TIDLE_MASK    0x03U
  #define INTC_IPR5_QSCI1_TIDLE_BITNUM  0x00U
  #define INTC_IPR5_QSCI1_TDRE_MASK     0x0CU
  #define INTC_IPR5_QSCI1_TDRE_BITNUM   0x02U
  #define INTC_IPR5_QSCI0_RERR_MASK     0x30U
  #define INTC_IPR5_QSCI0_RERR_BITNUM   0x04U
  #define INTC_IPR5_QSCI0_RCV_MASK      0xC0U
  #define INTC_IPR5_QSCI0_RCV_BITNUM    0x06U
  #define INTC_IPR5_QSCI0_TIDLE_MASK    0x0300U
  #define INTC_IPR5_QSCI0_TIDLE_BITNUM  0x08U
  #define INTC_IPR5_QSCI0_TDRE_MASK     0x0C00U
  #define INTC_IPR5_QSCI0_TDRE_BITNUM   0x0AU
  #define INTC_IPR5_QSPI2_XMIT_MASK     0x3000U
  #define INTC_IPR5_QSPI2_XMIT_BITNUM   0x0CU
  #define INTC_IPR5_QSPI2_RCV_MASK      0xC000U
  #define INTC_IPR5_QSPI2_RCV_BITNUM    0x0EU
  #define INTC_IPR5                     (*((volatile word *)0x0000E305))


  /*** INTC_IPR6 - Interrupt Priority Register 6; 0x0000E306 ***/
  union {
    word Word;
  } INTC_IPR6_STR;

  #define INTC_IPR6_QSPI1_XMIT0_MASK    0x01U
  #define INTC_IPR6_QSPI1_XMIT1_MASK    0x02U
  #define INTC_IPR6_QSPI1_RCV0_MASK     0x04U
  #define INTC_IPR6_QSPI1_RCV1_MASK     0x08U
  #define INTC_IPR6_QSPI0_XMIT0_MASK    0x10U
  #define INTC_IPR6_QSPI0_XMIT1_MASK    0x20U
  #define INTC_IPR6_QSPI0_RCV0_MASK     0x40U
  #define INTC_IPR6_QSPI0_RCV1_MASK     0x80U
  #define INTC_IPR6_IIC10_MASK          0x0100U
  #define INTC_IPR6_IIC11_MASK          0x0200U
  #define INTC_IPR6_IIC00_MASK          0x0400U
  #define INTC_IPR6_IIC01_MASK          0x0800U
  #define INTC_IPR6_PWMB_FAULT0_MASK    0x1000U
  #define INTC_IPR6_PWMB_FAULT1_MASK    0x2000U
  #define INTC_IPR6_PWMB_RERR0_MASK     0x4000U
  #define INTC_IPR6_PWMB_RERR1_MASK     0x8000U
  #define INTC_IPR6_QSPI1_XMIT_MASK     0x03U
  #define INTC_IPR6_QSPI1_XMIT_BITNUM   0x00U
  #define INTC_IPR6_QSPI1_RCV_MASK      0x0CU
  #define INTC_IPR6_QSPI1_RCV_BITNUM    0x02U
  #define INTC_IPR6_QSPI0_XMIT_MASK     0x30U
  #define INTC_IPR6_QSPI0_XMIT_BITNUM   0x04U
  #define INTC_IPR6_QSPI0_RCV_MASK      0xC0U
  #define INTC_IPR6_QSPI0_RCV_BITNUM    0x06U
  #define INTC_IPR6_IIC1_MASK           0x0300U
  #define INTC_IPR6_IIC1_BITNUM         0x08U
  #define INTC_IPR6_IIC0_MASK           0x0C00U
  #define INTC_IPR6_IIC0_BITNUM         0x0AU
  #define INTC_IPR6_PWMB_FAULT_MASK     0x3000U
  #define INTC_IPR6_PWMB_FAULT_BITNUM   0x0CU
  #define INTC_IPR6_PWMB_RERR_MASK      0xC000U
  #define INTC_IPR6_PWMB_RERR_BITNUM    0x0EU
  #define INTC_IPR6                     (*((volatile word *)0x0000E306))


  /*** INTC_IPR7 - Interrupt Priority Register 7; 0x0000E307 ***/
  union {
    word Word;
  } INTC_IPR7_STR;

  #define INTC_IPR7_PWMB_RELOAD30_MASK  0x01U
  #define INTC_IPR7_PWMB_RELOAD31_MASK  0x02U
  #define INTC_IPR7_PWMB_CAP30_MASK     0x04U
  #define INTC_IPR7_PWMB_CAP31_MASK     0x08U
  #define INTC_IPR7_PWMB_CMP30_MASK     0x10U
  #define INTC_IPR7_PWMB_CMP31_MASK     0x20U
  #define INTC_IPR7_PWMB_RELOAD20_MASK  0x40U
  #define INTC_IPR7_PWMB_RELOAD21_MASK  0x80U
  #define INTC_IPR7_PWMB_CAP20_MASK     0x0100U
  #define INTC_IPR7_PWMB_CAP21_MASK     0x0200U
  #define INTC_IPR7_PWMB_CMP20_MASK     0x0400U
  #define INTC_IPR7_PWMB_CMP21_MASK     0x0800U
  #define INTC_IPR7_PWMB_RELOAD10_MASK  0x1000U
  #define INTC_IPR7_PWMB_RELOAD11_MASK  0x2000U
  #define INTC_IPR7_PWMB_CAP10_MASK     0x4000U
  #define INTC_IPR7_PWMB_CAP11_MASK     0x8000U
  #define INTC_IPR7_PWMB_RELOAD3_MASK   0x03U
  #define INTC_IPR7_PWMB_RELOAD3_BITNUM 0x00U
  #define INTC_IPR7_PWMB_CAP3_MASK      0x0CU
  #define INTC_IPR7_PWMB_CAP3_BITNUM    0x02U
  #define INTC_IPR7_PWMB_CMP3_MASK      0x30U
  #define INTC_IPR7_PWMB_CMP3_BITNUM    0x04U
  #define INTC_IPR7_PWMB_RELOAD2_MASK   0xC0U
  #define INTC_IPR7_PWMB_RELOAD2_BITNUM 0x06U
  #define INTC_IPR7_PWMB_CAP2_MASK      0x0300U
  #define INTC_IPR7_PWMB_CAP2_BITNUM    0x08U
  #define INTC_IPR7_PWMB_CMP2_MASK      0x0C00U
  #define INTC_IPR7_PWMB_CMP2_BITNUM    0x0AU
  #define INTC_IPR7_PWMB_RELOAD1_MASK   0x3000U
  #define INTC_IPR7_PWMB_RELOAD1_BITNUM 0x0CU
  #define INTC_IPR7_PWMB_CAP1_MASK      0xC000U
  #define INTC_IPR7_PWMB_CAP1_BITNUM    0x0EU
  #define INTC_IPR7                     (*((volatile word *)0x0000E307))


  /*** INTC_IPR8 - Interrupt Priority Register 8; 0x0000E308 ***/
  union {
    word Word;
  } INTC_IPR8_STR;

  #define INTC_IPR8_PWMB_CMP10_MASK     0x01U
  #define INTC_IPR8_PWMB_CMP11_MASK     0x02U
  #define INTC_IPR8_PWMB_RELOAD00_MASK  0x04U
  #define INTC_IPR8_PWMB_RELOAD01_MASK  0x08U
  #define INTC_IPR8_PWMB_CAP00_MASK     0x10U
  #define INTC_IPR8_PWMB_CAP01_MASK     0x20U
  #define INTC_IPR8_PWMB_CMP00_MASK     0x40U
  #define INTC_IPR8_PWMB_CMP01_MASK     0x80U
  #define INTC_IPR8_PWMA_FAULT0_MASK    0x0100U
  #define INTC_IPR8_PWMA_FAULT1_MASK    0x0200U
  #define INTC_IPR8_PWMA_RERR0_MASK     0x0400U
  #define INTC_IPR8_PWMA_RERR1_MASK     0x0800U
  #define INTC_IPR8_PWMA_RELOAD30_MASK  0x1000U
  #define INTC_IPR8_PWMA_RELOAD31_MASK  0x2000U
  #define INTC_IPR8_PWMA_CAP0_MASK      0x4000U
  #define INTC_IPR8_PWMA_CAP1_MASK      0x8000U
  #define INTC_IPR8_PWMB_CMP1_MASK      0x03U
  #define INTC_IPR8_PWMB_CMP1_BITNUM    0x00U
  #define INTC_IPR8_PWMB_RELOAD0_MASK   0x0CU
  #define INTC_IPR8_PWMB_RELOAD0_BITNUM 0x02U
  #define INTC_IPR8_PWMB_CAP0_MASK      0x30U
  #define INTC_IPR8_PWMB_CAP0_BITNUM    0x04U
  #define INTC_IPR8_PWMB_CMP0_MASK      0xC0U
  #define INTC_IPR8_PWMB_CMP0_BITNUM    0x06U
  #define INTC_IPR8_PWMA_FAULT_MASK     0x0300U
  #define INTC_IPR8_PWMA_FAULT_BITNUM   0x08U
  #define INTC_IPR8_PWMA_RERR_MASK      0x0C00U
  #define INTC_IPR8_PWMA_RERR_BITNUM    0x0AU
  #define INTC_IPR8_PWMA_RELOAD3_MASK   0x3000U
  #define INTC_IPR8_PWMA_RELOAD3_BITNUM 0x0CU
  #define INTC_IPR8_PWMA_CAP_MASK       0xC000U
  #define INTC_IPR8_PWMA_CAP_BITNUM     0x0EU
  #define INTC_IPR8                     (*((volatile word *)0x0000E308))


  /*** INTC_IPR9 - Interrupt Priority Register 9; 0x0000E309 ***/
  union {
    word Word;
  } INTC_IPR9_STR;

  #define INTC_IPR9_PWMA_CMP30_MASK     0x01U
  #define INTC_IPR9_PWMA_CMP31_MASK     0x02U
  #define INTC_IPR9_PWMA_RELOAD20_MASK  0x04U
  #define INTC_IPR9_PWMA_RELOAD21_MASK  0x08U
  #define INTC_IPR9_PWMA_CMP20_MASK     0x10U
  #define INTC_IPR9_PWMA_CMP21_MASK     0x20U
  #define INTC_IPR9_PWMA_RELOAD10_MASK  0x40U
  #define INTC_IPR9_PWMA_RELOAD11_MASK  0x80U
  #define INTC_IPR9_PWMA_CMP10_MASK     0x0100U
  #define INTC_IPR9_PWMA_CMP11_MASK     0x0200U
  #define INTC_IPR9_PWMA_RELOAD00_MASK  0x0400U
  #define INTC_IPR9_PWMA_RELOAD01_MASK  0x0800U
  #define INTC_IPR9_PWMA_CMP00_MASK     0x1000U
  #define INTC_IPR9_PWMA_CMP01_MASK     0x2000U
  #define INTC_IPR9_FTFL_RDCOL0_MASK    0x4000U
  #define INTC_IPR9_FTFL_RDCOL1_MASK    0x8000U
  #define INTC_IPR9_PWMA_CMP3_MASK      0x03U
  #define INTC_IPR9_PWMA_CMP3_BITNUM    0x00U
  #define INTC_IPR9_PWMA_RELOAD2_MASK   0x0CU
  #define INTC_IPR9_PWMA_RELOAD2_BITNUM 0x02U
  #define INTC_IPR9_PWMA_CMP2_MASK      0x30U
  #define INTC_IPR9_PWMA_CMP2_BITNUM    0x04U
  #define INTC_IPR9_PWMA_RELOAD1_MASK   0xC0U
  #define INTC_IPR9_PWMA_RELOAD1_BITNUM 0x06U
  #define INTC_IPR9_PWMA_CMP1_MASK      0x0300U
  #define INTC_IPR9_PWMA_CMP1_BITNUM    0x08U
  #define INTC_IPR9_PWMA_RELOAD0_MASK   0x0C00U
  #define INTC_IPR9_PWMA_RELOAD0_BITNUM 0x0AU
  #define INTC_IPR9_PWMA_CMP0_MASK      0x3000U
  #define INTC_IPR9_PWMA_CMP0_BITNUM    0x0CU
  #define INTC_IPR9_FTFL_RDCOL_MASK     0xC000U
  #define INTC_IPR9_FTFL_RDCOL_BITNUM   0x0EU
  #define INTC_IPR9                     (*((volatile word *)0x0000E309))


  /*** INTC_IPR10 - Interrupt Priority Register 10; 0x0000E30A ***/
  union {
    word Word;
  } INTC_IPR10_STR;

  #define INTC_IPR10_FTFL_CC0_MASK      0x01U
  #define INTC_IPR10_FTFL_CC1_MASK      0x02U
  #define INTC_IPR10_CMPD0_MASK         0x04U
  #define INTC_IPR10_CMPD1_MASK         0x08U
  #define INTC_IPR10_CMPC0_MASK         0x10U
  #define INTC_IPR10_CMPC1_MASK         0x20U
  #define INTC_IPR10_CMPB0_MASK         0x40U
  #define INTC_IPR10_CMPB1_MASK         0x80U
  #define INTC_IPR10_CMPA0_MASK         0x0100U
  #define INTC_IPR10_CMPA1_MASK         0x0200U
  #define INTC_IPR10_PIT1_ROLLOVR0_MASK 0x0400U
  #define INTC_IPR10_PIT1_ROLLOVR1_MASK 0x0800U
  #define INTC_IPR10_PIT0_ROLLOVR0_MASK 0x1000U
  #define INTC_IPR10_PIT0_ROLLOVR1_MASK 0x2000U
  #define INTC_IPR10_PDB10_MASK         0x4000U
  #define INTC_IPR10_PDB11_MASK         0x8000U
  #define INTC_IPR10_FTFL_CC_MASK       0x03U
  #define INTC_IPR10_FTFL_CC_BITNUM     0x00U
  #define INTC_IPR10_CMPD_MASK          0x0CU
  #define INTC_IPR10_CMPD_BITNUM        0x02U
  #define INTC_IPR10_CMPC_MASK          0x30U
  #define INTC_IPR10_CMPC_BITNUM        0x04U
  #define INTC_IPR10_CMPB_MASK          0xC0U
  #define INTC_IPR10_CMPB_BITNUM        0x06U
  #define INTC_IPR10_CMPA_MASK          0x0300U
  #define INTC_IPR10_CMPA_BITNUM        0x08U
  #define INTC_IPR10_PIT1_ROLLOVR_MASK  0x0C00U
  #define INTC_IPR10_PIT1_ROLLOVR_BITNUM 0x0AU
  #define INTC_IPR10_PIT0_ROLLOVR_MASK  0x3000U
  #define INTC_IPR10_PIT0_ROLLOVR_BITNUM 0x0CU
  #define INTC_IPR10_PDB1_MASK          0xC000U
  #define INTC_IPR10_PDB1_BITNUM        0x0EU
  #define INTC_IPR10                    (*((volatile word *)0x0000E30A))


  /*** INTC_IPR11 - Interrupt Priority Register 11; 0x0000E30B ***/
  union {
    word Word;
  } INTC_IPR11_STR;

  #define INTC_IPR11_PDB00_MASK         0x01U
  #define INTC_IPR11_PDB01_MASK         0x02U
  #define INTC_IPR11_ENC_INDEX0_MASK    0x04U
  #define INTC_IPR11_ENC_INDEX1_MASK    0x08U
  #define INTC_IPR11_ENC_HOME_DOG0_MASK 0x10U
  #define INTC_IPR11_ENC_HOME_DOG1_MASK 0x20U
  #define INTC_IPR11_ENC_COMPARE0_MASK  0x40U
  #define INTC_IPR11_ENC_COMPARE1_MASK  0x80U
  #define INTC_IPR11_GPIOG0_MASK        0x0100U
  #define INTC_IPR11_GPIOG1_MASK        0x0200U
  #define INTC_IPR11_GPIOF0_MASK        0x0400U
  #define INTC_IPR11_GPIOF1_MASK        0x0800U
  #define INTC_IPR11_GPIOE0_MASK        0x1000U
  #define INTC_IPR11_GPIOE1_MASK        0x2000U
  #define INTC_IPR11_GPIOD0_MASK        0x4000U
  #define INTC_IPR11_GPIOD1_MASK        0x8000U
  #define INTC_IPR11_PDB0_MASK          0x03U
  #define INTC_IPR11_PDB0_BITNUM        0x00U
  #define INTC_IPR11_ENC_INDEX_MASK     0x0CU
  #define INTC_IPR11_ENC_INDEX_BITNUM   0x02U
  #define INTC_IPR11_ENC_HOME_DOG_MASK  0x30U
  #define INTC_IPR11_ENC_HOME_DOG_BITNUM 0x04U
  #define INTC_IPR11_ENC_COMPARE_MASK   0xC0U
  #define INTC_IPR11_ENC_COMPARE_BITNUM 0x06U
  #define INTC_IPR11_GPIOG_MASK         0x0300U
  #define INTC_IPR11_GPIOG_BITNUM       0x08U
  #define INTC_IPR11_GPIOF_MASK         0x0C00U
  #define INTC_IPR11_GPIOF_BITNUM       0x0AU
  #define INTC_IPR11_GPIOE_MASK         0x3000U
  #define INTC_IPR11_GPIOE_BITNUM       0x0CU
  #define INTC_IPR11_GPIOD_MASK         0xC000U
  #define INTC_IPR11_GPIOD_BITNUM       0x0EU
  #define INTC_IPR11                    (*((volatile word *)0x0000E30B))


  /*** INTC_IPR12 - Interrupt Priority Register 12; 0x0000E30C ***/
  union {
    word Word;
  } INTC_IPR12_STR;

  #define INTC_IPR12_GPIOC0_MASK        0x01U
  #define INTC_IPR12_GPIOC1_MASK        0x02U
  #define INTC_IPR12_GPIOB0_MASK        0x04U
  #define INTC_IPR12_GPIOB1_MASK        0x08U
  #define INTC_IPR12_GPIOA0_MASK        0x10U
  #define INTC_IPR12_GPIOA1_MASK        0x20U
  #define INTC_IPR12_COP_INT0_MASK      0x40U
  #define INTC_IPR12_COP_INT1_MASK      0x80U
  #define INTC_IPR12_EWM_INT0_MASK      0x0100U
  #define INTC_IPR12_EWM_INT1_MASK      0x0200U
  #define INTC_IPR12_GPIOC_MASK         0x03U
  #define INTC_IPR12_GPIOC_BITNUM       0x00U
  #define INTC_IPR12_GPIOB_MASK         0x0CU
  #define INTC_IPR12_GPIOB_BITNUM       0x02U
  #define INTC_IPR12_GPIOA_MASK         0x30U
  #define INTC_IPR12_GPIOA_BITNUM       0x04U
  #define INTC_IPR12_COP_INT_MASK       0xC0U
  #define INTC_IPR12_COP_INT_BITNUM     0x06U
  #define INTC_IPR12_EWM_INT_MASK       0x0300U
  #define INTC_IPR12_EWM_INT_BITNUM     0x08U
  #define INTC_IPR12                    (*((volatile word *)0x0000E30C))


  /*** INTC_VBA - Vector Base Address Register; 0x0000E30D ***/
  union {
    word Word;
  } INTC_VBA_STR;

  #define INTC_VBA_VECTOR_BASE_ADDRESS0_MASK 0x01U
  #define INTC_VBA_VECTOR_BASE_ADDRESS1_MASK 0x02U
  #define INTC_VBA_VECTOR_BASE_ADDRESS2_MASK 0x04U
  #define INTC_VBA_VECTOR_BASE_ADDRESS3_MASK 0x08U
  #define INTC_VBA_VECTOR_BASE_ADDRESS4_MASK 0x10U
  #define INTC_VBA_VECTOR_BASE_ADDRESS5_MASK 0x20U
  #define INTC_VBA_VECTOR_BASE_ADDRESS6_MASK 0x40U
  #define INTC_VBA_VECTOR_BASE_ADDRESS7_MASK 0x80U
  #define INTC_VBA_VECTOR_BASE_ADDRESS8_MASK 0x0100U
  #define INTC_VBA_VECTOR_BASE_ADDRESS9_MASK 0x0200U
  #define INTC_VBA_VECTOR_BASE_ADDRESS10_MASK 0x0400U
  #define INTC_VBA_VECTOR_BASE_ADDRESS11_MASK 0x0800U
  #define INTC_VBA_VECTOR_BASE_ADDRESS12_MASK 0x1000U
  #define INTC_VBA_VECTOR_BASE_ADDRESS_MASK 0x1FFFU
  #define INTC_VBA_VECTOR_BASE_ADDRESS_BITNUM 0x00U
  #define INTC_VBA                      (*((volatile word *)0x0000E30D))


  /*** INTC_FIM0 - Fast Interrupt 0 Match Register; 0x0000E30E ***/
  union {
    word Word;
  } INTC_FIM0_STR;

  #define INTC_FIM0_FAST_INTERRUPT_00_MASK 0x01U
  #define INTC_FIM0_FAST_INTERRUPT_01_MASK 0x02U
  #define INTC_FIM0_FAST_INTERRUPT_02_MASK 0x04U
  #define INTC_FIM0_FAST_INTERRUPT_03_MASK 0x08U
  #define INTC_FIM0_FAST_INTERRUPT_04_MASK 0x10U
  #define INTC_FIM0_FAST_INTERRUPT_05_MASK 0x20U
  #define INTC_FIM0_FAST_INTERRUPT_06_MASK 0x40U
  #define INTC_FIM0_FAST_INTERRUPT_0_MASK 0x7FU
  #define INTC_FIM0_FAST_INTERRUPT_0_BITNUM 0x00U
  #define INTC_FIM0                     (*((volatile word *)0x0000E30E))


  /*** INTC_FIVAL0 - Fast Interrupt 0 Vector Address Low Register; 0x0000E30F ***/
  union {
    word Word;
  } INTC_FIVAL0_STR;

  #define INTC_FIVAL0                   (*((volatile word *)0x0000E30F))


  /*** INTC_FIVAH0 - Fast Interrupt 0 Vector Address High Register; 0x0000E310 ***/
  union {
    word Word;
  } INTC_FIVAH0_STR;

  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH0_MASK 0x01U
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH1_MASK 0x02U
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH2_MASK 0x04U
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH3_MASK 0x08U
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH4_MASK 0x10U
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH_MASK 0x1FU
  #define INTC_FIVAH0_FI_0_VECTOR_ADDRESS_HIGH_BITNUM 0x00U
  #define INTC_FIVAH0                   (*((volatile word *)0x0000E310))


  /*** INTC_FIM1 - Fast Interrupt 1 Match Register; 0x0000E311 ***/
  union {
    word Word;
  } INTC_FIM1_STR;

  #define INTC_FIM1_FAST_INTERRUPT_10_MASK 0x01U
  #define INTC_FIM1_FAST_INTERRUPT_11_MASK 0x02U
  #define INTC_FIM1_FAST_INTERRUPT_12_MASK 0x04U
  #define INTC_FIM1_FAST_INTERRUPT_13_MASK 0x08U
  #define INTC_FIM1_FAST_INTERRUPT_14_MASK 0x10U
  #define INTC_FIM1_FAST_INTERRUPT_15_MASK 0x20U
  #define INTC_FIM1_FAST_INTERRUPT_16_MASK 0x40U
  #define INTC_FIM1_FAST_INTERRUPT_1_MASK 0x7FU
  #define INTC_FIM1_FAST_INTERRUPT_1_BITNUM 0x00U
  #define INTC_FIM1                     (*((volatile word *)0x0000E311))


  /*** INTC_FIVAL1 - Fast Interrupt 1 Vector Address Low Register; 0x0000E312 ***/
  union {
    word Word;
  } INTC_FIVAL1_STR;

  #define INTC_FIVAL1                   (*((volatile word *)0x0000E312))


  /*** INTC_FIVAH1 - Fast Interrupt 1 Vector Address High Register; 0x0000E313 ***/
  union {
    word Word;
  } INTC_FIVAH1_STR;

  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH0_MASK 0x01U
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH1_MASK 0x02U
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH2_MASK 0x04U
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH3_MASK 0x08U
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH4_MASK 0x10U
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH_MASK 0x1FU
  #define INTC_FIVAH1_FI_1_VECTOR_ADDRESS_HIGH_BITNUM 0x00U
  #define INTC_FIVAH1                   (*((volatile word *)0x0000E313))


  /*** INTC_IRQP0 - IRQ Pending Register 0; 0x0000E314 ***/
  union {
    word Word;
  } INTC_IRQP0_STR;

  #define INTC_IRQP0_PENDING0_MASK      0x02U
  #define INTC_IRQP0_PENDING1_MASK      0x04U
  #define INTC_IRQP0_PENDING2_MASK      0x08U
  #define INTC_IRQP0_PENDING3_MASK      0x10U
  #define INTC_IRQP0_PENDING4_MASK      0x20U
  #define INTC_IRQP0_PENDING5_MASK      0x40U
  #define INTC_IRQP0_PENDING6_MASK      0x80U
  #define INTC_IRQP0_PENDING7_MASK      0x0100U
  #define INTC_IRQP0_PENDING8_MASK      0x0200U
  #define INTC_IRQP0_PENDING9_MASK      0x0400U
  #define INTC_IRQP0_PENDING10_MASK     0x0800U
  #define INTC_IRQP0_PENDING11_MASK     0x1000U
  #define INTC_IRQP0_PENDING12_MASK     0x2000U
  #define INTC_IRQP0_PENDING13_MASK     0x4000U
  #define INTC_IRQP0_PENDING14_MASK     0x8000U
  #define INTC_IRQP0_PENDING_MASK       0xFFFEU
  #define INTC_IRQP0_PENDING_BITNUM     0x01U
  #define INTC_IRQP0                    (*((volatile word *)0x0000E314))


  /*** INTC_IRQP1 - IRQ Pending Register 1; 0x0000E315 ***/
  union {
    word Word;
  } INTC_IRQP1_STR;

  #define INTC_IRQP1                    (*((volatile word *)0x0000E315))


  /*** INTC_IRQP2 - IRQ Pending Register 2; 0x0000E316 ***/
  union {
    word Word;
  } INTC_IRQP2_STR;

  #define INTC_IRQP2                    (*((volatile word *)0x0000E316))


  /*** INTC_IRQP3 - IRQ Pending Register 3; 0x0000E317 ***/
  union {
    word Word;
  } INTC_IRQP3_STR;

  #define INTC_IRQP3                    (*((volatile word *)0x0000E317))


  /*** INTC_IRQP4 - IRQ Pending Register 4; 0x0000E318 ***/
  union {
    word Word;
  } INTC_IRQP4_STR;

  #define INTC_IRQP4                    (*((volatile word *)0x0000E318))


  /*** INTC_IRQP5 - IRQ Pending Register 5; 0x0000E319 ***/
  union {
    word Word;
  } INTC_IRQP5_STR;

  #define INTC_IRQP5                    (*((volatile word *)0x0000E319))


  /*** INTC_IRQP6 - IRQ Pending Register 6; 0x0000E31A ***/
  union {
    word Word;
  } INTC_IRQP6_STR;

  #define INTC_IRQP6_PENDING0_MASK      0x01U
  #define INTC_IRQP6_PENDING1_MASK      0x02U
  #define INTC_IRQP6_PENDING2_MASK      0x04U
  #define INTC_IRQP6_PENDING3_MASK      0x08U
  #define INTC_IRQP6_PENDING4_MASK      0x10U
  #define INTC_IRQP6_PENDING5_MASK      0x20U
  #define INTC_IRQP6_PENDING6_MASK      0x40U
  #define INTC_IRQP6_PENDING7_MASK      0x80U
  #define INTC_IRQP6_PENDING8_MASK      0x0100U
  #define INTC_IRQP6_PENDING9_MASK      0x0200U
  #define INTC_IRQP6_PENDING10_MASK     0x0400U
  #define INTC_IRQP6_PENDING11_MASK     0x0800U
  #define INTC_IRQP6_PENDING12_MASK     0x1000U
  #define INTC_IRQP6_PENDING13_MASK     0x2000U
  #define INTC_IRQP6_PENDING_MASK       0x3FFFU
  #define INTC_IRQP6_PENDING_BITNUM     0x00U
  #define INTC_IRQP6                    (*((volatile word *)0x0000E31A))


  /*** INTC_CTRL - Control Register; 0x0000E31B ***/
  union {
    word Word;
  } INTC_CTRL_STR;

  #define INTC_CTRL_INT_DIS_MASK        0x20U
  #define INTC_CTRL_VAB0_MASK           0x40U
  #define INTC_CTRL_VAB1_MASK           0x80U
  #define INTC_CTRL_VAB2_MASK           0x0100U
  #define INTC_CTRL_VAB3_MASK           0x0200U
  #define INTC_CTRL_VAB4_MASK           0x0400U
  #define INTC_CTRL_VAB5_MASK           0x0800U
  #define INTC_CTRL_VAB6_MASK           0x1000U
  #define INTC_CTRL_IPIC0_MASK          0x2000U
  #define INTC_CTRL_IPIC1_MASK          0x4000U
  #define INTC_CTRL_INT_MASK            0x8000U
  #define INTC_CTRL_VAB_MASK            0x1FC0U
  #define INTC_CTRL_VAB_BITNUM          0x06U
  #define INTC_CTRL_IPIC_MASK           0x6000U
  #define INTC_CTRL_IPIC_BITNUM         0x0DU
  #define INTC_CTRL                     (*((volatile word *)0x0000E31B))


} INTC_PRPH;
/******************************************
*** Peripheral COP
*******************************************/
typedef volatile struct {
  /*** COP_CTRL - COP Control Register; 0x0000E320 ***/
  union {
    word Word;
  } COP_CTRL_STR;

  #define COP_CTRL_CWP_MASK             0x01U
  #define COP_CTRL_CEN_MASK             0x02U
  #define COP_CTRL_CWEN_MASK            0x04U
  #define COP_CTRL_CSEN_MASK            0x08U
  #define COP_CTRL_CLOREN_MASK          0x10U
  #define COP_CTRL_CLKSEL0_MASK         0x20U
  #define COP_CTRL_CLKSEL1_MASK         0x40U
  #define COP_CTRL_INTEN_MASK           0x80U
  #define COP_CTRL_PSS0_MASK            0x0100U
  #define COP_CTRL_PSS1_MASK            0x0200U
  #define COP_CTRL_CLKSEL_MASK          0x60U
  #define COP_CTRL_CLKSEL_BITNUM        0x05U
  #define COP_CTRL_PSS_MASK             0x0300U
  #define COP_CTRL_PSS_BITNUM           0x08U
  #define COP_CTRL                      (*((volatile word *)0x0000E320))


  /*** COP_TOUT - COP Timeout Register; 0x0000E321 ***/
  union {
    word Word;
  } COP_TOUT_STR;

  #define COP_TOUT                      (*((volatile word *)0x0000E321))


  /*** COP_CNTR - COP Counter Register; 0x0000E322 ***/
  union {
    word Word;
  } COP_CNTR_STR;

  #define COP_CNTR                      (*((volatile word *)0x0000E322))


  /*** COP_INTVAL - COP Interrupt Value Register; 0x0000E323 ***/
  union {
    word Word;
  } COP_INTVAL_STR;

  #define COP_INTVAL                    (*((volatile word *)0x0000E323))


} COP_PRPH;
/******************************************
*** Peripheral EWM
*******************************************/
typedef volatile struct {
  /*** EWM_CTRL - Control Register; 0x0000E330 ***/
  union {
    word Word;
  } EWM_CTRL_STR;

  #define EWM_CTRL_EWMEN_MASK           0x01U
  #define EWM_CTRL_ASSIN_MASK           0x02U
  #define EWM_CTRL_INEN_MASK            0x04U
  #define EWM_CTRL_INTEN_MASK           0x08U
  #define EWM_CTRL                      (*((volatile word *)0x0000E330))


  /*** EWM_SERV - Service Register; 0x0000E331 ***/
  union {
    word Word;
  } EWM_SERV_STR;

  #define EWM_SERV_SERVICE0_MASK        0x01U
  #define EWM_SERV_SERVICE1_MASK        0x02U
  #define EWM_SERV_SERVICE2_MASK        0x04U
  #define EWM_SERV_SERVICE3_MASK        0x08U
  #define EWM_SERV_SERVICE4_MASK        0x10U
  #define EWM_SERV_SERVICE5_MASK        0x20U
  #define EWM_SERV_SERVICE6_MASK        0x40U
  #define EWM_SERV_SERVICE7_MASK        0x80U
  #define EWM_SERV_SERVICE_MASK         0xFFU
  #define EWM_SERV_SERVICE_BITNUM       0x00U
  #define EWM_SERV                      (*((volatile word *)0x0000E331))


  /*** EWM_CMPL - Compare Low Register; 0x0000E332 ***/
  union {
    word Word;
  } EWM_CMPL_STR;

  #define EWM_CMPL_COMPAREL0_MASK       0x01U
  #define EWM_CMPL_COMPAREL1_MASK       0x02U
  #define EWM_CMPL_COMPAREL2_MASK       0x04U
  #define EWM_CMPL_COMPAREL3_MASK       0x08U
  #define EWM_CMPL_COMPAREL4_MASK       0x10U
  #define EWM_CMPL_COMPAREL5_MASK       0x20U
  #define EWM_CMPL_COMPAREL6_MASK       0x40U
  #define EWM_CMPL_COMPAREL7_MASK       0x80U
  #define EWM_CMPL_COMPAREL_MASK        0xFFU
  #define EWM_CMPL_COMPAREL_BITNUM      0x00U
  #define EWM_CMPL                      (*((volatile word *)0x0000E332))


  /*** EWM_CMPH - Compare High Register; 0x0000E333 ***/
  union {
    word Word;
  } EWM_CMPH_STR;

  #define EWM_CMPH_COMPAREH0_MASK       0x01U
  #define EWM_CMPH_COMPAREH1_MASK       0x02U
  #define EWM_CMPH_COMPAREH2_MASK       0x04U
  #define EWM_CMPH_COMPAREH3_MASK       0x08U
  #define EWM_CMPH_COMPAREH4_MASK       0x10U
  #define EWM_CMPH_COMPAREH5_MASK       0x20U
  #define EWM_CMPH_COMPAREH6_MASK       0x40U
  #define EWM_CMPH_COMPAREH7_MASK       0x80U
  #define EWM_CMPH_COMPAREH_MASK        0xFFU
  #define EWM_CMPH_COMPAREH_BITNUM      0x00U
  #define EWM_CMPH                      (*((volatile word *)0x0000E333))


  /*** EWM_CLKCTRL - Clock Control Register; 0x0000E334 ***/
  union {
    word Word;
  } EWM_CLKCTRL_STR;

  #define EWM_CLKCTRL_CLKSEL0_MASK      0x01U
  #define EWM_CLKCTRL_CLKSEL1_MASK      0x02U
  #define EWM_CLKCTRL_CLKSEL_MASK       0x03U
  #define EWM_CLKCTRL_CLKSEL_BITNUM     0x00U
  #define EWM_CLKCTRL                   (*((volatile word *)0x0000E334))


  /*** EWM_CLKPRESCALER - Clock Prescaler Register; 0x0000E335 ***/
  union {
    word Word;
  } EWM_CLKPRESCALER_STR;

  #define EWM_CLKPRESCALER_CLK_DIV0_MASK 0x01U
  #define EWM_CLKPRESCALER_CLK_DIV1_MASK 0x02U
  #define EWM_CLKPRESCALER_CLK_DIV2_MASK 0x04U
  #define EWM_CLKPRESCALER_CLK_DIV3_MASK 0x08U
  #define EWM_CLKPRESCALER_CLK_DIV4_MASK 0x10U
  #define EWM_CLKPRESCALER_CLK_DIV5_MASK 0x20U
  #define EWM_CLKPRESCALER_CLK_DIV6_MASK 0x40U
  #define EWM_CLKPRESCALER_CLK_DIV7_MASK 0x80U
  #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFU
  #define EWM_CLKPRESCALER_CLK_DIV_BITNUM 0x00U
  #define EWM_CLKPRESCALER              (*((volatile word *)0x0000E335))


} EWM_PRPH;
/******************************************
*** Peripheral XBARA
*******************************************/
typedef volatile struct {
  /*** XBARA_SEL0 - Crossbar A Select Register 0; 0x0000E340 ***/
  union {
    word Word;
  } XBARA_SEL0_STR;

  #define XBARA_SEL0_SEL00_MASK         0x01U
  #define XBARA_SEL0_SEL01_MASK         0x02U
  #define XBARA_SEL0_SEL02_MASK         0x04U
  #define XBARA_SEL0_SEL03_MASK         0x08U
  #define XBARA_SEL0_SEL04_MASK         0x10U
  #define XBARA_SEL0_SEL05_MASK         0x20U
  #define XBARA_SEL0_SEL10_MASK         0x0100U
  #define XBARA_SEL0_SEL11_MASK         0x0200U
  #define XBARA_SEL0_SEL12_MASK         0x0400U
  #define XBARA_SEL0_SEL13_MASK         0x0800U
  #define XBARA_SEL0_SEL14_MASK         0x1000U
  #define XBARA_SEL0_SEL15_MASK         0x2000U
  #define XBARA_SEL0_SEL0_MASK          0x3FU
  #define XBARA_SEL0_SEL0_BITNUM        0x00U
  #define XBARA_SEL0_SEL1_MASK          0x3F00U
  #define XBARA_SEL0_SEL1_BITNUM        0x08U
  #define XBARA_SEL0                    (*((volatile word *)0x0000E340))


  /*** XBARA_SEL1 - Crossbar A Select Register 1; 0x0000E341 ***/
  union {
    word Word;
  } XBARA_SEL1_STR;

  #define XBARA_SEL1_SEL20_MASK         0x01U
  #define XBARA_SEL1_SEL21_MASK         0x02U
  #define XBARA_SEL1_SEL22_MASK         0x04U
  #define XBARA_SEL1_SEL23_MASK         0x08U
  #define XBARA_SEL1_SEL24_MASK         0x10U
  #define XBARA_SEL1_SEL25_MASK         0x20U
  #define XBARA_SEL1_SEL30_MASK         0x0100U
  #define XBARA_SEL1_SEL31_MASK         0x0200U
  #define XBARA_SEL1_SEL32_MASK         0x0400U
  #define XBARA_SEL1_SEL33_MASK         0x0800U
  #define XBARA_SEL1_SEL34_MASK         0x1000U
  #define XBARA_SEL1_SEL35_MASK         0x2000U
  #define XBARA_SEL1_SEL2_MASK          0x3FU
  #define XBARA_SEL1_SEL2_BITNUM        0x00U
  #define XBARA_SEL1_SEL3_MASK          0x3F00U
  #define XBARA_SEL1_SEL3_BITNUM        0x08U
  #define XBARA_SEL1                    (*((volatile word *)0x0000E341))


  /*** XBARA_SEL2 - Crossbar A Select Register 2; 0x0000E342 ***/
  union {
    word Word;
  } XBARA_SEL2_STR;

  #define XBARA_SEL2_SEL40_MASK         0x01U
  #define XBARA_SEL2_SEL41_MASK         0x02U
  #define XBARA_SEL2_SEL42_MASK         0x04U
  #define XBARA_SEL2_SEL43_MASK         0x08U
  #define XBARA_SEL2_SEL44_MASK         0x10U
  #define XBARA_SEL2_SEL45_MASK         0x20U
  #define XBARA_SEL2_SEL50_MASK         0x0100U
  #define XBARA_SEL2_SEL51_MASK         0x0200U
  #define XBARA_SEL2_SEL52_MASK         0x0400U
  #define XBARA_SEL2_SEL53_MASK         0x0800U
  #define XBARA_SEL2_SEL54_MASK         0x1000U
  #define XBARA_SEL2_SEL55_MASK         0x2000U
  #define XBARA_SEL2_SEL4_MASK          0x3FU
  #define XBARA_SEL2_SEL4_BITNUM        0x00U
  #define XBARA_SEL2_SEL5_MASK          0x3F00U
  #define XBARA_SEL2_SEL5_BITNUM        0x08U
  #define XBARA_SEL2                    (*((volatile word *)0x0000E342))


  /*** XBARA_SEL3 - Crossbar A Select Register 3; 0x0000E343 ***/
  union {
    word Word;
  } XBARA_SEL3_STR;

  #define XBARA_SEL3_SEL60_MASK         0x01U
  #define XBARA_SEL3_SEL61_MASK         0x02U
  #define XBARA_SEL3_SEL62_MASK         0x04U
  #define XBARA_SEL3_SEL63_MASK         0x08U
  #define XBARA_SEL3_SEL64_MASK         0x10U
  #define XBARA_SEL3_SEL65_MASK         0x20U
  #define XBARA_SEL3_SEL70_MASK         0x0100U
  #define XBARA_SEL3_SEL71_MASK         0x0200U
  #define XBARA_SEL3_SEL72_MASK         0x0400U
  #define XBARA_SEL3_SEL73_MASK         0x0800U
  #define XBARA_SEL3_SEL74_MASK         0x1000U
  #define XBARA_SEL3_SEL75_MASK         0x2000U
  #define XBARA_SEL3_SEL6_MASK          0x3FU
  #define XBARA_SEL3_SEL6_BITNUM        0x00U
  #define XBARA_SEL3_SEL7_MASK          0x3F00U
  #define XBARA_SEL3_SEL7_BITNUM        0x08U
  #define XBARA_SEL3                    (*((volatile word *)0x0000E343))


  /*** XBARA_SEL4 - Crossbar A Select Register 4; 0x0000E344 ***/
  union {
    word Word;
  } XBARA_SEL4_STR;

  #define XBARA_SEL4_SEL80_MASK         0x01U
  #define XBARA_SEL4_SEL81_MASK         0x02U
  #define XBARA_SEL4_SEL82_MASK         0x04U
  #define XBARA_SEL4_SEL83_MASK         0x08U
  #define XBARA_SEL4_SEL84_MASK         0x10U
  #define XBARA_SEL4_SEL85_MASK         0x20U
  #define XBARA_SEL4_SEL90_MASK         0x0100U
  #define XBARA_SEL4_SEL91_MASK         0x0200U
  #define XBARA_SEL4_SEL92_MASK         0x0400U
  #define XBARA_SEL4_SEL93_MASK         0x0800U
  #define XBARA_SEL4_SEL94_MASK         0x1000U
  #define XBARA_SEL4_SEL95_MASK         0x2000U
  #define XBARA_SEL4_SEL8_MASK          0x3FU
  #define XBARA_SEL4_SEL8_BITNUM        0x00U
  #define XBARA_SEL4_SEL9_MASK          0x3F00U
  #define XBARA_SEL4_SEL9_BITNUM        0x08U
  #define XBARA_SEL4                    (*((volatile word *)0x0000E344))


  /*** XBARA_SEL5 - Crossbar A Select Register 5; 0x0000E345 ***/
  union {
    word Word;
  } XBARA_SEL5_STR;

  #define XBARA_SEL5_SEL100_MASK        0x01U
  #define XBARA_SEL5_SEL101_MASK        0x02U
  #define XBARA_SEL5_SEL102_MASK        0x04U
  #define XBARA_SEL5_SEL103_MASK        0x08U
  #define XBARA_SEL5_SEL104_MASK        0x10U
  #define XBARA_SEL5_SEL105_MASK        0x20U
  #define XBARA_SEL5_SEL110_MASK        0x0100U
  #define XBARA_SEL5_SEL111_MASK        0x0200U
  #define XBARA_SEL5_SEL112_MASK        0x0400U
  #define XBARA_SEL5_SEL113_MASK        0x0800U
  #define XBARA_SEL5_SEL114_MASK        0x1000U
  #define XBARA_SEL5_SEL115_MASK        0x2000U
  #define XBARA_SEL5_SEL10_MASK         0x3FU
  #define XBARA_SEL5_SEL10_BITNUM       0x00U
  #define XBARA_SEL5_SEL11_MASK         0x3F00U
  #define XBARA_SEL5_SEL11_BITNUM       0x08U
  #define XBARA_SEL5                    (*((volatile word *)0x0000E345))


  /*** XBARA_SEL6 - Crossbar A Select Register 6; 0x0000E346 ***/
  union {
    word Word;
  } XBARA_SEL6_STR;

  #define XBARA_SEL6_SEL120_MASK        0x01U
  #define XBARA_SEL6_SEL121_MASK        0x02U
  #define XBARA_SEL6_SEL122_MASK        0x04U
  #define XBARA_SEL6_SEL123_MASK        0x08U
  #define XBARA_SEL6_SEL124_MASK        0x10U
  #define XBARA_SEL6_SEL125_MASK        0x20U
  #define XBARA_SEL6_SEL130_MASK        0x0100U
  #define XBARA_SEL6_SEL131_MASK        0x0200U
  #define XBARA_SEL6_SEL132_MASK        0x0400U
  #define XBARA_SEL6_SEL133_MASK        0x0800U
  #define XBARA_SEL6_SEL134_MASK        0x1000U
  #define XBARA_SEL6_SEL135_MASK        0x2000U
  #define XBARA_SEL6_SEL12_MASK         0x3FU
  #define XBARA_SEL6_SEL12_BITNUM       0x00U
  #define XBARA_SEL6_SEL13_MASK         0x3F00U
  #define XBARA_SEL6_SEL13_BITNUM       0x08U
  #define XBARA_SEL6                    (*((volatile word *)0x0000E346))


  /*** XBARA_SEL7 - Crossbar A Select Register 7; 0x0000E347 ***/
  union {
    word Word;
  } XBARA_SEL7_STR;

  #define XBARA_SEL7_SEL140_MASK        0x01U
  #define XBARA_SEL7_SEL141_MASK        0x02U
  #define XBARA_SEL7_SEL142_MASK        0x04U
  #define XBARA_SEL7_SEL143_MASK        0x08U
  #define XBARA_SEL7_SEL144_MASK        0x10U
  #define XBARA_SEL7_SEL145_MASK        0x20U
  #define XBARA_SEL7_SEL150_MASK        0x0100U
  #define XBARA_SEL7_SEL151_MASK        0x0200U
  #define XBARA_SEL7_SEL152_MASK        0x0400U
  #define XBARA_SEL7_SEL153_MASK        0x0800U
  #define XBARA_SEL7_SEL154_MASK        0x1000U
  #define XBARA_SEL7_SEL155_MASK        0x2000U
  #define XBARA_SEL7_SEL14_MASK         0x3FU
  #define XBARA_SEL7_SEL14_BITNUM       0x00U
  #define XBARA_SEL7_SEL15_MASK         0x3F00U
  #define XBARA_SEL7_SEL15_BITNUM       0x08U
  #define XBARA_SEL7                    (*((volatile word *)0x0000E347))


  /*** XBARA_SEL8 - Crossbar A Select Register 8; 0x0000E348 ***/
  union {
    word Word;
  } XBARA_SEL8_STR;

  #define XBARA_SEL8_SEL160_MASK        0x01U
  #define XBARA_SEL8_SEL161_MASK        0x02U
  #define XBARA_SEL8_SEL162_MASK        0x04U
  #define XBARA_SEL8_SEL163_MASK        0x08U
  #define XBARA_SEL8_SEL164_MASK        0x10U
  #define XBARA_SEL8_SEL165_MASK        0x20U
  #define XBARA_SEL8_SEL170_MASK        0x0100U
  #define XBARA_SEL8_SEL171_MASK        0x0200U
  #define XBARA_SEL8_SEL172_MASK        0x0400U
  #define XBARA_SEL8_SEL173_MASK        0x0800U
  #define XBARA_SEL8_SEL174_MASK        0x1000U
  #define XBARA_SEL8_SEL175_MASK        0x2000U
  #define XBARA_SEL8_SEL16_MASK         0x3FU
  #define XBARA_SEL8_SEL16_BITNUM       0x00U
  #define XBARA_SEL8_SEL17_MASK         0x3F00U
  #define XBARA_SEL8_SEL17_BITNUM       0x08U
  #define XBARA_SEL8                    (*((volatile word *)0x0000E348))


  /*** XBARA_SEL9 - Crossbar A Select Register 9; 0x0000E349 ***/
  union {
    word Word;
  } XBARA_SEL9_STR;

  #define XBARA_SEL9_SEL180_MASK        0x01U
  #define XBARA_SEL9_SEL181_MASK        0x02U
  #define XBARA_SEL9_SEL182_MASK        0x04U
  #define XBARA_SEL9_SEL183_MASK        0x08U
  #define XBARA_SEL9_SEL184_MASK        0x10U
  #define XBARA_SEL9_SEL185_MASK        0x20U
  #define XBARA_SEL9_SEL190_MASK        0x0100U
  #define XBARA_SEL9_SEL191_MASK        0x0200U
  #define XBARA_SEL9_SEL192_MASK        0x0400U
  #define XBARA_SEL9_SEL193_MASK        0x0800U
  #define XBARA_SEL9_SEL194_MASK        0x1000U
  #define XBARA_SEL9_SEL195_MASK        0x2000U
  #define XBARA_SEL9_SEL18_MASK         0x3FU
  #define XBARA_SEL9_SEL18_BITNUM       0x00U
  #define XBARA_SEL9_SEL19_MASK         0x3F00U
  #define XBARA_SEL9_SEL19_BITNUM       0x08U
  #define XBARA_SEL9                    (*((volatile word *)0x0000E349))


  /*** XBARA_SEL10 - Crossbar A Select Register 10; 0x0000E34A ***/
  union {
    word Word;
  } XBARA_SEL10_STR;

  #define XBARA_SEL10_SEL200_MASK       0x01U
  #define XBARA_SEL10_SEL201_MASK       0x02U
  #define XBARA_SEL10_SEL202_MASK       0x04U
  #define XBARA_SEL10_SEL203_MASK       0x08U
  #define XBARA_SEL10_SEL204_MASK       0x10U
  #define XBARA_SEL10_SEL205_MASK       0x20U
  #define XBARA_SEL10_SEL210_MASK       0x0100U
  #define XBARA_SEL10_SEL211_MASK       0x0200U
  #define XBARA_SEL10_SEL212_MASK       0x0400U
  #define XBARA_SEL10_SEL213_MASK       0x0800U
  #define XBARA_SEL10_SEL214_MASK       0x1000U
  #define XBARA_SEL10_SEL215_MASK       0x2000U
  #define XBARA_SEL10_SEL20_MASK        0x3FU
  #define XBARA_SEL10_SEL20_BITNUM      0x00U
  #define XBARA_SEL10_SEL21_MASK        0x3F00U
  #define XBARA_SEL10_SEL21_BITNUM      0x08U
  #define XBARA_SEL10                   (*((volatile word *)0x0000E34A))


  /*** XBARA_SEL11 - Crossbar A Select Register 11; 0x0000E34B ***/
  union {
    word Word;
  } XBARA_SEL11_STR;

  #define XBARA_SEL11_SEL220_MASK       0x01U
  #define XBARA_SEL11_SEL221_MASK       0x02U
  #define XBARA_SEL11_SEL222_MASK       0x04U
  #define XBARA_SEL11_SEL223_MASK       0x08U
  #define XBARA_SEL11_SEL224_MASK       0x10U
  #define XBARA_SEL11_SEL225_MASK       0x20U
  #define XBARA_SEL11_SEL230_MASK       0x0100U
  #define XBARA_SEL11_SEL231_MASK       0x0200U
  #define XBARA_SEL11_SEL232_MASK       0x0400U
  #define XBARA_SEL11_SEL233_MASK       0x0800U
  #define XBARA_SEL11_SEL234_MASK       0x1000U
  #define XBARA_SEL11_SEL235_MASK       0x2000U
  #define XBARA_SEL11_SEL22_MASK        0x3FU
  #define XBARA_SEL11_SEL22_BITNUM      0x00U
  #define XBARA_SEL11_SEL23_MASK        0x3F00U
  #define XBARA_SEL11_SEL23_BITNUM      0x08U
  #define XBARA_SEL11                   (*((volatile word *)0x0000E34B))


  /*** XBARA_SEL12 - Crossbar A Select Register 12; 0x0000E34C ***/
  union {
    word Word;
  } XBARA_SEL12_STR;

  #define XBARA_SEL12_SEL240_MASK       0x01U
  #define XBARA_SEL12_SEL241_MASK       0x02U
  #define XBARA_SEL12_SEL242_MASK       0x04U
  #define XBARA_SEL12_SEL243_MASK       0x08U
  #define XBARA_SEL12_SEL244_MASK       0x10U
  #define XBARA_SEL12_SEL245_MASK       0x20U
  #define XBARA_SEL12_SEL250_MASK       0x0100U
  #define XBARA_SEL12_SEL251_MASK       0x0200U
  #define XBARA_SEL12_SEL252_MASK       0x0400U
  #define XBARA_SEL12_SEL253_MASK       0x0800U
  #define XBARA_SEL12_SEL254_MASK       0x1000U
  #define XBARA_SEL12_SEL255_MASK       0x2000U
  #define XBARA_SEL12_SEL24_MASK        0x3FU
  #define XBARA_SEL12_SEL24_BITNUM      0x00U
  #define XBARA_SEL12_SEL25_MASK        0x3F00U
  #define XBARA_SEL12_SEL25_BITNUM      0x08U
  #define XBARA_SEL12                   (*((volatile word *)0x0000E34C))


  /*** XBARA_SEL13 - Crossbar A Select Register 13; 0x0000E34D ***/
  union {
    word Word;
  } XBARA_SEL13_STR;

  #define XBARA_SEL13_SEL260_MASK       0x01U
  #define XBARA_SEL13_SEL261_MASK       0x02U
  #define XBARA_SEL13_SEL262_MASK       0x04U
  #define XBARA_SEL13_SEL263_MASK       0x08U
  #define XBARA_SEL13_SEL264_MASK       0x10U
  #define XBARA_SEL13_SEL265_MASK       0x20U
  #define XBARA_SEL13_SEL270_MASK       0x0100U
  #define XBARA_SEL13_SEL271_MASK       0x0200U
  #define XBARA_SEL13_SEL272_MASK       0x0400U
  #define XBARA_SEL13_SEL273_MASK       0x0800U
  #define XBARA_SEL13_SEL274_MASK       0x1000U
  #define XBARA_SEL13_SEL275_MASK       0x2000U
  #define XBARA_SEL13_SEL26_MASK        0x3FU
  #define XBARA_SEL13_SEL26_BITNUM      0x00U
  #define XBARA_SEL13_SEL27_MASK        0x3F00U
  #define XBARA_SEL13_SEL27_BITNUM      0x08U
  #define XBARA_SEL13                   (*((volatile word *)0x0000E34D))


  /*** XBARA_SEL14 - Crossbar A Select Register 14; 0x0000E34E ***/
  union {
    word Word;
  } XBARA_SEL14_STR;

  #define XBARA_SEL14_SEL280_MASK       0x01U
  #define XBARA_SEL14_SEL281_MASK       0x02U
  #define XBARA_SEL14_SEL282_MASK       0x04U
  #define XBARA_SEL14_SEL283_MASK       0x08U
  #define XBARA_SEL14_SEL284_MASK       0x10U
  #define XBARA_SEL14_SEL285_MASK       0x20U
  #define XBARA_SEL14_SEL290_MASK       0x0100U
  #define XBARA_SEL14_SEL291_MASK       0x0200U
  #define XBARA_SEL14_SEL292_MASK       0x0400U
  #define XBARA_SEL14_SEL293_MASK       0x0800U
  #define XBARA_SEL14_SEL294_MASK       0x1000U
  #define XBARA_SEL14_SEL295_MASK       0x2000U
  #define XBARA_SEL14_SEL28_MASK        0x3FU
  #define XBARA_SEL14_SEL28_BITNUM      0x00U
  #define XBARA_SEL14_SEL29_MASK        0x3F00U
  #define XBARA_SEL14_SEL29_BITNUM      0x08U
  #define XBARA_SEL14                   (*((volatile word *)0x0000E34E))


  /*** XBARA_SEL15 - Crossbar A Select Register 15; 0x0000E34F ***/
  union {
    word Word;
  } XBARA_SEL15_STR;

  #define XBARA_SEL15_SEL300_MASK       0x01U
  #define XBARA_SEL15_SEL301_MASK       0x02U
  #define XBARA_SEL15_SEL302_MASK       0x04U
  #define XBARA_SEL15_SEL303_MASK       0x08U
  #define XBARA_SEL15_SEL304_MASK       0x10U
  #define XBARA_SEL15_SEL305_MASK       0x20U
  #define XBARA_SEL15_SEL310_MASK       0x0100U
  #define XBARA_SEL15_SEL311_MASK       0x0200U
  #define XBARA_SEL15_SEL312_MASK       0x0400U
  #define XBARA_SEL15_SEL313_MASK       0x0800U
  #define XBARA_SEL15_SEL314_MASK       0x1000U
  #define XBARA_SEL15_SEL315_MASK       0x2000U
  #define XBARA_SEL15_SEL30_MASK        0x3FU
  #define XBARA_SEL15_SEL30_BITNUM      0x00U
  #define XBARA_SEL15_SEL31_MASK        0x3F00U
  #define XBARA_SEL15_SEL31_BITNUM      0x08U
  #define XBARA_SEL15                   (*((volatile word *)0x0000E34F))


  /*** XBARA_SEL16 - Crossbar A Select Register 16; 0x0000E350 ***/
  union {
    word Word;
  } XBARA_SEL16_STR;

  #define XBARA_SEL16_SEL320_MASK       0x01U
  #define XBARA_SEL16_SEL321_MASK       0x02U
  #define XBARA_SEL16_SEL322_MASK       0x04U
  #define XBARA_SEL16_SEL323_MASK       0x08U
  #define XBARA_SEL16_SEL324_MASK       0x10U
  #define XBARA_SEL16_SEL325_MASK       0x20U
  #define XBARA_SEL16_SEL330_MASK       0x0100U
  #define XBARA_SEL16_SEL331_MASK       0x0200U
  #define XBARA_SEL16_SEL332_MASK       0x0400U
  #define XBARA_SEL16_SEL333_MASK       0x0800U
  #define XBARA_SEL16_SEL334_MASK       0x1000U
  #define XBARA_SEL16_SEL335_MASK       0x2000U
  #define XBARA_SEL16_SEL32_MASK        0x3FU
  #define XBARA_SEL16_SEL32_BITNUM      0x00U
  #define XBARA_SEL16_SEL33_MASK        0x3F00U
  #define XBARA_SEL16_SEL33_BITNUM      0x08U
  #define XBARA_SEL16                   (*((volatile word *)0x0000E350))


  /*** XBARA_SEL17 - Crossbar A Select Register 17; 0x0000E351 ***/
  union {
    word Word;
  } XBARA_SEL17_STR;

  #define XBARA_SEL17_SEL340_MASK       0x01U
  #define XBARA_SEL17_SEL341_MASK       0x02U
  #define XBARA_SEL17_SEL342_MASK       0x04U
  #define XBARA_SEL17_SEL343_MASK       0x08U
  #define XBARA_SEL17_SEL344_MASK       0x10U
  #define XBARA_SEL17_SEL345_MASK       0x20U
  #define XBARA_SEL17_SEL350_MASK       0x0100U
  #define XBARA_SEL17_SEL351_MASK       0x0200U
  #define XBARA_SEL17_SEL352_MASK       0x0400U
  #define XBARA_SEL17_SEL353_MASK       0x0800U
  #define XBARA_SEL17_SEL354_MASK       0x1000U
  #define XBARA_SEL17_SEL355_MASK       0x2000U
  #define XBARA_SEL17_SEL34_MASK        0x3FU
  #define XBARA_SEL17_SEL34_BITNUM      0x00U
  #define XBARA_SEL17_SEL35_MASK        0x3F00U
  #define XBARA_SEL17_SEL35_BITNUM      0x08U
  #define XBARA_SEL17                   (*((volatile word *)0x0000E351))


  /*** XBARA_SEL18 - Crossbar A Select Register 18; 0x0000E352 ***/
  union {
    word Word;
  } XBARA_SEL18_STR;

  #define XBARA_SEL18_SEL360_MASK       0x01U
  #define XBARA_SEL18_SEL361_MASK       0x02U
  #define XBARA_SEL18_SEL362_MASK       0x04U
  #define XBARA_SEL18_SEL363_MASK       0x08U
  #define XBARA_SEL18_SEL364_MASK       0x10U
  #define XBARA_SEL18_SEL365_MASK       0x20U
  #define XBARA_SEL18_SEL370_MASK       0x0100U
  #define XBARA_SEL18_SEL371_MASK       0x0200U
  #define XBARA_SEL18_SEL372_MASK       0x0400U
  #define XBARA_SEL18_SEL373_MASK       0x0800U
  #define XBARA_SEL18_SEL374_MASK       0x1000U
  #define XBARA_SEL18_SEL375_MASK       0x2000U
  #define XBARA_SEL18_SEL36_MASK        0x3FU
  #define XBARA_SEL18_SEL36_BITNUM      0x00U
  #define XBARA_SEL18_SEL37_MASK        0x3F00U
  #define XBARA_SEL18_SEL37_BITNUM      0x08U
  #define XBARA_SEL18                   (*((volatile word *)0x0000E352))


  /*** XBARA_SEL19 - Crossbar A Select Register 19; 0x0000E353 ***/
  union {
    word Word;
  } XBARA_SEL19_STR;

  #define XBARA_SEL19_SEL380_MASK       0x01U
  #define XBARA_SEL19_SEL381_MASK       0x02U
  #define XBARA_SEL19_SEL382_MASK       0x04U
  #define XBARA_SEL19_SEL383_MASK       0x08U
  #define XBARA_SEL19_SEL384_MASK       0x10U
  #define XBARA_SEL19_SEL385_MASK       0x20U
  #define XBARA_SEL19_SEL390_MASK       0x0100U
  #define XBARA_SEL19_SEL391_MASK       0x0200U
  #define XBARA_SEL19_SEL392_MASK       0x0400U
  #define XBARA_SEL19_SEL393_MASK       0x0800U
  #define XBARA_SEL19_SEL394_MASK       0x1000U
  #define XBARA_SEL19_SEL395_MASK       0x2000U
  #define XBARA_SEL19_SEL38_MASK        0x3FU
  #define XBARA_SEL19_SEL38_BITNUM      0x00U
  #define XBARA_SEL19_SEL39_MASK        0x3F00U
  #define XBARA_SEL19_SEL39_BITNUM      0x08U
  #define XBARA_SEL19                   (*((volatile word *)0x0000E353))


  /*** XBARA_SEL20 - Crossbar A Select Register 20; 0x0000E354 ***/
  union {
    word Word;
  } XBARA_SEL20_STR;

  #define XBARA_SEL20_SEL400_MASK       0x01U
  #define XBARA_SEL20_SEL401_MASK       0x02U
  #define XBARA_SEL20_SEL402_MASK       0x04U
  #define XBARA_SEL20_SEL403_MASK       0x08U
  #define XBARA_SEL20_SEL404_MASK       0x10U
  #define XBARA_SEL20_SEL405_MASK       0x20U
  #define XBARA_SEL20_SEL410_MASK       0x0100U
  #define XBARA_SEL20_SEL411_MASK       0x0200U
  #define XBARA_SEL20_SEL412_MASK       0x0400U
  #define XBARA_SEL20_SEL413_MASK       0x0800U
  #define XBARA_SEL20_SEL414_MASK       0x1000U
  #define XBARA_SEL20_SEL415_MASK       0x2000U
  #define XBARA_SEL20_SEL40_MASK        0x3FU
  #define XBARA_SEL20_SEL40_BITNUM      0x00U
  #define XBARA_SEL20_SEL41_MASK        0x3F00U
  #define XBARA_SEL20_SEL41_BITNUM      0x08U
  #define XBARA_SEL20                   (*((volatile word *)0x0000E354))


  /*** XBARA_SEL21 - Crossbar A Select Register 21; 0x0000E355 ***/
  union {
    word Word;
  } XBARA_SEL21_STR;

  #define XBARA_SEL21_SEL420_MASK       0x01U
  #define XBARA_SEL21_SEL421_MASK       0x02U
  #define XBARA_SEL21_SEL422_MASK       0x04U
  #define XBARA_SEL21_SEL423_MASK       0x08U
  #define XBARA_SEL21_SEL424_MASK       0x10U
  #define XBARA_SEL21_SEL425_MASK       0x20U
  #define XBARA_SEL21_SEL430_MASK       0x0100U
  #define XBARA_SEL21_SEL431_MASK       0x0200U
  #define XBARA_SEL21_SEL432_MASK       0x0400U
  #define XBARA_SEL21_SEL433_MASK       0x0800U
  #define XBARA_SEL21_SEL434_MASK       0x1000U
  #define XBARA_SEL21_SEL435_MASK       0x2000U
  #define XBARA_SEL21_SEL42_MASK        0x3FU
  #define XBARA_SEL21_SEL42_BITNUM      0x00U
  #define XBARA_SEL21_SEL43_MASK        0x3F00U
  #define XBARA_SEL21_SEL43_BITNUM      0x08U
  #define XBARA_SEL21                   (*((volatile word *)0x0000E355))


  /*** XBARA_SEL22 - Crossbar A Select Register 22; 0x0000E356 ***/
  union {
    word Word;
  } XBARA_SEL22_STR;

  #define XBARA_SEL22_SEL440_MASK       0x01U
  #define XBARA_SEL22_SEL441_MASK       0x02U
  #define XBARA_SEL22_SEL442_MASK       0x04U
  #define XBARA_SEL22_SEL443_MASK       0x08U
  #define XBARA_SEL22_SEL444_MASK       0x10U
  #define XBARA_SEL22_SEL445_MASK       0x20U
  #define XBARA_SEL22_SEL450_MASK       0x0100U
  #define XBARA_SEL22_SEL451_MASK       0x0200U
  #define XBARA_SEL22_SEL452_MASK       0x0400U
  #define XBARA_SEL22_SEL453_MASK       0x0800U
  #define XBARA_SEL22_SEL454_MASK       0x1000U
  #define XBARA_SEL22_SEL455_MASK       0x2000U
  #define XBARA_SEL22_SEL44_MASK        0x3FU
  #define XBARA_SEL22_SEL44_BITNUM      0x00U
  #define XBARA_SEL22_SEL45_MASK        0x3F00U
  #define XBARA_SEL22_SEL45_BITNUM      0x08U
  #define XBARA_SEL22                   (*((volatile word *)0x0000E356))


  /*** XBARA_SEL23 - Crossbar A Select Register 23; 0x0000E357 ***/
  union {
    word Word;
  } XBARA_SEL23_STR;

  #define XBARA_SEL23_SEL460_MASK       0x01U
  #define XBARA_SEL23_SEL461_MASK       0x02U
  #define XBARA_SEL23_SEL462_MASK       0x04U
  #define XBARA_SEL23_SEL463_MASK       0x08U
  #define XBARA_SEL23_SEL464_MASK       0x10U
  #define XBARA_SEL23_SEL465_MASK       0x20U
  #define XBARA_SEL23_SEL470_MASK       0x0100U
  #define XBARA_SEL23_SEL471_MASK       0x0200U
  #define XBARA_SEL23_SEL472_MASK       0x0400U
  #define XBARA_SEL23_SEL473_MASK       0x0800U
  #define XBARA_SEL23_SEL474_MASK       0x1000U
  #define XBARA_SEL23_SEL475_MASK       0x2000U
  #define XBARA_SEL23_SEL46_MASK        0x3FU
  #define XBARA_SEL23_SEL46_BITNUM      0x00U
  #define XBARA_SEL23_SEL47_MASK        0x3F00U
  #define XBARA_SEL23_SEL47_BITNUM      0x08U
  #define XBARA_SEL23                   (*((volatile word *)0x0000E357))


  /*** XBARA_SEL24 - Crossbar A Select Register 24; 0x0000E358 ***/
  union {
    word Word;
  } XBARA_SEL24_STR;

  #define XBARA_SEL24_SEL480_MASK       0x01U
  #define XBARA_SEL24_SEL481_MASK       0x02U
  #define XBARA_SEL24_SEL482_MASK       0x04U
  #define XBARA_SEL24_SEL483_MASK       0x08U
  #define XBARA_SEL24_SEL484_MASK       0x10U
  #define XBARA_SEL24_SEL485_MASK       0x20U
  #define XBARA_SEL24_SEL490_MASK       0x0100U
  #define XBARA_SEL24_SEL491_MASK       0x0200U
  #define XBARA_SEL24_SEL492_MASK       0x0400U
  #define XBARA_SEL24_SEL493_MASK       0x0800U
  #define XBARA_SEL24_SEL494_MASK       0x1000U
  #define XBARA_SEL24_SEL495_MASK       0x2000U
  #define XBARA_SEL24_SEL48_MASK        0x3FU
  #define XBARA_SEL24_SEL48_BITNUM      0x00U
  #define XBARA_SEL24_SEL49_MASK        0x3F00U
  #define XBARA_SEL24_SEL49_BITNUM      0x08U
  #define XBARA_SEL24                   (*((volatile word *)0x0000E358))


  /*** XBARA_SEL25 - Crossbar A Select Register 25; 0x0000E359 ***/
  union {
    word Word;
  } XBARA_SEL25_STR;

  #define XBARA_SEL25_SEL500_MASK       0x01U
  #define XBARA_SEL25_SEL501_MASK       0x02U
  #define XBARA_SEL25_SEL502_MASK       0x04U
  #define XBARA_SEL25_SEL503_MASK       0x08U
  #define XBARA_SEL25_SEL504_MASK       0x10U
  #define XBARA_SEL25_SEL505_MASK       0x20U
  #define XBARA_SEL25_SEL510_MASK       0x0100U
  #define XBARA_SEL25_SEL511_MASK       0x0200U
  #define XBARA_SEL25_SEL512_MASK       0x0400U
  #define XBARA_SEL25_SEL513_MASK       0x0800U
  #define XBARA_SEL25_SEL514_MASK       0x1000U
  #define XBARA_SEL25_SEL515_MASK       0x2000U
  #define XBARA_SEL25_SEL50_MASK        0x3FU
  #define XBARA_SEL25_SEL50_BITNUM      0x00U
  #define XBARA_SEL25_SEL51_MASK        0x3F00U
  #define XBARA_SEL25_SEL51_BITNUM      0x08U
  #define XBARA_SEL25                   (*((volatile word *)0x0000E359))


  /*** XBARA_SEL26 - Crossbar A Select Register 26; 0x0000E35A ***/
  union {
    word Word;
  } XBARA_SEL26_STR;

  #define XBARA_SEL26_SEL520_MASK       0x01U
  #define XBARA_SEL26_SEL521_MASK       0x02U
  #define XBARA_SEL26_SEL522_MASK       0x04U
  #define XBARA_SEL26_SEL523_MASK       0x08U
  #define XBARA_SEL26_SEL524_MASK       0x10U
  #define XBARA_SEL26_SEL525_MASK       0x20U
  #define XBARA_SEL26_SEL530_MASK       0x0100U
  #define XBARA_SEL26_SEL531_MASK       0x0200U
  #define XBARA_SEL26_SEL532_MASK       0x0400U
  #define XBARA_SEL26_SEL533_MASK       0x0800U
  #define XBARA_SEL26_SEL534_MASK       0x1000U
  #define XBARA_SEL26_SEL535_MASK       0x2000U
  #define XBARA_SEL26_SEL52_MASK        0x3FU
  #define XBARA_SEL26_SEL52_BITNUM      0x00U
  #define XBARA_SEL26_SEL53_MASK        0x3F00U
  #define XBARA_SEL26_SEL53_BITNUM      0x08U
  #define XBARA_SEL26                   (*((volatile word *)0x0000E35A))


  /*** XBARA_SEL27 - Crossbar A Select Register 27; 0x0000E35B ***/
  union {
    word Word;
  } XBARA_SEL27_STR;

  #define XBARA_SEL27_SEL540_MASK       0x01U
  #define XBARA_SEL27_SEL541_MASK       0x02U
  #define XBARA_SEL27_SEL542_MASK       0x04U
  #define XBARA_SEL27_SEL543_MASK       0x08U
  #define XBARA_SEL27_SEL544_MASK       0x10U
  #define XBARA_SEL27_SEL545_MASK       0x20U
  #define XBARA_SEL27_SEL550_MASK       0x0100U
  #define XBARA_SEL27_SEL551_MASK       0x0200U
  #define XBARA_SEL27_SEL552_MASK       0x0400U
  #define XBARA_SEL27_SEL553_MASK       0x0800U
  #define XBARA_SEL27_SEL554_MASK       0x1000U
  #define XBARA_SEL27_SEL555_MASK       0x2000U
  #define XBARA_SEL27_SEL54_MASK        0x3FU
  #define XBARA_SEL27_SEL54_BITNUM      0x00U
  #define XBARA_SEL27_SEL55_MASK        0x3F00U
  #define XBARA_SEL27_SEL55_BITNUM      0x08U
  #define XBARA_SEL27                   (*((volatile word *)0x0000E35B))


  /*** XBARA_SEL28 - Crossbar A Select Register 28; 0x0000E35C ***/
  union {
    word Word;
  } XBARA_SEL28_STR;

  #define XBARA_SEL28_SEL560_MASK       0x01U
  #define XBARA_SEL28_SEL561_MASK       0x02U
  #define XBARA_SEL28_SEL562_MASK       0x04U
  #define XBARA_SEL28_SEL563_MASK       0x08U
  #define XBARA_SEL28_SEL564_MASK       0x10U
  #define XBARA_SEL28_SEL565_MASK       0x20U
  #define XBARA_SEL28_SEL570_MASK       0x0100U
  #define XBARA_SEL28_SEL571_MASK       0x0200U
  #define XBARA_SEL28_SEL572_MASK       0x0400U
  #define XBARA_SEL28_SEL573_MASK       0x0800U
  #define XBARA_SEL28_SEL574_MASK       0x1000U
  #define XBARA_SEL28_SEL575_MASK       0x2000U
  #define XBARA_SEL28_SEL56_MASK        0x3FU
  #define XBARA_SEL28_SEL56_BITNUM      0x00U
  #define XBARA_SEL28_SEL57_MASK        0x3F00U
  #define XBARA_SEL28_SEL57_BITNUM      0x08U
  #define XBARA_SEL28                   (*((volatile word *)0x0000E35C))


  /*** XBARA_SEL29 - Crossbar A Select Register 29; 0x0000E35D ***/
  union {
    word Word;
  } XBARA_SEL29_STR;

  #define XBARA_SEL29_SEL580_MASK       0x01U
  #define XBARA_SEL29_SEL581_MASK       0x02U
  #define XBARA_SEL29_SEL582_MASK       0x04U
  #define XBARA_SEL29_SEL583_MASK       0x08U
  #define XBARA_SEL29_SEL584_MASK       0x10U
  #define XBARA_SEL29_SEL585_MASK       0x20U
  #define XBARA_SEL29_SEL58_MASK        0x3FU
  #define XBARA_SEL29_SEL58_BITNUM      0x00U
  #define XBARA_SEL29                   (*((volatile word *)0x0000E35D))


  /*** XBARA_CTRL0 - Crossbar A Control Register 0; 0x0000E35E ***/
  union {
    word Word;
  } XBARA_CTRL0_STR;

  #define XBARA_CTRL0_DEN0_MASK         0x01U
  #define XBARA_CTRL0_IEN0_MASK         0x02U
  #define XBARA_CTRL0_EDGE00_MASK       0x04U
  #define XBARA_CTRL0_EDGE01_MASK       0x08U
  #define XBARA_CTRL0_STS0_MASK         0x10U
  #define XBARA_CTRL0_DEN1_MASK         0x0100U
  #define XBARA_CTRL0_IEN1_MASK         0x0200U
  #define XBARA_CTRL0_EDGE10_MASK       0x0400U
  #define XBARA_CTRL0_EDGE11_MASK       0x0800U
  #define XBARA_CTRL0_STS1_MASK         0x1000U
  #define XBARA_CTRL0_EDGE0_MASK        0x0CU
  #define XBARA_CTRL0_EDGE0_BITNUM      0x02U
  #define XBARA_CTRL0_EDGE1_MASK        0x0C00U
  #define XBARA_CTRL0_EDGE1_BITNUM      0x0AU
  #define XBARA_CTRL0                   (*((volatile word *)0x0000E35E))


  /*** XBARA_CTRL1 - Crossbar A Control Register 1; 0x0000E35F ***/
  union {
    word Word;
  } XBARA_CTRL1_STR;

  #define XBARA_CTRL1_DEN2_MASK         0x01U
  #define XBARA_CTRL1_IEN2_MASK         0x02U
  #define XBARA_CTRL1_EDGE20_MASK       0x04U
  #define XBARA_CTRL1_EDGE21_MASK       0x08U
  #define XBARA_CTRL1_STS2_MASK         0x10U
  #define XBARA_CTRL1_DEN3_MASK         0x0100U
  #define XBARA_CTRL1_IEN3_MASK         0x0200U
  #define XBARA_CTRL1_EDGE30_MASK       0x0400U
  #define XBARA_CTRL1_EDGE31_MASK       0x0800U
  #define XBARA_CTRL1_STS3_MASK         0x1000U
  #define XBARA_CTRL1_EDGE2_MASK        0x0CU
  #define XBARA_CTRL1_EDGE2_BITNUM      0x02U
  #define XBARA_CTRL1_EDGE3_MASK        0x0C00U
  #define XBARA_CTRL1_EDGE3_BITNUM      0x0AU
  #define XBARA_CTRL1                   (*((volatile word *)0x0000E35F))


} XBARA_PRPH;
/******************************************
*** Peripheral XBARB
*******************************************/
typedef volatile struct {
  /*** XBARB_SEL0 - Crossbar B Select Register 0; 0x0000E360 ***/
  union {
    word Word;
  } XBARB_SEL0_STR;

  #define XBARB_SEL0_SEL00_MASK         0x01U
  #define XBARB_SEL0_SEL01_MASK         0x02U
  #define XBARB_SEL0_SEL02_MASK         0x04U
  #define XBARB_SEL0_SEL03_MASK         0x08U
  #define XBARB_SEL0_SEL04_MASK         0x10U
  #define XBARB_SEL0_SEL10_MASK         0x0100U
  #define XBARB_SEL0_SEL11_MASK         0x0200U
  #define XBARB_SEL0_SEL12_MASK         0x0400U
  #define XBARB_SEL0_SEL13_MASK         0x0800U
  #define XBARB_SEL0_SEL14_MASK         0x1000U
  #define XBARB_SEL0_SEL0_MASK          0x1FU
  #define XBARB_SEL0_SEL0_BITNUM        0x00U
  #define XBARB_SEL0_SEL1_MASK          0x1F00U
  #define XBARB_SEL0_SEL1_BITNUM        0x08U
  #define XBARB_SEL0                    (*((volatile word *)0x0000E360))


  /*** XBARB_SEL1 - Crossbar B Select Register 1; 0x0000E361 ***/
  union {
    word Word;
  } XBARB_SEL1_STR;

  #define XBARB_SEL1_SEL20_MASK         0x01U
  #define XBARB_SEL1_SEL21_MASK         0x02U
  #define XBARB_SEL1_SEL22_MASK         0x04U
  #define XBARB_SEL1_SEL23_MASK         0x08U
  #define XBARB_SEL1_SEL24_MASK         0x10U
  #define XBARB_SEL1_SEL30_MASK         0x0100U
  #define XBARB_SEL1_SEL31_MASK         0x0200U
  #define XBARB_SEL1_SEL32_MASK         0x0400U
  #define XBARB_SEL1_SEL33_MASK         0x0800U
  #define XBARB_SEL1_SEL34_MASK         0x1000U
  #define XBARB_SEL1_SEL2_MASK          0x1FU
  #define XBARB_SEL1_SEL2_BITNUM        0x00U
  #define XBARB_SEL1_SEL3_MASK          0x1F00U
  #define XBARB_SEL1_SEL3_BITNUM        0x08U
  #define XBARB_SEL1                    (*((volatile word *)0x0000E361))


  /*** XBARB_SEL2 - Crossbar B Select Register 2; 0x0000E362 ***/
  union {
    word Word;
  } XBARB_SEL2_STR;

  #define XBARB_SEL2_SEL40_MASK         0x01U
  #define XBARB_SEL2_SEL41_MASK         0x02U
  #define XBARB_SEL2_SEL42_MASK         0x04U
  #define XBARB_SEL2_SEL43_MASK         0x08U
  #define XBARB_SEL2_SEL44_MASK         0x10U
  #define XBARB_SEL2_SEL50_MASK         0x0100U
  #define XBARB_SEL2_SEL51_MASK         0x0200U
  #define XBARB_SEL2_SEL52_MASK         0x0400U
  #define XBARB_SEL2_SEL53_MASK         0x0800U
  #define XBARB_SEL2_SEL54_MASK         0x1000U
  #define XBARB_SEL2_SEL4_MASK          0x1FU
  #define XBARB_SEL2_SEL4_BITNUM        0x00U
  #define XBARB_SEL2_SEL5_MASK          0x1F00U
  #define XBARB_SEL2_SEL5_BITNUM        0x08U
  #define XBARB_SEL2                    (*((volatile word *)0x0000E362))


  /*** XBARB_SEL3 - Crossbar B Select Register 3; 0x0000E363 ***/
  union {
    word Word;
  } XBARB_SEL3_STR;

  #define XBARB_SEL3_SEL60_MASK         0x01U
  #define XBARB_SEL3_SEL61_MASK         0x02U
  #define XBARB_SEL3_SEL62_MASK         0x04U
  #define XBARB_SEL3_SEL63_MASK         0x08U
  #define XBARB_SEL3_SEL64_MASK         0x10U
  #define XBARB_SEL3_SEL70_MASK         0x0100U
  #define XBARB_SEL3_SEL71_MASK         0x0200U
  #define XBARB_SEL3_SEL72_MASK         0x0400U
  #define XBARB_SEL3_SEL73_MASK         0x0800U
  #define XBARB_SEL3_SEL74_MASK         0x1000U
  #define XBARB_SEL3_SEL6_MASK          0x1FU
  #define XBARB_SEL3_SEL6_BITNUM        0x00U
  #define XBARB_SEL3_SEL7_MASK          0x1F00U
  #define XBARB_SEL3_SEL7_BITNUM        0x08U
  #define XBARB_SEL3                    (*((volatile word *)0x0000E363))


  /*** XBARB_SEL4 - Crossbar B Select Register 4; 0x0000E364 ***/
  union {
    word Word;
  } XBARB_SEL4_STR;

  #define XBARB_SEL4_SEL80_MASK         0x01U
  #define XBARB_SEL4_SEL81_MASK         0x02U
  #define XBARB_SEL4_SEL82_MASK         0x04U
  #define XBARB_SEL4_SEL83_MASK         0x08U
  #define XBARB_SEL4_SEL84_MASK         0x10U
  #define XBARB_SEL4_SEL90_MASK         0x0100U
  #define XBARB_SEL4_SEL91_MASK         0x0200U
  #define XBARB_SEL4_SEL92_MASK         0x0400U
  #define XBARB_SEL4_SEL93_MASK         0x0800U
  #define XBARB_SEL4_SEL94_MASK         0x1000U
  #define XBARB_SEL4_SEL8_MASK          0x1FU
  #define XBARB_SEL4_SEL8_BITNUM        0x00U
  #define XBARB_SEL4_SEL9_MASK          0x1F00U
  #define XBARB_SEL4_SEL9_BITNUM        0x08U
  #define XBARB_SEL4                    (*((volatile word *)0x0000E364))


  /*** XBARB_SEL5 - Crossbar B Select Register 5; 0x0000E365 ***/
  union {
    word Word;
  } XBARB_SEL5_STR;

  #define XBARB_SEL5_SEL100_MASK        0x01U
  #define XBARB_SEL5_SEL101_MASK        0x02U
  #define XBARB_SEL5_SEL102_MASK        0x04U
  #define XBARB_SEL5_SEL103_MASK        0x08U
  #define XBARB_SEL5_SEL104_MASK        0x10U
  #define XBARB_SEL5_SEL110_MASK        0x0100U
  #define XBARB_SEL5_SEL111_MASK        0x0200U
  #define XBARB_SEL5_SEL112_MASK        0x0400U
  #define XBARB_SEL5_SEL113_MASK        0x0800U
  #define XBARB_SEL5_SEL114_MASK        0x1000U
  #define XBARB_SEL5_SEL10_MASK         0x1FU
  #define XBARB_SEL5_SEL10_BITNUM       0x00U
  #define XBARB_SEL5_SEL11_MASK         0x1F00U
  #define XBARB_SEL5_SEL11_BITNUM       0x08U
  #define XBARB_SEL5                    (*((volatile word *)0x0000E365))


  /*** XBARB_SEL6 - Crossbar B Select Register 6; 0x0000E366 ***/
  union {
    word Word;
  } XBARB_SEL6_STR;

  #define XBARB_SEL6_SEL120_MASK        0x01U
  #define XBARB_SEL6_SEL121_MASK        0x02U
  #define XBARB_SEL6_SEL122_MASK        0x04U
  #define XBARB_SEL6_SEL123_MASK        0x08U
  #define XBARB_SEL6_SEL124_MASK        0x10U
  #define XBARB_SEL6_SEL130_MASK        0x0100U
  #define XBARB_SEL6_SEL131_MASK        0x0200U
  #define XBARB_SEL6_SEL132_MASK        0x0400U
  #define XBARB_SEL6_SEL133_MASK        0x0800U
  #define XBARB_SEL6_SEL134_MASK        0x1000U
  #define XBARB_SEL6_SEL12_MASK         0x1FU
  #define XBARB_SEL6_SEL12_BITNUM       0x00U
  #define XBARB_SEL6_SEL13_MASK         0x1F00U
  #define XBARB_SEL6_SEL13_BITNUM       0x08U
  #define XBARB_SEL6                    (*((volatile word *)0x0000E366))


  /*** XBARB_SEL7 - Crossbar B Select Register 7; 0x0000E367 ***/
  union {
    word Word;
  } XBARB_SEL7_STR;

  #define XBARB_SEL7_SEL140_MASK        0x01U
  #define XBARB_SEL7_SEL141_MASK        0x02U
  #define XBARB_SEL7_SEL142_MASK        0x04U
  #define XBARB_SEL7_SEL143_MASK        0x08U
  #define XBARB_SEL7_SEL144_MASK        0x10U
  #define XBARB_SEL7_SEL150_MASK        0x0100U
  #define XBARB_SEL7_SEL151_MASK        0x0200U
  #define XBARB_SEL7_SEL152_MASK        0x0400U
  #define XBARB_SEL7_SEL153_MASK        0x0800U
  #define XBARB_SEL7_SEL154_MASK        0x1000U
  #define XBARB_SEL7_SEL14_MASK         0x1FU
  #define XBARB_SEL7_SEL14_BITNUM       0x00U
  #define XBARB_SEL7_SEL15_MASK         0x1F00U
  #define XBARB_SEL7_SEL15_BITNUM       0x08U
  #define XBARB_SEL7                    (*((volatile word *)0x0000E367))


} XBARB_PRPH;
/******************************************
*** Peripheral AOI
*******************************************/
typedef volatile struct {
  /*** AOI_BFCRT010 - Boolean Function Term 0 and 1 Configuration Register for EVENTn; 0x0000E380 ***/
  union {
    word Word;
  } AOI_BFCRT010_STR;

  #define AOI_BFCRT010_PT1_DC0_MASK     0x01U
  #define AOI_BFCRT010_PT1_DC1_MASK     0x02U
  #define AOI_BFCRT010_PT1_CC0_MASK     0x04U
  #define AOI_BFCRT010_PT1_CC1_MASK     0x08U
  #define AOI_BFCRT010_PT1_BC0_MASK     0x10U
  #define AOI_BFCRT010_PT1_BC1_MASK     0x20U
  #define AOI_BFCRT010_PT1_AC0_MASK     0x40U
  #define AOI_BFCRT010_PT1_AC1_MASK     0x80U
  #define AOI_BFCRT010_PT0_DC0_MASK     0x0100U
  #define AOI_BFCRT010_PT0_DC1_MASK     0x0200U
  #define AOI_BFCRT010_PT0_CC0_MASK     0x0400U
  #define AOI_BFCRT010_PT0_CC1_MASK     0x0800U
  #define AOI_BFCRT010_PT0_BC0_MASK     0x1000U
  #define AOI_BFCRT010_PT0_BC1_MASK     0x2000U
  #define AOI_BFCRT010_PT0_AC0_MASK     0x4000U
  #define AOI_BFCRT010_PT0_AC1_MASK     0x8000U
  #define AOI_BFCRT010_PT1_DC_MASK      0x03U
  #define AOI_BFCRT010_PT1_DC_BITNUM    0x00U
  #define AOI_BFCRT010_PT1_CC_MASK      0x0CU
  #define AOI_BFCRT010_PT1_CC_BITNUM    0x02U
  #define AOI_BFCRT010_PT1_BC_MASK      0x30U
  #define AOI_BFCRT010_PT1_BC_BITNUM    0x04U
  #define AOI_BFCRT010_PT1_AC_MASK      0xC0U
  #define AOI_BFCRT010_PT1_AC_BITNUM    0x06U
  #define AOI_BFCRT010_PT0_DC_MASK      0x0300U
  #define AOI_BFCRT010_PT0_DC_BITNUM    0x08U
  #define AOI_BFCRT010_PT0_CC_MASK      0x0C00U
  #define AOI_BFCRT010_PT0_CC_BITNUM    0x0AU
  #define AOI_BFCRT010_PT0_BC_MASK      0x3000U
  #define AOI_BFCRT010_PT0_BC_BITNUM    0x0CU
  #define AOI_BFCRT010_PT0_AC_MASK      0xC000U
  #define AOI_BFCRT010_PT0_AC_BITNUM    0x0EU
  #define AOI_BFCRT010                  (*((volatile word *)0x0000E380))


  /*** AOI_BFCRT230 - Boolean Function Term 2 and 3 Configuration Register for EVENTn; 0x0000E381 ***/
  union {
    word Word;
  } AOI_BFCRT230_STR;

  #define AOI_BFCRT230_PT3_DC0_MASK     0x01U
  #define AOI_BFCRT230_PT3_DC1_MASK     0x02U
  #define AOI_BFCRT230_PT3_CC0_MASK     0x04U
  #define AOI_BFCRT230_PT3_CC1_MASK     0x08U
  #define AOI_BFCRT230_PT3_BC0_MASK     0x10U
  #define AOI_BFCRT230_PT3_BC1_MASK     0x20U
  #define AOI_BFCRT230_PT3_AC0_MASK     0x40U
  #define AOI_BFCRT230_PT3_AC1_MASK     0x80U
  #define AOI_BFCRT230_PT2_DC0_MASK     0x0100U
  #define AOI_BFCRT230_PT2_DC1_MASK     0x0200U
  #define AOI_BFCRT230_PT2_CC0_MASK     0x0400U
  #define AOI_BFCRT230_PT2_CC1_MASK     0x0800U
  #define AOI_BFCRT230_PT2_BC0_MASK     0x1000U
  #define AOI_BFCRT230_PT2_BC1_MASK     0x2000U
  #define AOI_BFCRT230_PT2_AC0_MASK     0x4000U
  #define AOI_BFCRT230_PT2_AC1_MASK     0x8000U
  #define AOI_BFCRT230_PT3_DC_MASK      0x03U
  #define AOI_BFCRT230_PT3_DC_BITNUM    0x00U
  #define AOI_BFCRT230_PT3_CC_MASK      0x0CU
  #define AOI_BFCRT230_PT3_CC_BITNUM    0x02U
  #define AOI_BFCRT230_PT3_BC_MASK      0x30U
  #define AOI_BFCRT230_PT3_BC_BITNUM    0x04U
  #define AOI_BFCRT230_PT3_AC_MASK      0xC0U
  #define AOI_BFCRT230_PT3_AC_BITNUM    0x06U
  #define AOI_BFCRT230_PT2_DC_MASK      0x0300U
  #define AOI_BFCRT230_PT2_DC_BITNUM    0x08U
  #define AOI_BFCRT230_PT2_CC_MASK      0x0C00U
  #define AOI_BFCRT230_PT2_CC_BITNUM    0x0AU
  #define AOI_BFCRT230_PT2_BC_MASK      0x3000U
  #define AOI_BFCRT230_PT2_BC_BITNUM    0x0CU
  #define AOI_BFCRT230_PT2_AC_MASK      0xC000U
  #define AOI_BFCRT230_PT2_AC_BITNUM    0x0EU
  #define AOI_BFCRT230                  (*((volatile word *)0x0000E381))


  /*** AOI_BFCRT011 - Boolean Function Term 0 and 1 Configuration Register for EVENTn; 0x0000E382 ***/
  union {
    word Word;
  } AOI_BFCRT011_STR;

  #define AOI_BFCRT011_PT1_DC0_MASK     0x01U
  #define AOI_BFCRT011_PT1_DC1_MASK     0x02U
  #define AOI_BFCRT011_PT1_CC0_MASK     0x04U
  #define AOI_BFCRT011_PT1_CC1_MASK     0x08U
  #define AOI_BFCRT011_PT1_BC0_MASK     0x10U
  #define AOI_BFCRT011_PT1_BC1_MASK     0x20U
  #define AOI_BFCRT011_PT1_AC0_MASK     0x40U
  #define AOI_BFCRT011_PT1_AC1_MASK     0x80U
  #define AOI_BFCRT011_PT0_DC0_MASK     0x0100U
  #define AOI_BFCRT011_PT0_DC1_MASK     0x0200U
  #define AOI_BFCRT011_PT0_CC0_MASK     0x0400U
  #define AOI_BFCRT011_PT0_CC1_MASK     0x0800U
  #define AOI_BFCRT011_PT0_BC0_MASK     0x1000U
  #define AOI_BFCRT011_PT0_BC1_MASK     0x2000U
  #define AOI_BFCRT011_PT0_AC0_MASK     0x4000U
  #define AOI_BFCRT011_PT0_AC1_MASK     0x8000U
  #define AOI_BFCRT011_PT1_DC_MASK      0x03U
  #define AOI_BFCRT011_PT1_DC_BITNUM    0x00U
  #define AOI_BFCRT011_PT1_CC_MASK      0x0CU
  #define AOI_BFCRT011_PT1_CC_BITNUM    0x02U
  #define AOI_BFCRT011_PT1_BC_MASK      0x30U
  #define AOI_BFCRT011_PT1_BC_BITNUM    0x04U
  #define AOI_BFCRT011_PT1_AC_MASK      0xC0U
  #define AOI_BFCRT011_PT1_AC_BITNUM    0x06U
  #define AOI_BFCRT011_PT0_DC_MASK      0x0300U
  #define AOI_BFCRT011_PT0_DC_BITNUM    0x08U
  #define AOI_BFCRT011_PT0_CC_MASK      0x0C00U
  #define AOI_BFCRT011_PT0_CC_BITNUM    0x0AU
  #define AOI_BFCRT011_PT0_BC_MASK      0x3000U
  #define AOI_BFCRT011_PT0_BC_BITNUM    0x0CU
  #define AOI_BFCRT011_PT0_AC_MASK      0xC000U
  #define AOI_BFCRT011_PT0_AC_BITNUM    0x0EU
  #define AOI_BFCRT011                  (*((volatile word *)0x0000E382))


  /*** AOI_BFCRT231 - Boolean Function Term 2 and 3 Configuration Register for EVENTn; 0x0000E383 ***/
  union {
    word Word;
  } AOI_BFCRT231_STR;

  #define AOI_BFCRT231_PT3_DC0_MASK     0x01U
  #define AOI_BFCRT231_PT3_DC1_MASK     0x02U
  #define AOI_BFCRT231_PT3_CC0_MASK     0x04U
  #define AOI_BFCRT231_PT3_CC1_MASK     0x08U
  #define AOI_BFCRT231_PT3_BC0_MASK     0x10U
  #define AOI_BFCRT231_PT3_BC1_MASK     0x20U
  #define AOI_BFCRT231_PT3_AC0_MASK     0x40U
  #define AOI_BFCRT231_PT3_AC1_MASK     0x80U
  #define AOI_BFCRT231_PT2_DC0_MASK     0x0100U
  #define AOI_BFCRT231_PT2_DC1_MASK     0x0200U
  #define AOI_BFCRT231_PT2_CC0_MASK     0x0400U
  #define AOI_BFCRT231_PT2_CC1_MASK     0x0800U
  #define AOI_BFCRT231_PT2_BC0_MASK     0x1000U
  #define AOI_BFCRT231_PT2_BC1_MASK     0x2000U
  #define AOI_BFCRT231_PT2_AC0_MASK     0x4000U
  #define AOI_BFCRT231_PT2_AC1_MASK     0x8000U
  #define AOI_BFCRT231_PT3_DC_MASK      0x03U
  #define AOI_BFCRT231_PT3_DC_BITNUM    0x00U
  #define AOI_BFCRT231_PT3_CC_MASK      0x0CU
  #define AOI_BFCRT231_PT3_CC_BITNUM    0x02U
  #define AOI_BFCRT231_PT3_BC_MASK      0x30U
  #define AOI_BFCRT231_PT3_BC_BITNUM    0x04U
  #define AOI_BFCRT231_PT3_AC_MASK      0xC0U
  #define AOI_BFCRT231_PT3_AC_BITNUM    0x06U
  #define AOI_BFCRT231_PT2_DC_MASK      0x0300U
  #define AOI_BFCRT231_PT2_DC_BITNUM    0x08U
  #define AOI_BFCRT231_PT2_CC_MASK      0x0C00U
  #define AOI_BFCRT231_PT2_CC_BITNUM    0x0AU
  #define AOI_BFCRT231_PT2_BC_MASK      0x3000U
  #define AOI_BFCRT231_PT2_BC_BITNUM    0x0CU
  #define AOI_BFCRT231_PT2_AC_MASK      0xC000U
  #define AOI_BFCRT231_PT2_AC_BITNUM    0x0EU
  #define AOI_BFCRT231                  (*((volatile word *)0x0000E383))


  /*** AOI_BFCRT012 - Boolean Function Term 0 and 1 Configuration Register for EVENTn; 0x0000E384 ***/
  union {
    word Word;
  } AOI_BFCRT012_STR;

  #define AOI_BFCRT012_PT1_DC0_MASK     0x01U
  #define AOI_BFCRT012_PT1_DC1_MASK     0x02U
  #define AOI_BFCRT012_PT1_CC0_MASK     0x04U
  #define AOI_BFCRT012_PT1_CC1_MASK     0x08U
  #define AOI_BFCRT012_PT1_BC0_MASK     0x10U
  #define AOI_BFCRT012_PT1_BC1_MASK     0x20U
  #define AOI_BFCRT012_PT1_AC0_MASK     0x40U
  #define AOI_BFCRT012_PT1_AC1_MASK     0x80U
  #define AOI_BFCRT012_PT0_DC0_MASK     0x0100U
  #define AOI_BFCRT012_PT0_DC1_MASK     0x0200U
  #define AOI_BFCRT012_PT0_CC0_MASK     0x0400U
  #define AOI_BFCRT012_PT0_CC1_MASK     0x0800U
  #define AOI_BFCRT012_PT0_BC0_MASK     0x1000U
  #define AOI_BFCRT012_PT0_BC1_MASK     0x2000U
  #define AOI_BFCRT012_PT0_AC0_MASK     0x4000U
  #define AOI_BFCRT012_PT0_AC1_MASK     0x8000U
  #define AOI_BFCRT012_PT1_DC_MASK      0x03U
  #define AOI_BFCRT012_PT1_DC_BITNUM    0x00U
  #define AOI_BFCRT012_PT1_CC_MASK      0x0CU
  #define AOI_BFCRT012_PT1_CC_BITNUM    0x02U
  #define AOI_BFCRT012_PT1_BC_MASK      0x30U
  #define AOI_BFCRT012_PT1_BC_BITNUM    0x04U
  #define AOI_BFCRT012_PT1_AC_MASK      0xC0U
  #define AOI_BFCRT012_PT1_AC_BITNUM    0x06U
  #define AOI_BFCRT012_PT0_DC_MASK      0x0300U
  #define AOI_BFCRT012_PT0_DC_BITNUM    0x08U
  #define AOI_BFCRT012_PT0_CC_MASK      0x0C00U
  #define AOI_BFCRT012_PT0_CC_BITNUM    0x0AU
  #define AOI_BFCRT012_PT0_BC_MASK      0x3000U
  #define AOI_BFCRT012_PT0_BC_BITNUM    0x0CU
  #define AOI_BFCRT012_PT0_AC_MASK      0xC000U
  #define AOI_BFCRT012_PT0_AC_BITNUM    0x0EU
  #define AOI_BFCRT012                  (*((volatile word *)0x0000E384))


  /*** AOI_BFCRT232 - Boolean Function Term 2 and 3 Configuration Register for EVENTn; 0x0000E385 ***/
  union {
    word Word;
  } AOI_BFCRT232_STR;

  #define AOI_BFCRT232_PT3_DC0_MASK     0x01U
  #define AOI_BFCRT232_PT3_DC1_MASK     0x02U
  #define AOI_BFCRT232_PT3_CC0_MASK     0x04U
  #define AOI_BFCRT232_PT3_CC1_MASK     0x08U
  #define AOI_BFCRT232_PT3_BC0_MASK     0x10U
  #define AOI_BFCRT232_PT3_BC1_MASK     0x20U
  #define AOI_BFCRT232_PT3_AC0_MASK     0x40U
  #define AOI_BFCRT232_PT3_AC1_MASK     0x80U
  #define AOI_BFCRT232_PT2_DC0_MASK     0x0100U
  #define AOI_BFCRT232_PT2_DC1_MASK     0x0200U
  #define AOI_BFCRT232_PT2_CC0_MASK     0x0400U
  #define AOI_BFCRT232_PT2_CC1_MASK     0x0800U
  #define AOI_BFCRT232_PT2_BC0_MASK     0x1000U
  #define AOI_BFCRT232_PT2_BC1_MASK     0x2000U
  #define AOI_BFCRT232_PT2_AC0_MASK     0x4000U
  #define AOI_BFCRT232_PT2_AC1_MASK     0x8000U
  #define AOI_BFCRT232_PT3_DC_MASK      0x03U
  #define AOI_BFCRT232_PT3_DC_BITNUM    0x00U
  #define AOI_BFCRT232_PT3_CC_MASK      0x0CU
  #define AOI_BFCRT232_PT3_CC_BITNUM    0x02U
  #define AOI_BFCRT232_PT3_BC_MASK      0x30U
  #define AOI_BFCRT232_PT3_BC_BITNUM    0x04U
  #define AOI_BFCRT232_PT3_AC_MASK      0xC0U
  #define AOI_BFCRT232_PT3_AC_BITNUM    0x06U
  #define AOI_BFCRT232_PT2_DC_MASK      0x0300U
  #define AOI_BFCRT232_PT2_DC_BITNUM    0x08U
  #define AOI_BFCRT232_PT2_CC_MASK      0x0C00U
  #define AOI_BFCRT232_PT2_CC_BITNUM    0x0AU
  #define AOI_BFCRT232_PT2_BC_MASK      0x3000U
  #define AOI_BFCRT232_PT2_BC_BITNUM    0x0CU
  #define AOI_BFCRT232_PT2_AC_MASK      0xC000U
  #define AOI_BFCRT232_PT2_AC_BITNUM    0x0EU
  #define AOI_BFCRT232                  (*((volatile word *)0x0000E385))


  /*** AOI_BFCRT013 - Boolean Function Term 0 and 1 Configuration Register for EVENTn; 0x0000E386 ***/
  union {
    word Word;
  } AOI_BFCRT013_STR;

  #define AOI_BFCRT013_PT1_DC0_MASK     0x01U
  #define AOI_BFCRT013_PT1_DC1_MASK     0x02U
  #define AOI_BFCRT013_PT1_CC0_MASK     0x04U
  #define AOI_BFCRT013_PT1_CC1_MASK     0x08U
  #define AOI_BFCRT013_PT1_BC0_MASK     0x10U
  #define AOI_BFCRT013_PT1_BC1_MASK     0x20U
  #define AOI_BFCRT013_PT1_AC0_MASK     0x40U
  #define AOI_BFCRT013_PT1_AC1_MASK     0x80U
  #define AOI_BFCRT013_PT0_DC0_MASK     0x0100U
  #define AOI_BFCRT013_PT0_DC1_MASK     0x0200U
  #define AOI_BFCRT013_PT0_CC0_MASK     0x0400U
  #define AOI_BFCRT013_PT0_CC1_MASK     0x0800U
  #define AOI_BFCRT013_PT0_BC0_MASK     0x1000U
  #define AOI_BFCRT013_PT0_BC1_MASK     0x2000U
  #define AOI_BFCRT013_PT0_AC0_MASK     0x4000U
  #define AOI_BFCRT013_PT0_AC1_MASK     0x8000U
  #define AOI_BFCRT013_PT1_DC_MASK      0x03U
  #define AOI_BFCRT013_PT1_DC_BITNUM    0x00U
  #define AOI_BFCRT013_PT1_CC_MASK      0x0CU
  #define AOI_BFCRT013_PT1_CC_BITNUM    0x02U
  #define AOI_BFCRT013_PT1_BC_MASK      0x30U
  #define AOI_BFCRT013_PT1_BC_BITNUM    0x04U
  #define AOI_BFCRT013_PT1_AC_MASK      0xC0U
  #define AOI_BFCRT013_PT1_AC_BITNUM    0x06U
  #define AOI_BFCRT013_PT0_DC_MASK      0x0300U
  #define AOI_BFCRT013_PT0_DC_BITNUM    0x08U
  #define AOI_BFCRT013_PT0_CC_MASK      0x0C00U
  #define AOI_BFCRT013_PT0_CC_BITNUM    0x0AU
  #define AOI_BFCRT013_PT0_BC_MASK      0x3000U
  #define AOI_BFCRT013_PT0_BC_BITNUM    0x0CU
  #define AOI_BFCRT013_PT0_AC_MASK      0xC000U
  #define AOI_BFCRT013_PT0_AC_BITNUM    0x0EU
  #define AOI_BFCRT013                  (*((volatile word *)0x0000E386))


  /*** AOI_BFCRT233 - Boolean Function Term 2 and 3 Configuration Register for EVENTn; 0x0000E387 ***/
  union {
    word Word;
  } AOI_BFCRT233_STR;

  #define AOI_BFCRT233_PT3_DC0_MASK     0x01U
  #define AOI_BFCRT233_PT3_DC1_MASK     0x02U
  #define AOI_BFCRT233_PT3_CC0_MASK     0x04U
  #define AOI_BFCRT233_PT3_CC1_MASK     0x08U
  #define AOI_BFCRT233_PT3_BC0_MASK     0x10U
  #define AOI_BFCRT233_PT3_BC1_MASK     0x20U
  #define AOI_BFCRT233_PT3_AC0_MASK     0x40U
  #define AOI_BFCRT233_PT3_AC1_MASK     0x80U
  #define AOI_BFCRT233_PT2_DC0_MASK     0x0100U
  #define AOI_BFCRT233_PT2_DC1_MASK     0x0200U
  #define AOI_BFCRT233_PT2_CC0_MASK     0x0400U
  #define AOI_BFCRT233_PT2_CC1_MASK     0x0800U
  #define AOI_BFCRT233_PT2_BC0_MASK     0x1000U
  #define AOI_BFCRT233_PT2_BC1_MASK     0x2000U
  #define AOI_BFCRT233_PT2_AC0_MASK     0x4000U
  #define AOI_BFCRT233_PT2_AC1_MASK     0x8000U
  #define AOI_BFCRT233_PT3_DC_MASK      0x03U
  #define AOI_BFCRT233_PT3_DC_BITNUM    0x00U
  #define AOI_BFCRT233_PT3_CC_MASK      0x0CU
  #define AOI_BFCRT233_PT3_CC_BITNUM    0x02U
  #define AOI_BFCRT233_PT3_BC_MASK      0x30U
  #define AOI_BFCRT233_PT3_BC_BITNUM    0x04U
  #define AOI_BFCRT233_PT3_AC_MASK      0xC0U
  #define AOI_BFCRT233_PT3_AC_BITNUM    0x06U
  #define AOI_BFCRT233_PT2_DC_MASK      0x0300U
  #define AOI_BFCRT233_PT2_DC_BITNUM    0x08U
  #define AOI_BFCRT233_PT2_CC_MASK      0x0C00U
  #define AOI_BFCRT233_PT2_CC_BITNUM    0x0AU
  #define AOI_BFCRT233_PT2_BC_MASK      0x3000U
  #define AOI_BFCRT233_PT2_BC_BITNUM    0x0CU
  #define AOI_BFCRT233_PT2_AC_MASK      0xC000U
  #define AOI_BFCRT233_PT2_AC_BITNUM    0x0EU
  #define AOI_BFCRT233                  (*((volatile word *)0x0000E387))


} AOI_PRPH;
/******************************************
*** Peripheral FTFL
*******************************************/
typedef volatile struct {
  /*** FTFL_FSTAT - Flash Status Register; 0x0001C780 ***/
  union {
    byte Byte;
  } FTFL_FSTAT_STR;

  #define FTFL_FSTAT_MGSTAT0_MASK       0x01U
  #define FTFL_FSTAT_FPVIOL_MASK        0x10U
  #define FTFL_FSTAT_ACCERR_MASK        0x20U
  #define FTFL_FSTAT_RDCOLERR_MASK      0x40U
  #define FTFL_FSTAT_CCIF_MASK          0x80U
  #define FTFL_FSTAT                    (*((volatile byte *)0x0001C780))


  /*** FTFL_FCNFG - Flash Configuration Register; 0x0001C781 ***/
  union {
    byte Byte;
  } FTFL_FCNFG_STR;

  #define FTFL_FCNFG_EEERDY_MASK        0x01U
  #define FTFL_FCNFG_RAMRDY_MASK        0x02U
  #define FTFL_FCNFG_PFLSH_MASK         0x04U
  #define FTFL_FCNFG_ERSSUSP_MASK       0x10U
  #define FTFL_FCNFG_ERSAREQ_MASK       0x20U
  #define FTFL_FCNFG_RDCOLLIE_MASK      0x40U
  #define FTFL_FCNFG_CCIE_MASK          0x80U
  #define FTFL_FCNFG                    (*((volatile byte *)0x0001C781))


  /*** FTFL_FSEC - Flash Security Register; 0x0001C782 ***/
  union {
    byte Byte;
  } FTFL_FSEC_STR;

  #define FTFL_FSEC_SEC0_MASK           0x01U
  #define FTFL_FSEC_SEC1_MASK           0x02U
  #define FTFL_FSEC_FSLACC0_MASK        0x04U
  #define FTFL_FSEC_FSLACC1_MASK        0x08U
  #define FTFL_FSEC_MEEN0_MASK          0x10U
  #define FTFL_FSEC_MEEN1_MASK          0x20U
  #define FTFL_FSEC_KEYEN0_MASK         0x40U
  #define FTFL_FSEC_KEYEN1_MASK         0x80U
  #define FTFL_FSEC_SEC_MASK            0x03U
  #define FTFL_FSEC_SEC_BITNUM          0x00U
  #define FTFL_FSEC_FSLACC_MASK         0x0CU
  #define FTFL_FSEC_FSLACC_BITNUM       0x02U
  #define FTFL_FSEC_MEEN_MASK           0x30U
  #define FTFL_FSEC_MEEN_BITNUM         0x04U
  #define FTFL_FSEC_KEYEN_MASK          0xC0U
  #define FTFL_FSEC_KEYEN_BITNUM        0x06U
  #define FTFL_FSEC                     (*((volatile byte *)0x0001C782))


  /*** FTFL_FOPT - Flash Option Register; 0x0001C783 ***/
  union {
    byte Byte;
  } FTFL_FOPT_STR;

  #define FTFL_FOPT                     (*((volatile byte *)0x0001C783))


  /*** FTFL_FCCOB3 - Flash Common Command Object Registers; 0x0001C784 ***/
  union {
    byte Byte;
  } FTFL_FCCOB3_STR;

  #define FTFL_FCCOB3                   (*((volatile byte *)0x0001C784))


  /*** FTFL_FCCOB2 - Flash Common Command Object Registers; 0x0001C785 ***/
  union {
    byte Byte;
  } FTFL_FCCOB2_STR;

  #define FTFL_FCCOB2                   (*((volatile byte *)0x0001C785))


  /*** FTFL_FCCOB1 - Flash Common Command Object Registers; 0x0001C786 ***/
  union {
    byte Byte;
  } FTFL_FCCOB1_STR;

  #define FTFL_FCCOB1                   (*((volatile byte *)0x0001C786))


  /*** FTFL_FCCOB0 - Flash Common Command Object Registers; 0x0001C787 ***/
  union {
    byte Byte;
  } FTFL_FCCOB0_STR;

  #define FTFL_FCCOB0                   (*((volatile byte *)0x0001C787))


  /*** FTFL_FCCOB7 - Flash Common Command Object Registers; 0x0001C788 ***/
  union {
    byte Byte;
  } FTFL_FCCOB7_STR;

  #define FTFL_FCCOB7                   (*((volatile byte *)0x0001C788))


  /*** FTFL_FCCOB6 - Flash Common Command Object Registers; 0x0001C789 ***/
  union {
    byte Byte;
  } FTFL_FCCOB6_STR;

  #define FTFL_FCCOB6                   (*((volatile byte *)0x0001C789))


  /*** FTFL_FCCOB5 - Flash Common Command Object Registers; 0x0001C78A ***/
  union {
    byte Byte;
  } FTFL_FCCOB5_STR;

  #define FTFL_FCCOB5                   (*((volatile byte *)0x0001C78A))


  /*** FTFL_FCCOB4 - Flash Common Command Object Registers; 0x0001C78B ***/
  union {
    byte Byte;
  } FTFL_FCCOB4_STR;

  #define FTFL_FCCOB4                   (*((volatile byte *)0x0001C78B))


  /*** FTFL_FCCOBB - Flash Common Command Object Registers; 0x0001C78C ***/
  union {
    byte Byte;
  } FTFL_FCCOBB_STR;

  #define FTFL_FCCOBB                   (*((volatile byte *)0x0001C78C))


  /*** FTFL_FCCOBA - Flash Common Command Object Registers; 0x0001C78D ***/
  union {
    byte Byte;
  } FTFL_FCCOBA_STR;

  #define FTFL_FCCOBA                   (*((volatile byte *)0x0001C78D))


  /*** FTFL_FCCOB9 - Flash Common Command Object Registers; 0x0001C78E ***/
  union {
    byte Byte;
  } FTFL_FCCOB9_STR;

  #define FTFL_FCCOB9                   (*((volatile byte *)0x0001C78E))


  /*** FTFL_FCCOB8 - Flash Common Command Object Registers; 0x0001C78F ***/
  union {
    byte Byte;
  } FTFL_FCCOB8_STR;

  #define FTFL_FCCOB8                   (*((volatile byte *)0x0001C78F))


  /*** FTFL_FPROT3 - Program Flash Protection Registers; 0x0001C790 ***/
  union {
    byte Byte;
  } FTFL_FPROT3_STR;

  #define FTFL_FPROT3                   (*((volatile byte *)0x0001C790))


  /*** FTFL_FPROT2 - Program Flash Protection Registers; 0x0001C791 ***/
  union {
    byte Byte;
  } FTFL_FPROT2_STR;

  #define FTFL_FPROT2                   (*((volatile byte *)0x0001C791))


  /*** FTFL_FPROT1 - Program Flash Protection Registers; 0x0001C792 ***/
  union {
    byte Byte;
  } FTFL_FPROT1_STR;

  #define FTFL_FPROT1                   (*((volatile byte *)0x0001C792))


  /*** FTFL_FPROT0 - Program Flash Protection Registers; 0x0001C793 ***/
  union {
    byte Byte;
  } FTFL_FPROT0_STR;

  #define FTFL_FPROT0                   (*((volatile byte *)0x0001C793))


  byte Reserved0[2];                   /* Reserved (unused) registers */

  /*** FTFL_FEPROT - EEPROM Protection Register; 0x0001C796 ***/
  union {
    byte Byte;
  } FTFL_FEPROT_STR;

  #define FTFL_FEPROT                   (*((volatile byte *)0x0001C796))


  /*** FTFL_FDPROT - Data Flash Protection Register; 0x0001C797 ***/
  union {
    byte Byte;
  } FTFL_FDPROT_STR;

  #define FTFL_FDPROT                   (*((volatile byte *)0x0001C797))


} FTFL_PRPH;
/******************************************
*** Peripheral SIM
*******************************************/
typedef volatile struct {
  /*** SIM_CTRL - Control Register; 0x0000E400 ***/
  union {
    word Word;
  } SIM_CTRL_STR;

  #define SIM_CTRL_WAIT_disable0_MASK   0x01U
  #define SIM_CTRL_WAIT_disable1_MASK   0x02U
  #define SIM_CTRL_STOP_disable0_MASK   0x04U
  #define SIM_CTRL_STOP_disable1_MASK   0x08U
  #define SIM_CTRL_SWRst_MASK           0x10U
  #define SIM_CTRL_OnceEbl_MASK         0x20U
  #define SIM_CTRL_DMAEbl0_MASK         0x40U
  #define SIM_CTRL_DMAEbl1_MASK         0x80U
  #define SIM_CTRL_DMAEbl2_MASK         0x0100U
  #define SIM_CTRL_RST_FILT_MASK        0x0400U
  #define SIM_CTRL_WAIT_disable_MASK    0x03U
  #define SIM_CTRL_WAIT_disable_BITNUM  0x00U
  #define SIM_CTRL_STOP_disable_MASK    0x0CU
  #define SIM_CTRL_STOP_disable_BITNUM  0x02U
  #define SIM_CTRL_DMAEbl_MASK          0x01C0U
  #define SIM_CTRL_DMAEbl_BITNUM        0x06U
  #define SIM_CTRL                      (*((volatile word *)0x0000E400))


  /*** SIM_RSTAT - Reset Status Register; 0x0000E401 ***/
  union {
    word Word;
  } SIM_RSTAT_STR;

  #define SIM_RSTAT_POR_MASK            0x04U
  #define SIM_RSTAT_EXTR_MASK           0x08U
  #define SIM_RSTAT_COP_LOR_MASK        0x10U
  #define SIM_RSTAT_COP_CPU_MASK        0x20U
  #define SIM_RSTAT_SWR_MASK            0x40U
  #define SIM_RSTAT_EZPR_MASK           0x80U
  #define SIM_RSTAT                     (*((volatile word *)0x0000E401))


  /*** SIM_SCR0 - Software Control Register; 0x0000E402 ***/
  union {
    word Word;
  } SIM_SCR0_STR;

  #define SIM_SCR0                      (*((volatile word *)0x0000E402))


  /*** SIM_SCR1 - Software Control Register; 0x0000E403 ***/
  union {
    word Word;
  } SIM_SCR1_STR;

  #define SIM_SCR1                      (*((volatile word *)0x0000E403))


  /*** SIM_SCR2 - Software Control Register; 0x0000E404 ***/
  union {
    word Word;
  } SIM_SCR2_STR;

  #define SIM_SCR2                      (*((volatile word *)0x0000E404))


  /*** SIM_SCR3 - Software Control Register; 0x0000E405 ***/
  union {
    word Word;
  } SIM_SCR3_STR;

  #define SIM_SCR3                      (*((volatile word *)0x0000E405))


  /*** SIM_MSHID - Most Significant Half of JTAG ID; 0x0000E406 ***/
  union {
    word Word;
  } SIM_MSHID_STR;

  #define SIM_MSHID                     (*((volatile word *)0x0000E406))


  /*** SIM_LSHID - Least Significant Half of JTAG ID; 0x0000E407 ***/
  union {
    word Word;
  } SIM_LSHID_STR;

  #define SIM_LSHID                     (*((volatile word *)0x0000E407))


  /*** SIM_PWR - Power Control Register; 0x0000E408 ***/
  union {
    word Word;
  } SIM_PWR_STR;

  #define SIM_PWR_LRSTDBY0_MASK         0x01U
  #define SIM_PWR_LRSTDBY1_MASK         0x02U
  #define SIM_PWR_SR27STDBY0_MASK       0x04U
  #define SIM_PWR_SR27STDBY1_MASK       0x08U
  #define SIM_PWR_SR27PDN0_MASK         0x10U
  #define SIM_PWR_SR27PDN1_MASK         0x20U
  #define SIM_PWR_SR12STDBY0_MASK       0x40U
  #define SIM_PWR_SR12STDBY1_MASK       0x80U
  #define SIM_PWR_LRSTDBY_MASK          0x03U
  #define SIM_PWR_LRSTDBY_BITNUM        0x00U
  #define SIM_PWR_SR27STDBY_MASK        0x0CU
  #define SIM_PWR_SR27STDBY_BITNUM      0x02U
  #define SIM_PWR_SR27PDN_MASK          0x30U
  #define SIM_PWR_SR27PDN_BITNUM        0x04U
  #define SIM_PWR_SR12STDBY_MASK        0xC0U
  #define SIM_PWR_SR12STDBY_BITNUM      0x06U
  #define SIM_PWR                       (*((volatile word *)0x0000E408))


  word Reserved0[1];                   /* Reserved (unused) registers */

  /*** SIM_CLKOUT - Clock Output Select Register; 0x0000E40A ***/
  union {
    word Word;
  } SIM_CLKOUT_STR;

  #define SIM_CLKOUT_CLKOSEL00_MASK     0x01U
  #define SIM_CLKOUT_CLKOSEL01_MASK     0x02U
  #define SIM_CLKOUT_CLKOSEL02_MASK     0x04U
  #define SIM_CLKOUT_CLKDIS0_MASK       0x20U
  #define SIM_CLKOUT_CLKOSEL10_MASK     0x80U
  #define SIM_CLKOUT_CLKOSEL11_MASK     0x0100U
  #define SIM_CLKOUT_CLKOSEL12_MASK     0x0200U
  #define SIM_CLKOUT_CLKDIS1_MASK       0x1000U
  #define SIM_CLKOUT_CLKODIV0_MASK      0x2000U
  #define SIM_CLKOUT_CLKODIV1_MASK      0x4000U
  #define SIM_CLKOUT_CLKODIV2_MASK      0x8000U
  #define SIM_CLKOUT_CLKOSEL0_MASK      0x07U
  #define SIM_CLKOUT_CLKOSEL0_BITNUM    0x00U
  #define SIM_CLKOUT_CLKOSEL1_MASK      0x0380U
  #define SIM_CLKOUT_CLKOSEL1_BITNUM    0x07U
  #define SIM_CLKOUT_CLKODIV_MASK       0xE000U
  #define SIM_CLKOUT_CLKODIV_BITNUM     0x0DU
  #define SIM_CLKOUT                    (*((volatile word *)0x0000E40A))


  /*** SIM_PCR - Peripheral Clock Rate Register; 0x0000E40B ***/
  union {
    word Word;
  } SIM_PCR_STR;

  #define SIM_PCR_SCI2_CR_MASK          0x0800U
  #define SIM_PCR_SCI1_CR_MASK          0x1000U
  #define SIM_PCR_SCI0_CR_MASK          0x2000U
  #define SIM_PCR                       (*((volatile word *)0x0000E40B))


  /*** SIM_PCE0 - Peripheral Clock Enable Register 0; 0x0000E40C ***/
  union {
    word Word;
  } SIM_PCE0_STR;

  #define SIM_PCE0_GPIOG_MASK           0x01U
  #define SIM_PCE0_GPIOF_MASK           0x02U
  #define SIM_PCE0_GPIOE_MASK           0x04U
  #define SIM_PCE0_GPIOD_MASK           0x08U
  #define SIM_PCE0_GPIOC_MASK           0x10U
  #define SIM_PCE0_GPIOB_MASK           0x20U
  #define SIM_PCE0_GPIOA_MASK           0x40U
  #define SIM_PCE0_TB3_MASK             0x0100U
  #define SIM_PCE0_TB2_MASK             0x0200U
  #define SIM_PCE0_TB1_MASK             0x0400U
  #define SIM_PCE0_TB0_MASK             0x0800U
  #define SIM_PCE0_TA3_MASK             0x1000U
  #define SIM_PCE0_TA2_MASK             0x2000U
  #define SIM_PCE0_TA1_MASK             0x4000U
  #define SIM_PCE0_TA0_MASK             0x8000U
  #define SIM_PCE0                      (*((volatile word *)0x0000E40C))


  /*** SIM_PCE1 - Peripheral Clock Enable Register 1; 0x0000E40D ***/
  union {
    word Word;
  } SIM_PCE1_STR;

  #define SIM_PCE1_FLEXCAN_MASK         0x01U
  #define SIM_PCE1_IIC1_MASK            0x20U
  #define SIM_PCE1_IIC0_MASK            0x40U
  #define SIM_PCE1_QSPI2_MASK           0x80U
  #define SIM_PCE1_QSPI1_MASK           0x0100U
  #define SIM_PCE1_QSPI0_MASK           0x0200U
  #define SIM_PCE1_SCI2_MASK            0x0400U
  #define SIM_PCE1_SCI1_MASK            0x0800U
  #define SIM_PCE1_SCI0_MASK            0x1000U
  #define SIM_PCE1_DAC_MASK             0x2000U
  #define SIM_PCE1                      (*((volatile word *)0x0000E40D))


  /*** SIM_PCE2 - Peripheral Clock Enable Register 2; 0x0000E40E ***/
  union {
    word Word;
  } SIM_PCE2_STR;

  #define SIM_PCE2_PDB1_MASK            0x01U
  #define SIM_PCE2_PDB0_MASK            0x02U
  #define SIM_PCE2_PIT1_MASK            0x04U
  #define SIM_PCE2_PIT0_MASK            0x08U
  #define SIM_PCE2_QDC_MASK             0x10U
  #define SIM_PCE2_CRC_MASK             0x20U
  #define SIM_PCE2_CYCADC_MASK          0x80U
  #define SIM_PCE2_SARADC_MASK          0x0100U
  #define SIM_PCE2_CMPD_MASK            0x0200U
  #define SIM_PCE2_CMPC_MASK            0x0400U
  #define SIM_PCE2_CMPB_MASK            0x0800U
  #define SIM_PCE2_CMPA_MASK            0x1000U
  #define SIM_PCE2                      (*((volatile word *)0x0000E40E))


  /*** SIM_PCE3 - Peripheral Clock Enable Register 3; 0x0000E40F ***/
  union {
    word Word;
  } SIM_PCE3_STR;

  #define SIM_PCE3_PWMBCH3_MASK         0x01U
  #define SIM_PCE3_PWMBCH2_MASK         0x02U
  #define SIM_PCE3_PWMBCH1_MASK         0x04U
  #define SIM_PCE3_PWMBCH0_MASK         0x08U
  #define SIM_PCE3_PWMACH3_MASK         0x10U
  #define SIM_PCE3_PWMACH2_MASK         0x20U
  #define SIM_PCE3_PWMACH1_MASK         0x40U
  #define SIM_PCE3_PWMACH0_MASK         0x80U
  #define SIM_PCE3                      (*((volatile word *)0x0000E40F))


  /*** SIM_SD0 - STOP Disable Register 0; 0x0000E410 ***/
  union {
    word Word;
  } SIM_SD0_STR;

  #define SIM_SD0_GPIOG_MASK            0x01U
  #define SIM_SD0_GPIOF_MASK            0x02U
  #define SIM_SD0_GPIOE_MASK            0x04U
  #define SIM_SD0_GPIOD_MASK            0x08U
  #define SIM_SD0_GPIOC_MASK            0x10U
  #define SIM_SD0_GPIOB_MASK            0x20U
  #define SIM_SD0_GPIOA_MASK            0x40U
  #define SIM_SD0_TB3_MASK              0x0100U
  #define SIM_SD0_TB2_MASK              0x0200U
  #define SIM_SD0_TB1_MASK              0x0400U
  #define SIM_SD0_TB0_MASK              0x0800U
  #define SIM_SD0_TA3_MASK              0x1000U
  #define SIM_SD0_TA2_MASK              0x2000U
  #define SIM_SD0_TA1_MASK              0x4000U
  #define SIM_SD0_TA0_MASK              0x8000U
  #define SIM_SD0                       (*((volatile word *)0x0000E410))


  /*** SIM_SD1 - Peripheral Clock STOP Disable Register 1; 0x0000E411 ***/
  union {
    word Word;
  } SIM_SD1_STR;

  #define SIM_SD1_FLEXCAN_MASK          0x01U
  #define SIM_SD1_IIC1_MASK             0x20U
  #define SIM_SD1_IIC0_MASK             0x40U
  #define SIM_SD1_QSPI2_MASK            0x80U
  #define SIM_SD1_QSPI1_MASK            0x0100U
  #define SIM_SD1_QSPI0_MASK            0x0200U
  #define SIM_SD1_SCI2_MASK             0x0400U
  #define SIM_SD1_SCI1_MASK             0x0800U
  #define SIM_SD1_SCI0_MASK             0x1000U
  #define SIM_SD1_DAC_MASK              0x2000U
  #define SIM_SD1                       (*((volatile word *)0x0000E411))


  /*** SIM_SD2 - Peripheral Clock STOP Disable Register 2; 0x0000E412 ***/
  union {
    word Word;
  } SIM_SD2_STR;

  #define SIM_SD2_PDB1_MASK             0x01U
  #define SIM_SD2_PDB0_MASK             0x02U
  #define SIM_SD2_PIT1_MASK             0x04U
  #define SIM_SD2_PIT0_MASK             0x08U
  #define SIM_SD2_QDC_MASK              0x10U
  #define SIM_SD2_CRC_MASK              0x20U
  #define SIM_SD2_CYCADC_MASK           0x80U
  #define SIM_SD2_SARADC_MASK           0x0100U
  #define SIM_SD2_CMPD_MASK             0x0200U
  #define SIM_SD2_CMPC_MASK             0x0400U
  #define SIM_SD2_CMPB_MASK             0x0800U
  #define SIM_SD2_CMPA_MASK             0x1000U
  #define SIM_SD2                       (*((volatile word *)0x0000E412))


  /*** SIM_SD3 - Peripheral Clock STOP Disable Register 3; 0x0000E413 ***/
  union {
    word Word;
  } SIM_SD3_STR;

  #define SIM_SD3_PWMBCH3_MASK          0x01U
  #define SIM_SD3_PWMBCH2_MASK          0x02U
  #define SIM_SD3_PWMBCH1_MASK          0x04U
  #define SIM_SD3_PWMBCH0_MASK          0x08U
  #define SIM_SD3_PWMACH3_MASK          0x10U
  #define SIM_SD3_PWMACH2_MASK          0x20U
  #define SIM_SD3_PWMACH1_MASK          0x40U
  #define SIM_SD3_PWMACH0_MASK          0x80U
  #define SIM_SD3                       (*((volatile word *)0x0000E413))


  /*** SIM_IOSAHI - I/O Short Address Location Register; 0x0000E414 ***/
  union {
    word Word;
  } SIM_IOSAHI_STR;

  #define SIM_IOSAHI_ISAL0_MASK         0x01U
  #define SIM_IOSAHI_ISAL1_MASK         0x02U
  #define SIM_IOSAHI_ISAL_MASK          0x03U
  #define SIM_IOSAHI_ISAL_BITNUM        0x00U
  #define SIM_IOSAHI                    (*((volatile word *)0x0000E414))


  /*** SIM_IOSALO - I/O Short Address Location Register; 0x0000E415 ***/
  union {
    word Word;
  } SIM_IOSALO_STR;

  #define SIM_IOSALO                    (*((volatile word *)0x0000E415))


  /*** SIM_PROT - Protection Register; 0x0000E416 ***/
  union {
    word Word;
  } SIM_PROT_STR;

  #define SIM_PROT_GIPSP0_MASK          0x01U
  #define SIM_PROT_GIPSP1_MASK          0x02U
  #define SIM_PROT_PCEP0_MASK           0x04U
  #define SIM_PROT_PCEP1_MASK           0x08U
  #define SIM_PROT_GDP0_MASK            0x10U
  #define SIM_PROT_GDP1_MASK            0x20U
  #define SIM_PROT_PMODE0_MASK          0x40U
  #define SIM_PROT_PMODE1_MASK          0x80U
  #define SIM_PROT_GIPSP_MASK           0x03U
  #define SIM_PROT_GIPSP_BITNUM         0x00U
  #define SIM_PROT_PCEP_MASK            0x0CU
  #define SIM_PROT_PCEP_BITNUM          0x02U
  #define SIM_PROT_GDP_MASK             0x30U
  #define SIM_PROT_GDP_BITNUM           0x04U
  #define SIM_PROT_PMODE_MASK           0xC0U
  #define SIM_PROT_PMODE_BITNUM         0x06U
  #define SIM_PROT                      (*((volatile word *)0x0000E416))


  /*** SIM_GPSAL - GPIOA LSBs Peripheral Select Register; 0x0000E417 ***/
  union {
    word Word;
  } SIM_GPSAL_STR;

  #define SIM_GPSAL_A0_MASK             0x01U
  #define SIM_GPSAL                     (*((volatile word *)0x0000E417))


  /*** SIM_GPSBH - GPIOB MSBs Peripheral Select Register; 0x0000E418 ***/
  union {
    word Word;
  } SIM_GPSBH_STR;

  #define SIM_GPSBH_B90_MASK            0x04U
  #define SIM_GPSBH_B91_MASK            0x08U
  #define SIM_GPSBH_B100_MASK           0x10U
  #define SIM_GPSBH_B101_MASK           0x20U
  #define SIM_GPSBH_B110_MASK           0x40U
  #define SIM_GPSBH_B111_MASK           0x80U
  #define SIM_GPSBH_B9_MASK             0x0CU
  #define SIM_GPSBH_B9_BITNUM           0x02U
  #define SIM_GPSBH_B10_MASK            0x30U
  #define SIM_GPSBH_B10_BITNUM          0x04U
  #define SIM_GPSBH_B11_MASK            0xC0U
  #define SIM_GPSBH_B11_BITNUM          0x06U
  #define SIM_GPSBH                     (*((volatile word *)0x0000E418))


  /*** SIM_GPSCL - GPIOC LSBs Peripheral Select Register; 0x0000E419 ***/
  union {
    word Word;
  } SIM_GPSCL_STR;

  #define SIM_GPSCL_C0_MASK             0x01U
  #define SIM_GPSCL_C20_MASK            0x10U
  #define SIM_GPSCL_C21_MASK            0x20U
  #define SIM_GPSCL_C30_MASK            0x40U
  #define SIM_GPSCL_C31_MASK            0x80U
  #define SIM_GPSCL_C40_MASK            0x0100U
  #define SIM_GPSCL_C41_MASK            0x0200U
  #define SIM_GPSCL_C5_MASK             0x0400U
  #define SIM_GPSCL_C60_MASK            0x1000U
  #define SIM_GPSCL_C61_MASK            0x2000U
  #define SIM_GPSCL_C7_MASK             0x4000U
  #define SIM_GPSCL_C2_MASK             0x30U
  #define SIM_GPSCL_C2_BITNUM           0x04U
  #define SIM_GPSCL_C3_MASK             0xC0U
  #define SIM_GPSCL_C3_BITNUM           0x06U
  #define SIM_GPSCL_C4_MASK             0x0300U
  #define SIM_GPSCL_C4_BITNUM           0x08U
  #define SIM_GPSCL_C6_MASK             0x3000U
  #define SIM_GPSCL_C6_BITNUM           0x0CU
  #define SIM_GPSCL                     (*((volatile word *)0x0000E419))


  /*** SIM_GPSCH - GPIOC MSBs Peripheral Select Register; 0x0000E41A ***/
  union {
    word Word;
  } SIM_GPSCH_STR;

  #define SIM_GPSCH_C80_MASK            0x01U
  #define SIM_GPSCH_C81_MASK            0x02U
  #define SIM_GPSCH_C9_MASK             0x04U
  #define SIM_GPSCH_C100_MASK           0x10U
  #define SIM_GPSCH_C101_MASK           0x20U
  #define SIM_GPSCH_C110_MASK           0x40U
  #define SIM_GPSCH_C111_MASK           0x80U
  #define SIM_GPSCH_C120_MASK           0x0100U
  #define SIM_GPSCH_C121_MASK           0x0200U
  #define SIM_GPSCH_C130_MASK           0x0400U
  #define SIM_GPSCH_C131_MASK           0x0800U
  #define SIM_GPSCH_C14_MASK            0x1000U
  #define SIM_GPSCH_C15_MASK            0x4000U
  #define SIM_GPSCH_C8_MASK             0x03U
  #define SIM_GPSCH_C8_BITNUM           0x00U
  #define SIM_GPSCH_C10_MASK            0x30U
  #define SIM_GPSCH_C10_BITNUM          0x04U
  #define SIM_GPSCH_C11_MASK            0xC0U
  #define SIM_GPSCH_C11_BITNUM          0x06U
  #define SIM_GPSCH_C12_MASK            0x0300U
  #define SIM_GPSCH_C12_BITNUM          0x08U
  #define SIM_GPSCH_C13_MASK            0x0C00U
  #define SIM_GPSCH_C13_BITNUM          0x0AU
  #define SIM_GPSCH                     (*((volatile word *)0x0000E41A))


  /*** SIM_GPSDL - GPIOD LSBs Peripheral Select Register; 0x0000E41B ***/
  union {
    word Word;
  } SIM_GPSDL_STR;

  #define SIM_GPSDL_D50_MASK            0x0400U
  #define SIM_GPSDL_D51_MASK            0x0800U
  #define SIM_GPSDL_D60_MASK            0x1000U
  #define SIM_GPSDL_D61_MASK            0x2000U
  #define SIM_GPSDL_D70_MASK            0x4000U
  #define SIM_GPSDL_D71_MASK            0x8000U
  #define SIM_GPSDL_D5_MASK             0x0C00U
  #define SIM_GPSDL_D5_BITNUM           0x0AU
  #define SIM_GPSDL_D6_MASK             0x3000U
  #define SIM_GPSDL_D6_BITNUM           0x0CU
  #define SIM_GPSDL_D7_MASK             0xC000U
  #define SIM_GPSDL_D7_BITNUM           0x0EU
  #define SIM_GPSDL                     (*((volatile word *)0x0000E41B))


  /*** SIM_GPSEL - GPIOE LSBs Peripheral Select Register; 0x0000E41C ***/
  union {
    word Word;
  } SIM_GPSEL_STR;

  #define SIM_GPSEL_E4_MASK             0x0100U
  #define SIM_GPSEL_E5_MASK             0x0400U
  #define SIM_GPSEL_E60_MASK            0x1000U
  #define SIM_GPSEL_E61_MASK            0x2000U
  #define SIM_GPSEL_E70_MASK            0x4000U
  #define SIM_GPSEL_E71_MASK            0x8000U
  #define SIM_GPSEL_E6_MASK             0x3000U
  #define SIM_GPSEL_E6_BITNUM           0x0CU
  #define SIM_GPSEL_E7_MASK             0xC000U
  #define SIM_GPSEL_E7_BITNUM           0x0EU
  #define SIM_GPSEL                     (*((volatile word *)0x0000E41C))


  /*** SIM_GPSEH - GPIOE MSBs Peripheral Select Register; 0x0000E41D ***/
  union {
    word Word;
  } SIM_GPSEH_STR;

  #define SIM_GPSEH_E8_MASK             0x01U
  #define SIM_GPSEH_E9_MASK             0x04U
  #define SIM_GPSEH                     (*((volatile word *)0x0000E41D))


  /*** SIM_GPSFL - GPIOF LSBs Peripheral Select Register; 0x0000E41E ***/
  union {
    word Word;
  } SIM_GPSFL_STR;

  #define SIM_GPSFL_F00_MASK            0x01U
  #define SIM_GPSFL_F01_MASK            0x02U
  #define SIM_GPSFL_F10_MASK            0x04U
  #define SIM_GPSFL_F11_MASK            0x08U
  #define SIM_GPSFL_F2_MASK             0x10U
  #define SIM_GPSFL_F3_MASK             0x40U
  #define SIM_GPSFL_F4_MASK             0x0100U
  #define SIM_GPSFL_F5_MASK             0x0400U
  #define SIM_GPSFL_F60_MASK            0x1000U
  #define SIM_GPSFL_F61_MASK            0x2000U
  #define SIM_GPSFL_F70_MASK            0x4000U
  #define SIM_GPSFL_F71_MASK            0x8000U
  #define SIM_GPSFL_F0_MASK             0x03U
  #define SIM_GPSFL_F0_BITNUM           0x00U
  #define SIM_GPSFL_F1_MASK             0x0CU
  #define SIM_GPSFL_F1_BITNUM           0x02U
  #define SIM_GPSFL_F6_MASK             0x3000U
  #define SIM_GPSFL_F6_BITNUM           0x0CU
  #define SIM_GPSFL_F7_MASK             0xC000U
  #define SIM_GPSFL_F7_BITNUM           0x0EU
  #define SIM_GPSFL                     (*((volatile word *)0x0000E41E))


  /*** SIM_GPSFH - GPIOF MSBs Peripheral Select Register; 0x0000E41F ***/
  union {
    word Word;
  } SIM_GPSFH_STR;

  #define SIM_GPSFH_F80_MASK            0x01U
  #define SIM_GPSFH_F81_MASK            0x02U
  #define SIM_GPSFH_F90_MASK            0x04U
  #define SIM_GPSFH_F91_MASK            0x08U
  #define SIM_GPSFH_F100_MASK           0x10U
  #define SIM_GPSFH_F101_MASK           0x20U
  #define SIM_GPSFH_F11_MASK            0x40U
  #define SIM_GPSFH_F12_MASK            0x0100U
  #define SIM_GPSFH_F13_MASK            0x0400U
  #define SIM_GPSFH_F14_MASK            0x1000U
  #define SIM_GPSFH_F15_MASK            0x4000U
  #define SIM_GPSFH_F8_MASK             0x03U
  #define SIM_GPSFH_F8_BITNUM           0x00U
  #define SIM_GPSFH_F9_MASK             0x0CU
  #define SIM_GPSFH_F9_BITNUM           0x02U
  #define SIM_GPSFH_F10_MASK            0x30U
  #define SIM_GPSFH_F10_BITNUM          0x04U
  #define SIM_GPSFH                     (*((volatile word *)0x0000E41F))


  /*** SIM_GPSGL - GPIOG LSBs Peripheral Select Register; 0x0000E420 ***/
  union {
    word Word;
  } SIM_GPSGL_STR;

  #define SIM_GPSGL_G0_MASK             0x01U
  #define SIM_GPSGL_G1_MASK             0x04U
  #define SIM_GPSGL_G2_MASK             0x10U
  #define SIM_GPSGL_G3_MASK             0x40U
  #define SIM_GPSGL_G4_MASK             0x0100U
  #define SIM_GPSGL_G5_MASK             0x0400U
  #define SIM_GPSGL_G60_MASK            0x1000U
  #define SIM_GPSGL_G61_MASK            0x2000U
  #define SIM_GPSGL_G70_MASK            0x4000U
  #define SIM_GPSGL_G71_MASK            0x8000U
  #define SIM_GPSGL_G6_MASK             0x3000U
  #define SIM_GPSGL_G6_BITNUM           0x0CU
  #define SIM_GPSGL_G7_MASK             0xC000U
  #define SIM_GPSGL_G7_BITNUM           0x0EU
  #define SIM_GPSGL                     (*((volatile word *)0x0000E420))


  /*** SIM_GPSGH - GPIOG MSBs Peripheral Select Register; 0x0000E421 ***/
  union {
    word Word;
  } SIM_GPSGH_STR;

  #define SIM_GPSGH_G80_MASK            0x01U
  #define SIM_GPSGH_G81_MASK            0x02U
  #define SIM_GPSGH_G90_MASK            0x04U
  #define SIM_GPSGH_G91_MASK            0x08U
  #define SIM_GPSGH_G100_MASK           0x10U
  #define SIM_GPSGH_G101_MASK           0x20U
  #define SIM_GPSGH_G110_MASK           0x40U
  #define SIM_GPSGH_G111_MASK           0x80U
  #define SIM_GPSGH_G8_MASK             0x03U
  #define SIM_GPSGH_G8_BITNUM           0x00U
  #define SIM_GPSGH_G9_MASK             0x0CU
  #define SIM_GPSGH_G9_BITNUM           0x02U
  #define SIM_GPSGH_G10_MASK            0x30U
  #define SIM_GPSGH_G10_BITNUM          0x04U
  #define SIM_GPSGH_G11_MASK            0xC0U
  #define SIM_GPSGH_G11_BITNUM          0x06U
  #define SIM_GPSGH                     (*((volatile word *)0x0000E421))


  /*** SIM_IPS0 - Internal Peripheral Select Register 0; 0x0000E422 ***/
  union {
    word Word;
  } SIM_IPS0_STR;

  #define SIM_IPS0_PWMAF0_MASK          0x01U
  #define SIM_IPS0_PWMAF1_MASK          0x02U
  #define SIM_IPS0_PWMAF2_MASK          0x04U
  #define SIM_IPS0_PWMAF3_MASK          0x08U
  #define SIM_IPS0_PWMBF0_MASK          0x10U
  #define SIM_IPS0_PWMBF1_MASK          0x20U
  #define SIM_IPS0_PWMBF2_MASK          0x40U
  #define SIM_IPS0_TA0_MASK             0x0100U
  #define SIM_IPS0_TA1_MASK             0x0200U
  #define SIM_IPS0_TA2_MASK             0x0400U
  #define SIM_IPS0_TA3_MASK             0x0800U
  #define SIM_IPS0_TB0_MASK             0x1000U
  #define SIM_IPS0_TB1_MASK             0x2000U
  #define SIM_IPS0_TB2_MASK             0x4000U
  #define SIM_IPS0_TB3_MASK             0x8000U
  #define SIM_IPS0                      (*((volatile word *)0x0000E422))


  /*** SIM_MISC0 - Miscellaneous Register 0; 0x0000E423 ***/
  union {
    word Word;
  } SIM_MISC0_STR;

  #define SIM_MISC0_PIT_MSTR_MASK       0x01U
  #define SIM_MISC0_CLKINSEL_MASK       0x02U
  #define SIM_MISC0                     (*((volatile word *)0x0000E423))


  /*** SIM_PSWR0 - Peripheral Software Reset Register 0; 0x0000E424 ***/
  union {
    word Word;
  } SIM_PSWR0_STR;

  #define SIM_PSWR0_GPIO_MASK           0x40U
  #define SIM_PSWR0_TB_MASK             0x0800U
  #define SIM_PSWR0_TA_MASK             0x8000U
  #define SIM_PSWR0                     (*((volatile word *)0x0000E424))


  /*** SIM_PSWR1 - Peripheral Software Reset Register 1; 0x0000E425 ***/
  union {
    word Word;
  } SIM_PSWR1_STR;

  #define SIM_PSWR1_FLEXCAN_MASK        0x01U
  #define SIM_PSWR1_IIC1_MASK           0x20U
  #define SIM_PSWR1_IIC0_MASK           0x40U
  #define SIM_PSWR1_QSPI2_MASK          0x80U
  #define SIM_PSWR1_QSPI1_MASK          0x0100U
  #define SIM_PSWR1_QSPI0_MASK          0x0200U
  #define SIM_PSWR1_SCI2_MASK           0x0400U
  #define SIM_PSWR1_SCI1_MASK           0x0800U
  #define SIM_PSWR1_SCI0_MASK           0x1000U
  #define SIM_PSWR1_DAC_MASK            0x2000U
  #define SIM_PSWR1                     (*((volatile word *)0x0000E425))


  /*** SIM_PSWR2 - Peripheral Software Reset Register 2; 0x0000E426 ***/
  union {
    word Word;
  } SIM_PSWR2_STR;

  #define SIM_PSWR2_PDB1_MASK           0x01U
  #define SIM_PSWR2_PDB0_MASK           0x02U
  #define SIM_PSWR2_PIT1_MASK           0x04U
  #define SIM_PSWR2_PIT0_MASK           0x08U
  #define SIM_PSWR2_QDC_MASK            0x10U
  #define SIM_PSWR2_CRC_MASK            0x20U
  #define SIM_PSWR2_CYCADC_MASK         0x80U
  #define SIM_PSWR2_SARADC_MASK         0x0100U
  #define SIM_PSWR2_CMP_MASK            0x1000U
  #define SIM_PSWR2_EWM_MASK            0x8000U
  #define SIM_PSWR2                     (*((volatile word *)0x0000E426))


  /*** SIM_PSWR3 - Peripheral Software Reset Register 3; 0x0000E427 ***/
  union {
    word Word;
  } SIM_PSWR3_STR;

  #define SIM_PSWR3_PWMB_MASK           0x08U
  #define SIM_PSWR3_PWMA_MASK           0x80U
  #define SIM_PSWR3                     (*((volatile word *)0x0000E427))


  /*** SIM_PWRMODE - Power Mode Register; 0x0000E428 ***/
  union {
    word Word;
  } SIM_PWRMODE_STR;

  #define SIM_PWRMODE_VLPMODE_MASK      0x01U
  #define SIM_PWRMODE_LPMODE_MASK       0x02U
  #define SIM_PWRMODE_VLPMS_MASK        0x0100U
  #define SIM_PWRMODE_LPMS_MASK         0x0200U
  #define SIM_PWRMODE                   (*((volatile word *)0x0000E428))


  word Reserved1[3];                   /* Reserved (unused) registers */

  /*** SIM_NVMOPT2H - Non-Volatile Memory Option Register 2 (High); 0x0000E42C ***/
  union {
    word Word;
  } SIM_NVMOPT2H_STR;

  #define SIM_NVMOPT2H_ROSC_8M_FTRIM0_MASK 0x01U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM1_MASK 0x02U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM2_MASK 0x04U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM3_MASK 0x08U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM4_MASK 0x10U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM5_MASK 0x20U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM6_MASK 0x40U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM7_MASK 0x80U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM8_MASK 0x0100U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM9_MASK 0x0200U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM0_MASK 0x0400U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM1_MASK 0x0800U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM2_MASK 0x1000U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM3_MASK 0x2000U
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM_MASK 0x03FFU
  #define SIM_NVMOPT2H_ROSC_8M_FTRIM_BITNUM 0x00U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM_MASK 0x3C00U
  #define SIM_NVMOPT2H_ROSC_8M_TTRIM_BITNUM 0x0AU
  #define SIM_NVMOPT2H                  (*((volatile word *)0x0000E42C))


  /*** SIM_NVMOPT2L - Non-Volatile Memory Option Register 2 (Low); 0x0000E42D ***/
  union {
    word Word;
  } SIM_NVMOPT2L_STR;

  #define SIM_NVMOPT2L_ROSC_32K_FTRIM0_MASK 0x01U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM1_MASK 0x02U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM2_MASK 0x04U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM3_MASK 0x08U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM4_MASK 0x10U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM5_MASK 0x20U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM6_MASK 0x40U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM7_MASK 0x80U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM8_MASK 0x0100U
  #define SIM_NVMOPT2L_PMC_BGTRIM0_MASK 0x1000U
  #define SIM_NVMOPT2L_PMC_BGTRIM1_MASK 0x2000U
  #define SIM_NVMOPT2L_PMC_BGTRIM2_MASK 0x4000U
  #define SIM_NVMOPT2L_PMC_BGTRIM3_MASK 0x8000U
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM_MASK 0x01FFU
  #define SIM_NVMOPT2L_ROSC_32K_FTRIM_BITNUM 0x00U
  #define SIM_NVMOPT2L_PMC_BGTRIM_MASK  0xF000U
  #define SIM_NVMOPT2L_PMC_BGTRIM_BITNUM 0x0CU
  #define SIM_NVMOPT2L                  (*((volatile word *)0x0000E42D))


  /*** SIM_NVMOPT3H - Non-Volatile Memory Option Register 3 (High); 0x0000E42E ***/
  union {
    word Word;
  } SIM_NVMOPT3H_STR;

  #define SIM_NVMOPT3H                  (*((volatile word *)0x0000E42E))


} SIM_PRPH;
/******************************************
*** Peripheral ADC12
*******************************************/
typedef volatile struct {
  /*** ADC12_CTRL1 - ADC Control Register 1; 0x0000E500 ***/
  union {
    word Word;
  } ADC12_CTRL1_STR;

  #define ADC12_CTRL1_SMODE0_MASK       0x01U
  #define ADC12_CTRL1_SMODE1_MASK       0x02U
  #define ADC12_CTRL1_SMODE2_MASK       0x04U
  #define ADC12_CTRL1_CHNCFG_L0_MASK    0x10U
  #define ADC12_CTRL1_CHNCFG_L1_MASK    0x20U
  #define ADC12_CTRL1_CHNCFG_L2_MASK    0x40U
  #define ADC12_CTRL1_CHNCFG_L3_MASK    0x80U
  #define ADC12_CTRL1_HLMTIE_MASK       0x0100U
  #define ADC12_CTRL1_LLMTIE_MASK       0x0200U
  #define ADC12_CTRL1_ZCIE_MASK         0x0400U
  #define ADC12_CTRL1_EOSIE0_MASK       0x0800U
  #define ADC12_CTRL1_SYNC0_MASK        0x1000U
  #define ADC12_CTRL1_START0_MASK       0x2000U
  #define ADC12_CTRL1_STOP0_MASK        0x4000U
  #define ADC12_CTRL1_DMAEN0_MASK       0x8000U
  #define ADC12_CTRL1_SMODE_MASK        0x07U
  #define ADC12_CTRL1_SMODE_BITNUM      0x00U
  #define ADC12_CTRL1_CHNCFG_L_MASK     0xF0U
  #define ADC12_CTRL1_CHNCFG_L_BITNUM   0x04U
  #define ADC12_CTRL1                   (*((volatile word *)0x0000E500))


  /*** ADC12_CTRL2 - ADC Control Register 2; 0x0000E501 ***/
  union {
    word Word;
  } ADC12_CTRL2_STR;

  #define ADC12_CTRL2_DIV00_MASK        0x01U
  #define ADC12_CTRL2_DIV01_MASK        0x02U
  #define ADC12_CTRL2_DIV02_MASK        0x04U
  #define ADC12_CTRL2_DIV03_MASK        0x08U
  #define ADC12_CTRL2_DIV04_MASK        0x10U
  #define ADC12_CTRL2_DIV05_MASK        0x20U
  #define ADC12_CTRL2_SIMULT_MASK       0x40U
  #define ADC12_CTRL2_CHNCFG_H0_MASK    0x80U
  #define ADC12_CTRL2_CHNCFG_H1_MASK    0x0100U
  #define ADC12_CTRL2_CHNCFG_H2_MASK    0x0200U
  #define ADC12_CTRL2_CHNCFG_H3_MASK    0x0400U
  #define ADC12_CTRL2_EOSIE1_MASK       0x0800U
  #define ADC12_CTRL2_SYNC1_MASK        0x1000U
  #define ADC12_CTRL2_START1_MASK       0x2000U
  #define ADC12_CTRL2_STOP1_MASK        0x4000U
  #define ADC12_CTRL2_DMAEN1_MASK       0x8000U
  #define ADC12_CTRL2_DIV0_MASK         0x3FU
  #define ADC12_CTRL2_DIV0_BITNUM       0x00U
  #define ADC12_CTRL2_CHNCFG_H_MASK     0x0780U
  #define ADC12_CTRL2_CHNCFG_H_BITNUM   0x07U
  #define ADC12_CTRL2                   (*((volatile word *)0x0000E501))


  /*** ADC12_ZXCTRL1 - ADC Zero Crossing Control 1 Register; 0x0000E502 ***/
  union {
    word Word;
  } ADC12_ZXCTRL1_STR;

  #define ADC12_ZXCTRL1_ZCE00_MASK      0x01U
  #define ADC12_ZXCTRL1_ZCE01_MASK      0x02U
  #define ADC12_ZXCTRL1_ZCE10_MASK      0x04U
  #define ADC12_ZXCTRL1_ZCE11_MASK      0x08U
  #define ADC12_ZXCTRL1_ZCE20_MASK      0x10U
  #define ADC12_ZXCTRL1_ZCE21_MASK      0x20U
  #define ADC12_ZXCTRL1_ZCE30_MASK      0x40U
  #define ADC12_ZXCTRL1_ZCE31_MASK      0x80U
  #define ADC12_ZXCTRL1_ZCE40_MASK      0x0100U
  #define ADC12_ZXCTRL1_ZCE41_MASK      0x0200U
  #define ADC12_ZXCTRL1_ZCE50_MASK      0x0400U
  #define ADC12_ZXCTRL1_ZCE51_MASK      0x0800U
  #define ADC12_ZXCTRL1_ZCE60_MASK      0x1000U
  #define ADC12_ZXCTRL1_ZCE61_MASK      0x2000U
  #define ADC12_ZXCTRL1_ZCE70_MASK      0x4000U
  #define ADC12_ZXCTRL1_ZCE71_MASK      0x8000U
  #define ADC12_ZXCTRL1_ZCE0_MASK       0x03U
  #define ADC12_ZXCTRL1_ZCE0_BITNUM     0x00U
  #define ADC12_ZXCTRL1_ZCE1_MASK       0x0CU
  #define ADC12_ZXCTRL1_ZCE1_BITNUM     0x02U
  #define ADC12_ZXCTRL1_ZCE2_MASK       0x30U
  #define ADC12_ZXCTRL1_ZCE2_BITNUM     0x04U
  #define ADC12_ZXCTRL1_ZCE3_MASK       0xC0U
  #define ADC12_ZXCTRL1_ZCE3_BITNUM     0x06U
  #define ADC12_ZXCTRL1_ZCE4_MASK       0x0300U
  #define ADC12_ZXCTRL1_ZCE4_BITNUM     0x08U
  #define ADC12_ZXCTRL1_ZCE5_MASK       0x0C00U
  #define ADC12_ZXCTRL1_ZCE5_BITNUM     0x0AU
  #define ADC12_ZXCTRL1_ZCE6_MASK       0x3000U
  #define ADC12_ZXCTRL1_ZCE6_BITNUM     0x0CU
  #define ADC12_ZXCTRL1_ZCE7_MASK       0xC000U
  #define ADC12_ZXCTRL1_ZCE7_BITNUM     0x0EU
  #define ADC12_ZXCTRL1                 (*((volatile word *)0x0000E502))


  /*** ADC12_ZXCTRL2 - ADC Zero Crossing Control 2 Register; 0x0000E503 ***/
  union {
    word Word;
  } ADC12_ZXCTRL2_STR;

  #define ADC12_ZXCTRL2_ZCE80_MASK      0x01U
  #define ADC12_ZXCTRL2_ZCE81_MASK      0x02U
  #define ADC12_ZXCTRL2_ZCE90_MASK      0x04U
  #define ADC12_ZXCTRL2_ZCE91_MASK      0x08U
  #define ADC12_ZXCTRL2_ZCE100_MASK     0x10U
  #define ADC12_ZXCTRL2_ZCE101_MASK     0x20U
  #define ADC12_ZXCTRL2_ZCE110_MASK     0x40U
  #define ADC12_ZXCTRL2_ZCE111_MASK     0x80U
  #define ADC12_ZXCTRL2_ZCE120_MASK     0x0100U
  #define ADC12_ZXCTRL2_ZCE121_MASK     0x0200U
  #define ADC12_ZXCTRL2_ZCE130_MASK     0x0400U
  #define ADC12_ZXCTRL2_ZCE131_MASK     0x0800U
  #define ADC12_ZXCTRL2_ZCE140_MASK     0x1000U
  #define ADC12_ZXCTRL2_ZCE141_MASK     0x2000U
  #define ADC12_ZXCTRL2_ZCE150_MASK     0x4000U
  #define ADC12_ZXCTRL2_ZCE151_MASK     0x8000U
  #define ADC12_ZXCTRL2_ZCE8_MASK       0x03U
  #define ADC12_ZXCTRL2_ZCE8_BITNUM     0x00U
  #define ADC12_ZXCTRL2_ZCE9_MASK       0x0CU
  #define ADC12_ZXCTRL2_ZCE9_BITNUM     0x02U
  #define ADC12_ZXCTRL2_ZCE10_MASK      0x30U
  #define ADC12_ZXCTRL2_ZCE10_BITNUM    0x04U
  #define ADC12_ZXCTRL2_ZCE11_MASK      0xC0U
  #define ADC12_ZXCTRL2_ZCE11_BITNUM    0x06U
  #define ADC12_ZXCTRL2_ZCE12_MASK      0x0300U
  #define ADC12_ZXCTRL2_ZCE12_BITNUM    0x08U
  #define ADC12_ZXCTRL2_ZCE13_MASK      0x0C00U
  #define ADC12_ZXCTRL2_ZCE13_BITNUM    0x0AU
  #define ADC12_ZXCTRL2_ZCE14_MASK      0x3000U
  #define ADC12_ZXCTRL2_ZCE14_BITNUM    0x0CU
  #define ADC12_ZXCTRL2_ZCE15_MASK      0xC000U
  #define ADC12_ZXCTRL2_ZCE15_BITNUM    0x0EU
  #define ADC12_ZXCTRL2                 (*((volatile word *)0x0000E503))


  /*** ADC12_CLIST1 - ADC Channel List Register 1; 0x0000E504 ***/
  union {
    word Word;
  } ADC12_CLIST1_STR;

  #define ADC12_CLIST1_SAMPLE00_MASK    0x01U
  #define ADC12_CLIST1_SAMPLE01_MASK    0x02U
  #define ADC12_CLIST1_SAMPLE02_MASK    0x04U
  #define ADC12_CLIST1_SAMPLE03_MASK    0x08U
  #define ADC12_CLIST1_SAMPLE10_MASK    0x10U
  #define ADC12_CLIST1_SAMPLE11_MASK    0x20U
  #define ADC12_CLIST1_SAMPLE12_MASK    0x40U
  #define ADC12_CLIST1_SAMPLE13_MASK    0x80U
  #define ADC12_CLIST1_SAMPLE20_MASK    0x0100U
  #define ADC12_CLIST1_SAMPLE21_MASK    0x0200U
  #define ADC12_CLIST1_SAMPLE22_MASK    0x0400U
  #define ADC12_CLIST1_SAMPLE23_MASK    0x0800U
  #define ADC12_CLIST1_SAMPLE30_MASK    0x1000U
  #define ADC12_CLIST1_SAMPLE31_MASK    0x2000U
  #define ADC12_CLIST1_SAMPLE32_MASK    0x4000U
  #define ADC12_CLIST1_SAMPLE33_MASK    0x8000U
  #define ADC12_CLIST1_SAMPLE0_MASK     0x0FU
  #define ADC12_CLIST1_SAMPLE0_BITNUM   0x00U
  #define ADC12_CLIST1_SAMPLE1_MASK     0xF0U
  #define ADC12_CLIST1_SAMPLE1_BITNUM   0x04U
  #define ADC12_CLIST1_SAMPLE2_MASK     0x0F00U
  #define ADC12_CLIST1_SAMPLE2_BITNUM   0x08U
  #define ADC12_CLIST1_SAMPLE3_MASK     0xF000U
  #define ADC12_CLIST1_SAMPLE3_BITNUM   0x0CU
  #define ADC12_CLIST1                  (*((volatile word *)0x0000E504))


  /*** ADC12_CLIST2 - ADC Channel List Register 2; 0x0000E505 ***/
  union {
    word Word;
  } ADC12_CLIST2_STR;

  #define ADC12_CLIST2_SAMPLE40_MASK    0x01U
  #define ADC12_CLIST2_SAMPLE41_MASK    0x02U
  #define ADC12_CLIST2_SAMPLE42_MASK    0x04U
  #define ADC12_CLIST2_SAMPLE43_MASK    0x08U
  #define ADC12_CLIST2_SAMPLE50_MASK    0x10U
  #define ADC12_CLIST2_SAMPLE51_MASK    0x20U
  #define ADC12_CLIST2_SAMPLE52_MASK    0x40U
  #define ADC12_CLIST2_SAMPLE53_MASK    0x80U
  #define ADC12_CLIST2_SAMPLE60_MASK    0x0100U
  #define ADC12_CLIST2_SAMPLE61_MASK    0x0200U
  #define ADC12_CLIST2_SAMPLE62_MASK    0x0400U
  #define ADC12_CLIST2_SAMPLE63_MASK    0x0800U
  #define ADC12_CLIST2_SAMPLE70_MASK    0x1000U
  #define ADC12_CLIST2_SAMPLE71_MASK    0x2000U
  #define ADC12_CLIST2_SAMPLE72_MASK    0x4000U
  #define ADC12_CLIST2_SAMPLE73_MASK    0x8000U
  #define ADC12_CLIST2_SAMPLE4_MASK     0x0FU
  #define ADC12_CLIST2_SAMPLE4_BITNUM   0x00U
  #define ADC12_CLIST2_SAMPLE5_MASK     0xF0U
  #define ADC12_CLIST2_SAMPLE5_BITNUM   0x04U
  #define ADC12_CLIST2_SAMPLE6_MASK     0x0F00U
  #define ADC12_CLIST2_SAMPLE6_BITNUM   0x08U
  #define ADC12_CLIST2_SAMPLE7_MASK     0xF000U
  #define ADC12_CLIST2_SAMPLE7_BITNUM   0x0CU
  #define ADC12_CLIST2                  (*((volatile word *)0x0000E505))


  /*** ADC12_CLIST3 - ADC Channel List Register 3; 0x0000E506 ***/
  union {
    word Word;
  } ADC12_CLIST3_STR;

  #define ADC12_CLIST3_SAMPLE80_MASK    0x01U
  #define ADC12_CLIST3_SAMPLE81_MASK    0x02U
  #define ADC12_CLIST3_SAMPLE82_MASK    0x04U
  #define ADC12_CLIST3_SAMPLE83_MASK    0x08U
  #define ADC12_CLIST3_SAMPLE90_MASK    0x10U
  #define ADC12_CLIST3_SAMPLE91_MASK    0x20U
  #define ADC12_CLIST3_SAMPLE92_MASK    0x40U
  #define ADC12_CLIST3_SAMPLE93_MASK    0x80U
  #define ADC12_CLIST3_SAMPLE100_MASK   0x0100U
  #define ADC12_CLIST3_SAMPLE101_MASK   0x0200U
  #define ADC12_CLIST3_SAMPLE102_MASK   0x0400U
  #define ADC12_CLIST3_SAMPLE103_MASK   0x0800U
  #define ADC12_CLIST3_SAMPLE110_MASK   0x1000U
  #define ADC12_CLIST3_SAMPLE111_MASK   0x2000U
  #define ADC12_CLIST3_SAMPLE112_MASK   0x4000U
  #define ADC12_CLIST3_SAMPLE113_MASK   0x8000U
  #define ADC12_CLIST3_SAMPLE8_MASK     0x0FU
  #define ADC12_CLIST3_SAMPLE8_BITNUM   0x00U
  #define ADC12_CLIST3_SAMPLE9_MASK     0xF0U
  #define ADC12_CLIST3_SAMPLE9_BITNUM   0x04U
  #define ADC12_CLIST3_SAMPLE10_MASK    0x0F00U
  #define ADC12_CLIST3_SAMPLE10_BITNUM  0x08U
  #define ADC12_CLIST3_SAMPLE11_MASK    0xF000U
  #define ADC12_CLIST3_SAMPLE11_BITNUM  0x0CU
  #define ADC12_CLIST3                  (*((volatile word *)0x0000E506))


  /*** ADC12_CLIST4 - ADC Channel List Register 4; 0x0000E507 ***/
  union {
    word Word;
  } ADC12_CLIST4_STR;

  #define ADC12_CLIST4_SAMPLE120_MASK   0x01U
  #define ADC12_CLIST4_SAMPLE121_MASK   0x02U
  #define ADC12_CLIST4_SAMPLE122_MASK   0x04U
  #define ADC12_CLIST4_SAMPLE123_MASK   0x08U
  #define ADC12_CLIST4_SAMPLE130_MASK   0x10U
  #define ADC12_CLIST4_SAMPLE131_MASK   0x20U
  #define ADC12_CLIST4_SAMPLE132_MASK   0x40U
  #define ADC12_CLIST4_SAMPLE133_MASK   0x80U
  #define ADC12_CLIST4_SAMPLE140_MASK   0x0100U
  #define ADC12_CLIST4_SAMPLE141_MASK   0x0200U
  #define ADC12_CLIST4_SAMPLE142_MASK   0x0400U
  #define ADC12_CLIST4_SAMPLE143_MASK   0x0800U
  #define ADC12_CLIST4_SAMPLE150_MASK   0x1000U
  #define ADC12_CLIST4_SAMPLE151_MASK   0x2000U
  #define ADC12_CLIST4_SAMPLE152_MASK   0x4000U
  #define ADC12_CLIST4_SAMPLE153_MASK   0x8000U
  #define ADC12_CLIST4_SAMPLE12_MASK    0x0FU
  #define ADC12_CLIST4_SAMPLE12_BITNUM  0x00U
  #define ADC12_CLIST4_SAMPLE13_MASK    0xF0U
  #define ADC12_CLIST4_SAMPLE13_BITNUM  0x04U
  #define ADC12_CLIST4_SAMPLE14_MASK    0x0F00U
  #define ADC12_CLIST4_SAMPLE14_BITNUM  0x08U
  #define ADC12_CLIST4_SAMPLE15_MASK    0xF000U
  #define ADC12_CLIST4_SAMPLE15_BITNUM  0x0CU
  #define ADC12_CLIST4                  (*((volatile word *)0x0000E507))


  /*** ADC12_SDIS - ADC Sample Disable Register; 0x0000E508 ***/
  union {
    word Word;
  } ADC12_SDIS_STR;

  #define ADC12_SDIS                    (*((volatile word *)0x0000E508))


  /*** ADC12_STAT - ADC Status Register; 0x0000E509 ***/
  union {
    word Word;
  } ADC12_STAT_STR;

  #define ADC12_STAT_UNDEFINED0_MASK    0x01U
  #define ADC12_STAT_UNDEFINED1_MASK    0x02U
  #define ADC12_STAT_UNDEFINED2_MASK    0x04U
  #define ADC12_STAT_UNDEFINED3_MASK    0x08U
  #define ADC12_STAT_UNDEFINED4_MASK    0x10U
  #define ADC12_STAT_UNDEFINED5_MASK    0x20U
  #define ADC12_STAT_UNDEFINED6_MASK    0x40U
  #define ADC12_STAT_UNDEFINED7_MASK    0x80U
  #define ADC12_STAT_HLMTI_MASK         0x0100U
  #define ADC12_STAT_LLMTI_MASK         0x0200U
  #define ADC12_STAT_ZCI_MASK           0x0400U
  #define ADC12_STAT_EOSI0_MASK         0x0800U
  #define ADC12_STAT_EOSI1_MASK         0x1000U
  #define ADC12_STAT_CIP1_MASK          0x4000U
  #define ADC12_STAT_CIP0_MASK          0x8000U
  #define ADC12_STAT_UNDEFINED_MASK     0xFFU
  #define ADC12_STAT_UNDEFINED_BITNUM   0x00U
  #define ADC12_STAT                    (*((volatile word *)0x0000E509))


  /*** ADC12_RDY - ADC Ready Register; 0x0000E50A ***/
  union {
    word Word;
  } ADC12_RDY_STR;

  #define ADC12_RDY                     (*((volatile word *)0x0000E50A))


  /*** ADC12_LOLIMSTAT - ADC Low Limit Status Register; 0x0000E50B ***/
  union {
    word Word;
  } ADC12_LOLIMSTAT_STR;

  #define ADC12_LOLIMSTAT               (*((volatile word *)0x0000E50B))


  /*** ADC12_HILIMSTAT - ADC High Limit Status Register; 0x0000E50C ***/
  union {
    word Word;
  } ADC12_HILIMSTAT_STR;

  #define ADC12_HILIMSTAT               (*((volatile word *)0x0000E50C))


  /*** ADC12_ZXSTAT - ADC Zero Crossing Status Register; 0x0000E50D ***/
  union {
    word Word;
  } ADC12_ZXSTAT_STR;

  #define ADC12_ZXSTAT                  (*((volatile word *)0x0000E50D))


  /*** ADC12_RSLT0 - ADC Result Registers with sign extension; 0x0000E50E ***/
  union {
    word Word;
  } ADC12_RSLT0_STR;

  #define ADC12_RSLT0_RSLT0_MASK        0x08U
  #define ADC12_RSLT0_RSLT1_MASK        0x10U
  #define ADC12_RSLT0_RSLT2_MASK        0x20U
  #define ADC12_RSLT0_RSLT3_MASK        0x40U
  #define ADC12_RSLT0_RSLT4_MASK        0x80U
  #define ADC12_RSLT0_RSLT5_MASK        0x0100U
  #define ADC12_RSLT0_RSLT6_MASK        0x0200U
  #define ADC12_RSLT0_RSLT7_MASK        0x0400U
  #define ADC12_RSLT0_RSLT8_MASK        0x0800U
  #define ADC12_RSLT0_RSLT9_MASK        0x1000U
  #define ADC12_RSLT0_RSLT10_MASK       0x2000U
  #define ADC12_RSLT0_RSLT11_MASK       0x4000U
  #define ADC12_RSLT0_SEXT_MASK         0x8000U
  #define ADC12_RSLT0_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT0_RSLT_BITNUM       0x03U
  #define ADC12_RSLT0                   (*((volatile word *)0x0000E50E))


  /*** ADC12_RSLT1 - ADC Result Registers with sign extension; 0x0000E50F ***/
  union {
    word Word;
  } ADC12_RSLT1_STR;

  #define ADC12_RSLT1_RSLT0_MASK        0x08U
  #define ADC12_RSLT1_RSLT1_MASK        0x10U
  #define ADC12_RSLT1_RSLT2_MASK        0x20U
  #define ADC12_RSLT1_RSLT3_MASK        0x40U
  #define ADC12_RSLT1_RSLT4_MASK        0x80U
  #define ADC12_RSLT1_RSLT5_MASK        0x0100U
  #define ADC12_RSLT1_RSLT6_MASK        0x0200U
  #define ADC12_RSLT1_RSLT7_MASK        0x0400U
  #define ADC12_RSLT1_RSLT8_MASK        0x0800U
  #define ADC12_RSLT1_RSLT9_MASK        0x1000U
  #define ADC12_RSLT1_RSLT10_MASK       0x2000U
  #define ADC12_RSLT1_RSLT11_MASK       0x4000U
  #define ADC12_RSLT1_SEXT_MASK         0x8000U
  #define ADC12_RSLT1_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT1_RSLT_BITNUM       0x03U
  #define ADC12_RSLT1                   (*((volatile word *)0x0000E50F))


  /*** ADC12_RSLT2 - ADC Result Registers with sign extension; 0x0000E510 ***/
  union {
    word Word;
  } ADC12_RSLT2_STR;

  #define ADC12_RSLT2_RSLT0_MASK        0x08U
  #define ADC12_RSLT2_RSLT1_MASK        0x10U
  #define ADC12_RSLT2_RSLT2_MASK        0x20U
  #define ADC12_RSLT2_RSLT3_MASK        0x40U
  #define ADC12_RSLT2_RSLT4_MASK        0x80U
  #define ADC12_RSLT2_RSLT5_MASK        0x0100U
  #define ADC12_RSLT2_RSLT6_MASK        0x0200U
  #define ADC12_RSLT2_RSLT7_MASK        0x0400U
  #define ADC12_RSLT2_RSLT8_MASK        0x0800U
  #define ADC12_RSLT2_RSLT9_MASK        0x1000U
  #define ADC12_RSLT2_RSLT10_MASK       0x2000U
  #define ADC12_RSLT2_RSLT11_MASK       0x4000U
  #define ADC12_RSLT2_SEXT_MASK         0x8000U
  #define ADC12_RSLT2_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT2_RSLT_BITNUM       0x03U
  #define ADC12_RSLT2                   (*((volatile word *)0x0000E510))


  /*** ADC12_RSLT3 - ADC Result Registers with sign extension; 0x0000E511 ***/
  union {
    word Word;
  } ADC12_RSLT3_STR;

  #define ADC12_RSLT3_RSLT0_MASK        0x08U
  #define ADC12_RSLT3_RSLT1_MASK        0x10U
  #define ADC12_RSLT3_RSLT2_MASK        0x20U
  #define ADC12_RSLT3_RSLT3_MASK        0x40U
  #define ADC12_RSLT3_RSLT4_MASK        0x80U
  #define ADC12_RSLT3_RSLT5_MASK        0x0100U
  #define ADC12_RSLT3_RSLT6_MASK        0x0200U
  #define ADC12_RSLT3_RSLT7_MASK        0x0400U
  #define ADC12_RSLT3_RSLT8_MASK        0x0800U
  #define ADC12_RSLT3_RSLT9_MASK        0x1000U
  #define ADC12_RSLT3_RSLT10_MASK       0x2000U
  #define ADC12_RSLT3_RSLT11_MASK       0x4000U
  #define ADC12_RSLT3_SEXT_MASK         0x8000U
  #define ADC12_RSLT3_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT3_RSLT_BITNUM       0x03U
  #define ADC12_RSLT3                   (*((volatile word *)0x0000E511))


  /*** ADC12_RSLT4 - ADC Result Registers with sign extension; 0x0000E512 ***/
  union {
    word Word;
  } ADC12_RSLT4_STR;

  #define ADC12_RSLT4_RSLT0_MASK        0x08U
  #define ADC12_RSLT4_RSLT1_MASK        0x10U
  #define ADC12_RSLT4_RSLT2_MASK        0x20U
  #define ADC12_RSLT4_RSLT3_MASK        0x40U
  #define ADC12_RSLT4_RSLT4_MASK        0x80U
  #define ADC12_RSLT4_RSLT5_MASK        0x0100U
  #define ADC12_RSLT4_RSLT6_MASK        0x0200U
  #define ADC12_RSLT4_RSLT7_MASK        0x0400U
  #define ADC12_RSLT4_RSLT8_MASK        0x0800U
  #define ADC12_RSLT4_RSLT9_MASK        0x1000U
  #define ADC12_RSLT4_RSLT10_MASK       0x2000U
  #define ADC12_RSLT4_RSLT11_MASK       0x4000U
  #define ADC12_RSLT4_SEXT_MASK         0x8000U
  #define ADC12_RSLT4_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT4_RSLT_BITNUM       0x03U
  #define ADC12_RSLT4                   (*((volatile word *)0x0000E512))


  /*** ADC12_RSLT5 - ADC Result Registers with sign extension; 0x0000E513 ***/
  union {
    word Word;
  } ADC12_RSLT5_STR;

  #define ADC12_RSLT5_RSLT0_MASK        0x08U
  #define ADC12_RSLT5_RSLT1_MASK        0x10U
  #define ADC12_RSLT5_RSLT2_MASK        0x20U
  #define ADC12_RSLT5_RSLT3_MASK        0x40U
  #define ADC12_RSLT5_RSLT4_MASK        0x80U
  #define ADC12_RSLT5_RSLT5_MASK        0x0100U
  #define ADC12_RSLT5_RSLT6_MASK        0x0200U
  #define ADC12_RSLT5_RSLT7_MASK        0x0400U
  #define ADC12_RSLT5_RSLT8_MASK        0x0800U
  #define ADC12_RSLT5_RSLT9_MASK        0x1000U
  #define ADC12_RSLT5_RSLT10_MASK       0x2000U
  #define ADC12_RSLT5_RSLT11_MASK       0x4000U
  #define ADC12_RSLT5_SEXT_MASK         0x8000U
  #define ADC12_RSLT5_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT5_RSLT_BITNUM       0x03U
  #define ADC12_RSLT5                   (*((volatile word *)0x0000E513))


  /*** ADC12_RSLT6 - ADC Result Registers with sign extension; 0x0000E514 ***/
  union {
    word Word;
  } ADC12_RSLT6_STR;

  #define ADC12_RSLT6_RSLT0_MASK        0x08U
  #define ADC12_RSLT6_RSLT1_MASK        0x10U
  #define ADC12_RSLT6_RSLT2_MASK        0x20U
  #define ADC12_RSLT6_RSLT3_MASK        0x40U
  #define ADC12_RSLT6_RSLT4_MASK        0x80U
  #define ADC12_RSLT6_RSLT5_MASK        0x0100U
  #define ADC12_RSLT6_RSLT6_MASK        0x0200U
  #define ADC12_RSLT6_RSLT7_MASK        0x0400U
  #define ADC12_RSLT6_RSLT8_MASK        0x0800U
  #define ADC12_RSLT6_RSLT9_MASK        0x1000U
  #define ADC12_RSLT6_RSLT10_MASK       0x2000U
  #define ADC12_RSLT6_RSLT11_MASK       0x4000U
  #define ADC12_RSLT6_SEXT_MASK         0x8000U
  #define ADC12_RSLT6_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT6_RSLT_BITNUM       0x03U
  #define ADC12_RSLT6                   (*((volatile word *)0x0000E514))


  /*** ADC12_RSLT7 - ADC Result Registers with sign extension; 0x0000E515 ***/
  union {
    word Word;
  } ADC12_RSLT7_STR;

  #define ADC12_RSLT7_RSLT0_MASK        0x08U
  #define ADC12_RSLT7_RSLT1_MASK        0x10U
  #define ADC12_RSLT7_RSLT2_MASK        0x20U
  #define ADC12_RSLT7_RSLT3_MASK        0x40U
  #define ADC12_RSLT7_RSLT4_MASK        0x80U
  #define ADC12_RSLT7_RSLT5_MASK        0x0100U
  #define ADC12_RSLT7_RSLT6_MASK        0x0200U
  #define ADC12_RSLT7_RSLT7_MASK        0x0400U
  #define ADC12_RSLT7_RSLT8_MASK        0x0800U
  #define ADC12_RSLT7_RSLT9_MASK        0x1000U
  #define ADC12_RSLT7_RSLT10_MASK       0x2000U
  #define ADC12_RSLT7_RSLT11_MASK       0x4000U
  #define ADC12_RSLT7_SEXT_MASK         0x8000U
  #define ADC12_RSLT7_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT7_RSLT_BITNUM       0x03U
  #define ADC12_RSLT7                   (*((volatile word *)0x0000E515))


  /*** ADC12_RSLT8 - ADC Result Registers with sign extension; 0x0000E516 ***/
  union {
    word Word;
  } ADC12_RSLT8_STR;

  #define ADC12_RSLT8_RSLT0_MASK        0x08U
  #define ADC12_RSLT8_RSLT1_MASK        0x10U
  #define ADC12_RSLT8_RSLT2_MASK        0x20U
  #define ADC12_RSLT8_RSLT3_MASK        0x40U
  #define ADC12_RSLT8_RSLT4_MASK        0x80U
  #define ADC12_RSLT8_RSLT5_MASK        0x0100U
  #define ADC12_RSLT8_RSLT6_MASK        0x0200U
  #define ADC12_RSLT8_RSLT7_MASK        0x0400U
  #define ADC12_RSLT8_RSLT8_MASK        0x0800U
  #define ADC12_RSLT8_RSLT9_MASK        0x1000U
  #define ADC12_RSLT8_RSLT10_MASK       0x2000U
  #define ADC12_RSLT8_RSLT11_MASK       0x4000U
  #define ADC12_RSLT8_SEXT_MASK         0x8000U
  #define ADC12_RSLT8_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT8_RSLT_BITNUM       0x03U
  #define ADC12_RSLT8                   (*((volatile word *)0x0000E516))


  /*** ADC12_RSLT9 - ADC Result Registers with sign extension; 0x0000E517 ***/
  union {
    word Word;
  } ADC12_RSLT9_STR;

  #define ADC12_RSLT9_RSLT0_MASK        0x08U
  #define ADC12_RSLT9_RSLT1_MASK        0x10U
  #define ADC12_RSLT9_RSLT2_MASK        0x20U
  #define ADC12_RSLT9_RSLT3_MASK        0x40U
  #define ADC12_RSLT9_RSLT4_MASK        0x80U
  #define ADC12_RSLT9_RSLT5_MASK        0x0100U
  #define ADC12_RSLT9_RSLT6_MASK        0x0200U
  #define ADC12_RSLT9_RSLT7_MASK        0x0400U
  #define ADC12_RSLT9_RSLT8_MASK        0x0800U
  #define ADC12_RSLT9_RSLT9_MASK        0x1000U
  #define ADC12_RSLT9_RSLT10_MASK       0x2000U
  #define ADC12_RSLT9_RSLT11_MASK       0x4000U
  #define ADC12_RSLT9_SEXT_MASK         0x8000U
  #define ADC12_RSLT9_RSLT_MASK         0x7FF8U
  #define ADC12_RSLT9_RSLT_BITNUM       0x03U
  #define ADC12_RSLT9                   (*((volatile word *)0x0000E517))


  /*** ADC12_RSLT10 - ADC Result Registers with sign extension; 0x0000E518 ***/
  union {
    word Word;
  } ADC12_RSLT10_STR;

  #define ADC12_RSLT10_RSLT0_MASK       0x08U
  #define ADC12_RSLT10_RSLT1_MASK       0x10U
  #define ADC12_RSLT10_RSLT2_MASK       0x20U
  #define ADC12_RSLT10_RSLT3_MASK       0x40U
  #define ADC12_RSLT10_RSLT4_MASK       0x80U
  #define ADC12_RSLT10_RSLT5_MASK       0x0100U
  #define ADC12_RSLT10_RSLT6_MASK       0x0200U
  #define ADC12_RSLT10_RSLT7_MASK       0x0400U
  #define ADC12_RSLT10_RSLT8_MASK       0x0800U
  #define ADC12_RSLT10_RSLT9_MASK       0x1000U
  #define ADC12_RSLT10_RSLT10_MASK      0x2000U
  #define ADC12_RSLT10_RSLT11_MASK      0x4000U
  #define ADC12_RSLT10_SEXT_MASK        0x8000U
  #define ADC12_RSLT10_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT10_RSLT_BITNUM      0x03U
  #define ADC12_RSLT10                  (*((volatile word *)0x0000E518))


  /*** ADC12_RSLT11 - ADC Result Registers with sign extension; 0x0000E519 ***/
  union {
    word Word;
  } ADC12_RSLT11_STR;

  #define ADC12_RSLT11_RSLT0_MASK       0x08U
  #define ADC12_RSLT11_RSLT1_MASK       0x10U
  #define ADC12_RSLT11_RSLT2_MASK       0x20U
  #define ADC12_RSLT11_RSLT3_MASK       0x40U
  #define ADC12_RSLT11_RSLT4_MASK       0x80U
  #define ADC12_RSLT11_RSLT5_MASK       0x0100U
  #define ADC12_RSLT11_RSLT6_MASK       0x0200U
  #define ADC12_RSLT11_RSLT7_MASK       0x0400U
  #define ADC12_RSLT11_RSLT8_MASK       0x0800U
  #define ADC12_RSLT11_RSLT9_MASK       0x1000U
  #define ADC12_RSLT11_RSLT10_MASK      0x2000U
  #define ADC12_RSLT11_RSLT11_MASK      0x4000U
  #define ADC12_RSLT11_SEXT_MASK        0x8000U
  #define ADC12_RSLT11_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT11_RSLT_BITNUM      0x03U
  #define ADC12_RSLT11                  (*((volatile word *)0x0000E519))


  /*** ADC12_RSLT12 - ADC Result Registers with sign extension; 0x0000E51A ***/
  union {
    word Word;
  } ADC12_RSLT12_STR;

  #define ADC12_RSLT12_RSLT0_MASK       0x08U
  #define ADC12_RSLT12_RSLT1_MASK       0x10U
  #define ADC12_RSLT12_RSLT2_MASK       0x20U
  #define ADC12_RSLT12_RSLT3_MASK       0x40U
  #define ADC12_RSLT12_RSLT4_MASK       0x80U
  #define ADC12_RSLT12_RSLT5_MASK       0x0100U
  #define ADC12_RSLT12_RSLT6_MASK       0x0200U
  #define ADC12_RSLT12_RSLT7_MASK       0x0400U
  #define ADC12_RSLT12_RSLT8_MASK       0x0800U
  #define ADC12_RSLT12_RSLT9_MASK       0x1000U
  #define ADC12_RSLT12_RSLT10_MASK      0x2000U
  #define ADC12_RSLT12_RSLT11_MASK      0x4000U
  #define ADC12_RSLT12_SEXT_MASK        0x8000U
  #define ADC12_RSLT12_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT12_RSLT_BITNUM      0x03U
  #define ADC12_RSLT12                  (*((volatile word *)0x0000E51A))


  /*** ADC12_RSLT13 - ADC Result Registers with sign extension; 0x0000E51B ***/
  union {
    word Word;
  } ADC12_RSLT13_STR;

  #define ADC12_RSLT13_RSLT0_MASK       0x08U
  #define ADC12_RSLT13_RSLT1_MASK       0x10U
  #define ADC12_RSLT13_RSLT2_MASK       0x20U
  #define ADC12_RSLT13_RSLT3_MASK       0x40U
  #define ADC12_RSLT13_RSLT4_MASK       0x80U
  #define ADC12_RSLT13_RSLT5_MASK       0x0100U
  #define ADC12_RSLT13_RSLT6_MASK       0x0200U
  #define ADC12_RSLT13_RSLT7_MASK       0x0400U
  #define ADC12_RSLT13_RSLT8_MASK       0x0800U
  #define ADC12_RSLT13_RSLT9_MASK       0x1000U
  #define ADC12_RSLT13_RSLT10_MASK      0x2000U
  #define ADC12_RSLT13_RSLT11_MASK      0x4000U
  #define ADC12_RSLT13_SEXT_MASK        0x8000U
  #define ADC12_RSLT13_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT13_RSLT_BITNUM      0x03U
  #define ADC12_RSLT13                  (*((volatile word *)0x0000E51B))


  /*** ADC12_RSLT14 - ADC Result Registers with sign extension; 0x0000E51C ***/
  union {
    word Word;
  } ADC12_RSLT14_STR;

  #define ADC12_RSLT14_RSLT0_MASK       0x08U
  #define ADC12_RSLT14_RSLT1_MASK       0x10U
  #define ADC12_RSLT14_RSLT2_MASK       0x20U
  #define ADC12_RSLT14_RSLT3_MASK       0x40U
  #define ADC12_RSLT14_RSLT4_MASK       0x80U
  #define ADC12_RSLT14_RSLT5_MASK       0x0100U
  #define ADC12_RSLT14_RSLT6_MASK       0x0200U
  #define ADC12_RSLT14_RSLT7_MASK       0x0400U
  #define ADC12_RSLT14_RSLT8_MASK       0x0800U
  #define ADC12_RSLT14_RSLT9_MASK       0x1000U
  #define ADC12_RSLT14_RSLT10_MASK      0x2000U
  #define ADC12_RSLT14_RSLT11_MASK      0x4000U
  #define ADC12_RSLT14_SEXT_MASK        0x8000U
  #define ADC12_RSLT14_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT14_RSLT_BITNUM      0x03U
  #define ADC12_RSLT14                  (*((volatile word *)0x0000E51C))


  /*** ADC12_RSLT15 - ADC Result Registers with sign extension; 0x0000E51D ***/
  union {
    word Word;
  } ADC12_RSLT15_STR;

  #define ADC12_RSLT15_RSLT0_MASK       0x08U
  #define ADC12_RSLT15_RSLT1_MASK       0x10U
  #define ADC12_RSLT15_RSLT2_MASK       0x20U
  #define ADC12_RSLT15_RSLT3_MASK       0x40U
  #define ADC12_RSLT15_RSLT4_MASK       0x80U
  #define ADC12_RSLT15_RSLT5_MASK       0x0100U
  #define ADC12_RSLT15_RSLT6_MASK       0x0200U
  #define ADC12_RSLT15_RSLT7_MASK       0x0400U
  #define ADC12_RSLT15_RSLT8_MASK       0x0800U
  #define ADC12_RSLT15_RSLT9_MASK       0x1000U
  #define ADC12_RSLT15_RSLT10_MASK      0x2000U
  #define ADC12_RSLT15_RSLT11_MASK      0x4000U
  #define ADC12_RSLT15_SEXT_MASK        0x8000U
  #define ADC12_RSLT15_RSLT_MASK        0x7FF8U
  #define ADC12_RSLT15_RSLT_BITNUM      0x03U
  #define ADC12_RSLT15                  (*((volatile word *)0x0000E51D))


  /*** ADC12_LOLIM0 - ADC Low Limit Registers; 0x0000E51E ***/
  union {
    word Word;
  } ADC12_LOLIM0_STR;

  #define ADC12_LOLIM0_LLMT0_MASK       0x08U
  #define ADC12_LOLIM0_LLMT1_MASK       0x10U
  #define ADC12_LOLIM0_LLMT2_MASK       0x20U
  #define ADC12_LOLIM0_LLMT3_MASK       0x40U
  #define ADC12_LOLIM0_LLMT4_MASK       0x80U
  #define ADC12_LOLIM0_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM0_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM0_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM0_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM0_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM0_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM0_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM0_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM0_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM0                  (*((volatile word *)0x0000E51E))


  /*** ADC12_LOLIM1 - ADC Low Limit Registers; 0x0000E51F ***/
  union {
    word Word;
  } ADC12_LOLIM1_STR;

  #define ADC12_LOLIM1_LLMT0_MASK       0x08U
  #define ADC12_LOLIM1_LLMT1_MASK       0x10U
  #define ADC12_LOLIM1_LLMT2_MASK       0x20U
  #define ADC12_LOLIM1_LLMT3_MASK       0x40U
  #define ADC12_LOLIM1_LLMT4_MASK       0x80U
  #define ADC12_LOLIM1_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM1_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM1_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM1_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM1_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM1_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM1_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM1_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM1_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM1                  (*((volatile word *)0x0000E51F))


  /*** ADC12_LOLIM2 - ADC Low Limit Registers; 0x0000E520 ***/
  union {
    word Word;
  } ADC12_LOLIM2_STR;

  #define ADC12_LOLIM2_LLMT0_MASK       0x08U
  #define ADC12_LOLIM2_LLMT1_MASK       0x10U
  #define ADC12_LOLIM2_LLMT2_MASK       0x20U
  #define ADC12_LOLIM2_LLMT3_MASK       0x40U
  #define ADC12_LOLIM2_LLMT4_MASK       0x80U
  #define ADC12_LOLIM2_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM2_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM2_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM2_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM2_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM2_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM2_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM2_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM2_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM2                  (*((volatile word *)0x0000E520))


  /*** ADC12_LOLIM3 - ADC Low Limit Registers; 0x0000E521 ***/
  union {
    word Word;
  } ADC12_LOLIM3_STR;

  #define ADC12_LOLIM3_LLMT0_MASK       0x08U
  #define ADC12_LOLIM3_LLMT1_MASK       0x10U
  #define ADC12_LOLIM3_LLMT2_MASK       0x20U
  #define ADC12_LOLIM3_LLMT3_MASK       0x40U
  #define ADC12_LOLIM3_LLMT4_MASK       0x80U
  #define ADC12_LOLIM3_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM3_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM3_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM3_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM3_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM3_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM3_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM3_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM3_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM3                  (*((volatile word *)0x0000E521))


  /*** ADC12_LOLIM4 - ADC Low Limit Registers; 0x0000E522 ***/
  union {
    word Word;
  } ADC12_LOLIM4_STR;

  #define ADC12_LOLIM4_LLMT0_MASK       0x08U
  #define ADC12_LOLIM4_LLMT1_MASK       0x10U
  #define ADC12_LOLIM4_LLMT2_MASK       0x20U
  #define ADC12_LOLIM4_LLMT3_MASK       0x40U
  #define ADC12_LOLIM4_LLMT4_MASK       0x80U
  #define ADC12_LOLIM4_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM4_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM4_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM4_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM4_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM4_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM4_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM4_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM4_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM4                  (*((volatile word *)0x0000E522))


  /*** ADC12_LOLIM5 - ADC Low Limit Registers; 0x0000E523 ***/
  union {
    word Word;
  } ADC12_LOLIM5_STR;

  #define ADC12_LOLIM5_LLMT0_MASK       0x08U
  #define ADC12_LOLIM5_LLMT1_MASK       0x10U
  #define ADC12_LOLIM5_LLMT2_MASK       0x20U
  #define ADC12_LOLIM5_LLMT3_MASK       0x40U
  #define ADC12_LOLIM5_LLMT4_MASK       0x80U
  #define ADC12_LOLIM5_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM5_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM5_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM5_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM5_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM5_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM5_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM5_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM5_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM5                  (*((volatile word *)0x0000E523))


  /*** ADC12_LOLIM6 - ADC Low Limit Registers; 0x0000E524 ***/
  union {
    word Word;
  } ADC12_LOLIM6_STR;

  #define ADC12_LOLIM6_LLMT0_MASK       0x08U
  #define ADC12_LOLIM6_LLMT1_MASK       0x10U
  #define ADC12_LOLIM6_LLMT2_MASK       0x20U
  #define ADC12_LOLIM6_LLMT3_MASK       0x40U
  #define ADC12_LOLIM6_LLMT4_MASK       0x80U
  #define ADC12_LOLIM6_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM6_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM6_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM6_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM6_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM6_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM6_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM6_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM6_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM6                  (*((volatile word *)0x0000E524))


  /*** ADC12_LOLIM7 - ADC Low Limit Registers; 0x0000E525 ***/
  union {
    word Word;
  } ADC12_LOLIM7_STR;

  #define ADC12_LOLIM7_LLMT0_MASK       0x08U
  #define ADC12_LOLIM7_LLMT1_MASK       0x10U
  #define ADC12_LOLIM7_LLMT2_MASK       0x20U
  #define ADC12_LOLIM7_LLMT3_MASK       0x40U
  #define ADC12_LOLIM7_LLMT4_MASK       0x80U
  #define ADC12_LOLIM7_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM7_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM7_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM7_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM7_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM7_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM7_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM7_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM7_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM7                  (*((volatile word *)0x0000E525))


  /*** ADC12_LOLIM8 - ADC Low Limit Registers; 0x0000E526 ***/
  union {
    word Word;
  } ADC12_LOLIM8_STR;

  #define ADC12_LOLIM8_LLMT0_MASK       0x08U
  #define ADC12_LOLIM8_LLMT1_MASK       0x10U
  #define ADC12_LOLIM8_LLMT2_MASK       0x20U
  #define ADC12_LOLIM8_LLMT3_MASK       0x40U
  #define ADC12_LOLIM8_LLMT4_MASK       0x80U
  #define ADC12_LOLIM8_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM8_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM8_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM8_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM8_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM8_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM8_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM8_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM8_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM8                  (*((volatile word *)0x0000E526))


  /*** ADC12_LOLIM9 - ADC Low Limit Registers; 0x0000E527 ***/
  union {
    word Word;
  } ADC12_LOLIM9_STR;

  #define ADC12_LOLIM9_LLMT0_MASK       0x08U
  #define ADC12_LOLIM9_LLMT1_MASK       0x10U
  #define ADC12_LOLIM9_LLMT2_MASK       0x20U
  #define ADC12_LOLIM9_LLMT3_MASK       0x40U
  #define ADC12_LOLIM9_LLMT4_MASK       0x80U
  #define ADC12_LOLIM9_LLMT5_MASK       0x0100U
  #define ADC12_LOLIM9_LLMT6_MASK       0x0200U
  #define ADC12_LOLIM9_LLMT7_MASK       0x0400U
  #define ADC12_LOLIM9_LLMT8_MASK       0x0800U
  #define ADC12_LOLIM9_LLMT9_MASK       0x1000U
  #define ADC12_LOLIM9_LLMT10_MASK      0x2000U
  #define ADC12_LOLIM9_LLMT11_MASK      0x4000U
  #define ADC12_LOLIM9_LLMT_MASK        0x7FF8U
  #define ADC12_LOLIM9_LLMT_BITNUM      0x03U
  #define ADC12_LOLIM9                  (*((volatile word *)0x0000E527))


  /*** ADC12_LOLIM10 - ADC Low Limit Registers; 0x0000E528 ***/
  union {
    word Word;
  } ADC12_LOLIM10_STR;

  #define ADC12_LOLIM10_LLMT0_MASK      0x08U
  #define ADC12_LOLIM10_LLMT1_MASK      0x10U
  #define ADC12_LOLIM10_LLMT2_MASK      0x20U
  #define ADC12_LOLIM10_LLMT3_MASK      0x40U
  #define ADC12_LOLIM10_LLMT4_MASK      0x80U
  #define ADC12_LOLIM10_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM10_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM10_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM10_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM10_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM10_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM10_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM10_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM10_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM10                 (*((volatile word *)0x0000E528))


  /*** ADC12_LOLIM11 - ADC Low Limit Registers; 0x0000E529 ***/
  union {
    word Word;
  } ADC12_LOLIM11_STR;

  #define ADC12_LOLIM11_LLMT0_MASK      0x08U
  #define ADC12_LOLIM11_LLMT1_MASK      0x10U
  #define ADC12_LOLIM11_LLMT2_MASK      0x20U
  #define ADC12_LOLIM11_LLMT3_MASK      0x40U
  #define ADC12_LOLIM11_LLMT4_MASK      0x80U
  #define ADC12_LOLIM11_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM11_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM11_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM11_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM11_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM11_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM11_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM11_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM11_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM11                 (*((volatile word *)0x0000E529))


  /*** ADC12_LOLIM12 - ADC Low Limit Registers; 0x0000E52A ***/
  union {
    word Word;
  } ADC12_LOLIM12_STR;

  #define ADC12_LOLIM12_LLMT0_MASK      0x08U
  #define ADC12_LOLIM12_LLMT1_MASK      0x10U
  #define ADC12_LOLIM12_LLMT2_MASK      0x20U
  #define ADC12_LOLIM12_LLMT3_MASK      0x40U
  #define ADC12_LOLIM12_LLMT4_MASK      0x80U
  #define ADC12_LOLIM12_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM12_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM12_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM12_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM12_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM12_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM12_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM12_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM12_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM12                 (*((volatile word *)0x0000E52A))


  /*** ADC12_LOLIM13 - ADC Low Limit Registers; 0x0000E52B ***/
  union {
    word Word;
  } ADC12_LOLIM13_STR;

  #define ADC12_LOLIM13_LLMT0_MASK      0x08U
  #define ADC12_LOLIM13_LLMT1_MASK      0x10U
  #define ADC12_LOLIM13_LLMT2_MASK      0x20U
  #define ADC12_LOLIM13_LLMT3_MASK      0x40U
  #define ADC12_LOLIM13_LLMT4_MASK      0x80U
  #define ADC12_LOLIM13_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM13_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM13_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM13_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM13_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM13_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM13_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM13_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM13_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM13                 (*((volatile word *)0x0000E52B))


  /*** ADC12_LOLIM14 - ADC Low Limit Registers; 0x0000E52C ***/
  union {
    word Word;
  } ADC12_LOLIM14_STR;

  #define ADC12_LOLIM14_LLMT0_MASK      0x08U
  #define ADC12_LOLIM14_LLMT1_MASK      0x10U
  #define ADC12_LOLIM14_LLMT2_MASK      0x20U
  #define ADC12_LOLIM14_LLMT3_MASK      0x40U
  #define ADC12_LOLIM14_LLMT4_MASK      0x80U
  #define ADC12_LOLIM14_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM14_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM14_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM14_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM14_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM14_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM14_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM14_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM14_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM14                 (*((volatile word *)0x0000E52C))


  /*** ADC12_LOLIM15 - ADC Low Limit Registers; 0x0000E52D ***/
  union {
    word Word;
  } ADC12_LOLIM15_STR;

  #define ADC12_LOLIM15_LLMT0_MASK      0x08U
  #define ADC12_LOLIM15_LLMT1_MASK      0x10U
  #define ADC12_LOLIM15_LLMT2_MASK      0x20U
  #define ADC12_LOLIM15_LLMT3_MASK      0x40U
  #define ADC12_LOLIM15_LLMT4_MASK      0x80U
  #define ADC12_LOLIM15_LLMT5_MASK      0x0100U
  #define ADC12_LOLIM15_LLMT6_MASK      0x0200U
  #define ADC12_LOLIM15_LLMT7_MASK      0x0400U
  #define ADC12_LOLIM15_LLMT8_MASK      0x0800U
  #define ADC12_LOLIM15_LLMT9_MASK      0x1000U
  #define ADC12_LOLIM15_LLMT10_MASK     0x2000U
  #define ADC12_LOLIM15_LLMT11_MASK     0x4000U
  #define ADC12_LOLIM15_LLMT_MASK       0x7FF8U
  #define ADC12_LOLIM15_LLMT_BITNUM     0x03U
  #define ADC12_LOLIM15                 (*((volatile word *)0x0000E52D))


  /*** ADC12_HILIM0 - ADC High Limit Registers; 0x0000E52E ***/
  union {
    word Word;
  } ADC12_HILIM0_STR;

  #define ADC12_HILIM0_HLMT0_MASK       0x08U
  #define ADC12_HILIM0_HLMT1_MASK       0x10U
  #define ADC12_HILIM0_HLMT2_MASK       0x20U
  #define ADC12_HILIM0_HLMT3_MASK       0x40U
  #define ADC12_HILIM0_HLMT4_MASK       0x80U
  #define ADC12_HILIM0_HLMT5_MASK       0x0100U
  #define ADC12_HILIM0_HLMT6_MASK       0x0200U
  #define ADC12_HILIM0_HLMT7_MASK       0x0400U
  #define ADC12_HILIM0_HLMT8_MASK       0x0800U
  #define ADC12_HILIM0_HLMT9_MASK       0x1000U
  #define ADC12_HILIM0_HLMT10_MASK      0x2000U
  #define ADC12_HILIM0_HLMT11_MASK      0x4000U
  #define ADC12_HILIM0_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM0_HLMT_BITNUM      0x03U
  #define ADC12_HILIM0                  (*((volatile word *)0x0000E52E))


  /*** ADC12_HILIM1 - ADC High Limit Registers; 0x0000E52F ***/
  union {
    word Word;
  } ADC12_HILIM1_STR;

  #define ADC12_HILIM1_HLMT0_MASK       0x08U
  #define ADC12_HILIM1_HLMT1_MASK       0x10U
  #define ADC12_HILIM1_HLMT2_MASK       0x20U
  #define ADC12_HILIM1_HLMT3_MASK       0x40U
  #define ADC12_HILIM1_HLMT4_MASK       0x80U
  #define ADC12_HILIM1_HLMT5_MASK       0x0100U
  #define ADC12_HILIM1_HLMT6_MASK       0x0200U
  #define ADC12_HILIM1_HLMT7_MASK       0x0400U
  #define ADC12_HILIM1_HLMT8_MASK       0x0800U
  #define ADC12_HILIM1_HLMT9_MASK       0x1000U
  #define ADC12_HILIM1_HLMT10_MASK      0x2000U
  #define ADC12_HILIM1_HLMT11_MASK      0x4000U
  #define ADC12_HILIM1_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM1_HLMT_BITNUM      0x03U
  #define ADC12_HILIM1                  (*((volatile word *)0x0000E52F))


  /*** ADC12_HILIM2 - ADC High Limit Registers; 0x0000E530 ***/
  union {
    word Word;
  } ADC12_HILIM2_STR;

  #define ADC12_HILIM2_HLMT0_MASK       0x08U
  #define ADC12_HILIM2_HLMT1_MASK       0x10U
  #define ADC12_HILIM2_HLMT2_MASK       0x20U
  #define ADC12_HILIM2_HLMT3_MASK       0x40U
  #define ADC12_HILIM2_HLMT4_MASK       0x80U
  #define ADC12_HILIM2_HLMT5_MASK       0x0100U
  #define ADC12_HILIM2_HLMT6_MASK       0x0200U
  #define ADC12_HILIM2_HLMT7_MASK       0x0400U
  #define ADC12_HILIM2_HLMT8_MASK       0x0800U
  #define ADC12_HILIM2_HLMT9_MASK       0x1000U
  #define ADC12_HILIM2_HLMT10_MASK      0x2000U
  #define ADC12_HILIM2_HLMT11_MASK      0x4000U
  #define ADC12_HILIM2_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM2_HLMT_BITNUM      0x03U
  #define ADC12_HILIM2                  (*((volatile word *)0x0000E530))


  /*** ADC12_HILIM3 - ADC High Limit Registers; 0x0000E531 ***/
  union {
    word Word;
  } ADC12_HILIM3_STR;

  #define ADC12_HILIM3_HLMT0_MASK       0x08U
  #define ADC12_HILIM3_HLMT1_MASK       0x10U
  #define ADC12_HILIM3_HLMT2_MASK       0x20U
  #define ADC12_HILIM3_HLMT3_MASK       0x40U
  #define ADC12_HILIM3_HLMT4_MASK       0x80U
  #define ADC12_HILIM3_HLMT5_MASK       0x0100U
  #define ADC12_HILIM3_HLMT6_MASK       0x0200U
  #define ADC12_HILIM3_HLMT7_MASK       0x0400U
  #define ADC12_HILIM3_HLMT8_MASK       0x0800U
  #define ADC12_HILIM3_HLMT9_MASK       0x1000U
  #define ADC12_HILIM3_HLMT10_MASK      0x2000U
  #define ADC12_HILIM3_HLMT11_MASK      0x4000U
  #define ADC12_HILIM3_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM3_HLMT_BITNUM      0x03U
  #define ADC12_HILIM3                  (*((volatile word *)0x0000E531))


  /*** ADC12_HILIM4 - ADC High Limit Registers; 0x0000E532 ***/
  union {
    word Word;
  } ADC12_HILIM4_STR;

  #define ADC12_HILIM4_HLMT0_MASK       0x08U
  #define ADC12_HILIM4_HLMT1_MASK       0x10U
  #define ADC12_HILIM4_HLMT2_MASK       0x20U
  #define ADC12_HILIM4_HLMT3_MASK       0x40U
  #define ADC12_HILIM4_HLMT4_MASK       0x80U
  #define ADC12_HILIM4_HLMT5_MASK       0x0100U
  #define ADC12_HILIM4_HLMT6_MASK       0x0200U
  #define ADC12_HILIM4_HLMT7_MASK       0x0400U
  #define ADC12_HILIM4_HLMT8_MASK       0x0800U
  #define ADC12_HILIM4_HLMT9_MASK       0x1000U
  #define ADC12_HILIM4_HLMT10_MASK      0x2000U
  #define ADC12_HILIM4_HLMT11_MASK      0x4000U
  #define ADC12_HILIM4_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM4_HLMT_BITNUM      0x03U
  #define ADC12_HILIM4                  (*((volatile word *)0x0000E532))


  /*** ADC12_HILIM5 - ADC High Limit Registers; 0x0000E533 ***/
  union {
    word Word;
  } ADC12_HILIM5_STR;

  #define ADC12_HILIM5_HLMT0_MASK       0x08U
  #define ADC12_HILIM5_HLMT1_MASK       0x10U
  #define ADC12_HILIM5_HLMT2_MASK       0x20U
  #define ADC12_HILIM5_HLMT3_MASK       0x40U
  #define ADC12_HILIM5_HLMT4_MASK       0x80U
  #define ADC12_HILIM5_HLMT5_MASK       0x0100U
  #define ADC12_HILIM5_HLMT6_MASK       0x0200U
  #define ADC12_HILIM5_HLMT7_MASK       0x0400U
  #define ADC12_HILIM5_HLMT8_MASK       0x0800U
  #define ADC12_HILIM5_HLMT9_MASK       0x1000U
  #define ADC12_HILIM5_HLMT10_MASK      0x2000U
  #define ADC12_HILIM5_HLMT11_MASK      0x4000U
  #define ADC12_HILIM5_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM5_HLMT_BITNUM      0x03U
  #define ADC12_HILIM5                  (*((volatile word *)0x0000E533))


  /*** ADC12_HILIM6 - ADC High Limit Registers; 0x0000E534 ***/
  union {
    word Word;
  } ADC12_HILIM6_STR;

  #define ADC12_HILIM6_HLMT0_MASK       0x08U
  #define ADC12_HILIM6_HLMT1_MASK       0x10U
  #define ADC12_HILIM6_HLMT2_MASK       0x20U
  #define ADC12_HILIM6_HLMT3_MASK       0x40U
  #define ADC12_HILIM6_HLMT4_MASK       0x80U
  #define ADC12_HILIM6_HLMT5_MASK       0x0100U
  #define ADC12_HILIM6_HLMT6_MASK       0x0200U
  #define ADC12_HILIM6_HLMT7_MASK       0x0400U
  #define ADC12_HILIM6_HLMT8_MASK       0x0800U
  #define ADC12_HILIM6_HLMT9_MASK       0x1000U
  #define ADC12_HILIM6_HLMT10_MASK      0x2000U
  #define ADC12_HILIM6_HLMT11_MASK      0x4000U
  #define ADC12_HILIM6_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM6_HLMT_BITNUM      0x03U
  #define ADC12_HILIM6                  (*((volatile word *)0x0000E534))


  /*** ADC12_HILIM7 - ADC High Limit Registers; 0x0000E535 ***/
  union {
    word Word;
  } ADC12_HILIM7_STR;

  #define ADC12_HILIM7_HLMT0_MASK       0x08U
  #define ADC12_HILIM7_HLMT1_MASK       0x10U
  #define ADC12_HILIM7_HLMT2_MASK       0x20U
  #define ADC12_HILIM7_HLMT3_MASK       0x40U
  #define ADC12_HILIM7_HLMT4_MASK       0x80U
  #define ADC12_HILIM7_HLMT5_MASK       0x0100U
  #define ADC12_HILIM7_HLMT6_MASK       0x0200U
  #define ADC12_HILIM7_HLMT7_MASK       0x0400U
  #define ADC12_HILIM7_HLMT8_MASK       0x0800U
  #define ADC12_HILIM7_HLMT9_MASK       0x1000U
  #define ADC12_HILIM7_HLMT10_MASK      0x2000U
  #define ADC12_HILIM7_HLMT11_MASK      0x4000U
  #define ADC12_HILIM7_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM7_HLMT_BITNUM      0x03U
  #define ADC12_HILIM7                  (*((volatile word *)0x0000E535))


  /*** ADC12_HILIM8 - ADC High Limit Registers; 0x0000E536 ***/
  union {
    word Word;
  } ADC12_HILIM8_STR;

  #define ADC12_HILIM8_HLMT0_MASK       0x08U
  #define ADC12_HILIM8_HLMT1_MASK       0x10U
  #define ADC12_HILIM8_HLMT2_MASK       0x20U
  #define ADC12_HILIM8_HLMT3_MASK       0x40U
  #define ADC12_HILIM8_HLMT4_MASK       0x80U
  #define ADC12_HILIM8_HLMT5_MASK       0x0100U
  #define ADC12_HILIM8_HLMT6_MASK       0x0200U
  #define ADC12_HILIM8_HLMT7_MASK       0x0400U
  #define ADC12_HILIM8_HLMT8_MASK       0x0800U
  #define ADC12_HILIM8_HLMT9_MASK       0x1000U
  #define ADC12_HILIM8_HLMT10_MASK      0x2000U
  #define ADC12_HILIM8_HLMT11_MASK      0x4000U
  #define ADC12_HILIM8_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM8_HLMT_BITNUM      0x03U
  #define ADC12_HILIM8                  (*((volatile word *)0x0000E536))


  /*** ADC12_HILIM9 - ADC High Limit Registers; 0x0000E537 ***/
  union {
    word Word;
  } ADC12_HILIM9_STR;

  #define ADC12_HILIM9_HLMT0_MASK       0x08U
  #define ADC12_HILIM9_HLMT1_MASK       0x10U
  #define ADC12_HILIM9_HLMT2_MASK       0x20U
  #define ADC12_HILIM9_HLMT3_MASK       0x40U
  #define ADC12_HILIM9_HLMT4_MASK       0x80U
  #define ADC12_HILIM9_HLMT5_MASK       0x0100U
  #define ADC12_HILIM9_HLMT6_MASK       0x0200U
  #define ADC12_HILIM9_HLMT7_MASK       0x0400U
  #define ADC12_HILIM9_HLMT8_MASK       0x0800U
  #define ADC12_HILIM9_HLMT9_MASK       0x1000U
  #define ADC12_HILIM9_HLMT10_MASK      0x2000U
  #define ADC12_HILIM9_HLMT11_MASK      0x4000U
  #define ADC12_HILIM9_HLMT_MASK        0x7FF8U
  #define ADC12_HILIM9_HLMT_BITNUM      0x03U
  #define ADC12_HILIM9                  (*((volatile word *)0x0000E537))


  /*** ADC12_HILIM10 - ADC High Limit Registers; 0x0000E538 ***/
  union {
    word Word;
  } ADC12_HILIM10_STR;

  #define ADC12_HILIM10_HLMT0_MASK      0x08U
  #define ADC12_HILIM10_HLMT1_MASK      0x10U
  #define ADC12_HILIM10_HLMT2_MASK      0x20U
  #define ADC12_HILIM10_HLMT3_MASK      0x40U
  #define ADC12_HILIM10_HLMT4_MASK      0x80U
  #define ADC12_HILIM10_HLMT5_MASK      0x0100U
  #define ADC12_HILIM10_HLMT6_MASK      0x0200U
  #define ADC12_HILIM10_HLMT7_MASK      0x0400U
  #define ADC12_HILIM10_HLMT8_MASK      0x0800U
  #define ADC12_HILIM10_HLMT9_MASK      0x1000U
  #define ADC12_HILIM10_HLMT10_MASK     0x2000U
  #define ADC12_HILIM10_HLMT11_MASK     0x4000U
  #define ADC12_HILIM10_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM10_HLMT_BITNUM     0x03U
  #define ADC12_HILIM10                 (*((volatile word *)0x0000E538))


  /*** ADC12_HILIM11 - ADC High Limit Registers; 0x0000E539 ***/
  union {
    word Word;
  } ADC12_HILIM11_STR;

  #define ADC12_HILIM11_HLMT0_MASK      0x08U
  #define ADC12_HILIM11_HLMT1_MASK      0x10U
  #define ADC12_HILIM11_HLMT2_MASK      0x20U
  #define ADC12_HILIM11_HLMT3_MASK      0x40U
  #define ADC12_HILIM11_HLMT4_MASK      0x80U
  #define ADC12_HILIM11_HLMT5_MASK      0x0100U
  #define ADC12_HILIM11_HLMT6_MASK      0x0200U
  #define ADC12_HILIM11_HLMT7_MASK      0x0400U
  #define ADC12_HILIM11_HLMT8_MASK      0x0800U
  #define ADC12_HILIM11_HLMT9_MASK      0x1000U
  #define ADC12_HILIM11_HLMT10_MASK     0x2000U
  #define ADC12_HILIM11_HLMT11_MASK     0x4000U
  #define ADC12_HILIM11_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM11_HLMT_BITNUM     0x03U
  #define ADC12_HILIM11                 (*((volatile word *)0x0000E539))


  /*** ADC12_HILIM12 - ADC High Limit Registers; 0x0000E53A ***/
  union {
    word Word;
  } ADC12_HILIM12_STR;

  #define ADC12_HILIM12_HLMT0_MASK      0x08U
  #define ADC12_HILIM12_HLMT1_MASK      0x10U
  #define ADC12_HILIM12_HLMT2_MASK      0x20U
  #define ADC12_HILIM12_HLMT3_MASK      0x40U
  #define ADC12_HILIM12_HLMT4_MASK      0x80U
  #define ADC12_HILIM12_HLMT5_MASK      0x0100U
  #define ADC12_HILIM12_HLMT6_MASK      0x0200U
  #define ADC12_HILIM12_HLMT7_MASK      0x0400U
  #define ADC12_HILIM12_HLMT8_MASK      0x0800U
  #define ADC12_HILIM12_HLMT9_MASK      0x1000U
  #define ADC12_HILIM12_HLMT10_MASK     0x2000U
  #define ADC12_HILIM12_HLMT11_MASK     0x4000U
  #define ADC12_HILIM12_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM12_HLMT_BITNUM     0x03U
  #define ADC12_HILIM12                 (*((volatile word *)0x0000E53A))


  /*** ADC12_HILIM13 - ADC High Limit Registers; 0x0000E53B ***/
  union {
    word Word;
  } ADC12_HILIM13_STR;

  #define ADC12_HILIM13_HLMT0_MASK      0x08U
  #define ADC12_HILIM13_HLMT1_MASK      0x10U
  #define ADC12_HILIM13_HLMT2_MASK      0x20U
  #define ADC12_HILIM13_HLMT3_MASK      0x40U
  #define ADC12_HILIM13_HLMT4_MASK      0x80U
  #define ADC12_HILIM13_HLMT5_MASK      0x0100U
  #define ADC12_HILIM13_HLMT6_MASK      0x0200U
  #define ADC12_HILIM13_HLMT7_MASK      0x0400U
  #define ADC12_HILIM13_HLMT8_MASK      0x0800U
  #define ADC12_HILIM13_HLMT9_MASK      0x1000U
  #define ADC12_HILIM13_HLMT10_MASK     0x2000U
  #define ADC12_HILIM13_HLMT11_MASK     0x4000U
  #define ADC12_HILIM13_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM13_HLMT_BITNUM     0x03U
  #define ADC12_HILIM13                 (*((volatile word *)0x0000E53B))


  /*** ADC12_HILIM14 - ADC High Limit Registers; 0x0000E53C ***/
  union {
    word Word;
  } ADC12_HILIM14_STR;

  #define ADC12_HILIM14_HLMT0_MASK      0x08U
  #define ADC12_HILIM14_HLMT1_MASK      0x10U
  #define ADC12_HILIM14_HLMT2_MASK      0x20U
  #define ADC12_HILIM14_HLMT3_MASK      0x40U
  #define ADC12_HILIM14_HLMT4_MASK      0x80U
  #define ADC12_HILIM14_HLMT5_MASK      0x0100U
  #define ADC12_HILIM14_HLMT6_MASK      0x0200U
  #define ADC12_HILIM14_HLMT7_MASK      0x0400U
  #define ADC12_HILIM14_HLMT8_MASK      0x0800U
  #define ADC12_HILIM14_HLMT9_MASK      0x1000U
  #define ADC12_HILIM14_HLMT10_MASK     0x2000U
  #define ADC12_HILIM14_HLMT11_MASK     0x4000U
  #define ADC12_HILIM14_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM14_HLMT_BITNUM     0x03U
  #define ADC12_HILIM14                 (*((volatile word *)0x0000E53C))


  /*** ADC12_HILIM15 - ADC High Limit Registers; 0x0000E53D ***/
  union {
    word Word;
  } ADC12_HILIM15_STR;

  #define ADC12_HILIM15_HLMT0_MASK      0x08U
  #define ADC12_HILIM15_HLMT1_MASK      0x10U
  #define ADC12_HILIM15_HLMT2_MASK      0x20U
  #define ADC12_HILIM15_HLMT3_MASK      0x40U
  #define ADC12_HILIM15_HLMT4_MASK      0x80U
  #define ADC12_HILIM15_HLMT5_MASK      0x0100U
  #define ADC12_HILIM15_HLMT6_MASK      0x0200U
  #define ADC12_HILIM15_HLMT7_MASK      0x0400U
  #define ADC12_HILIM15_HLMT8_MASK      0x0800U
  #define ADC12_HILIM15_HLMT9_MASK      0x1000U
  #define ADC12_HILIM15_HLMT10_MASK     0x2000U
  #define ADC12_HILIM15_HLMT11_MASK     0x4000U
  #define ADC12_HILIM15_HLMT_MASK       0x7FF8U
  #define ADC12_HILIM15_HLMT_BITNUM     0x03U
  #define ADC12_HILIM15                 (*((volatile word *)0x0000E53D))


  /*** ADC12_OFFST0 - ADC Offset Registers; 0x0000E53E ***/
  union {
    word Word;
  } ADC12_OFFST0_STR;

  #define ADC12_OFFST0_OFFSET0_MASK     0x08U
  #define ADC12_OFFST0_OFFSET1_MASK     0x10U
  #define ADC12_OFFST0_OFFSET2_MASK     0x20U
  #define ADC12_OFFST0_OFFSET3_MASK     0x40U
  #define ADC12_OFFST0_OFFSET4_MASK     0x80U
  #define ADC12_OFFST0_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST0_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST0_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST0_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST0_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST0_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST0_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST0_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST0_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST0                  (*((volatile word *)0x0000E53E))


  /*** ADC12_OFFST1 - ADC Offset Registers; 0x0000E53F ***/
  union {
    word Word;
  } ADC12_OFFST1_STR;

  #define ADC12_OFFST1_OFFSET0_MASK     0x08U
  #define ADC12_OFFST1_OFFSET1_MASK     0x10U
  #define ADC12_OFFST1_OFFSET2_MASK     0x20U
  #define ADC12_OFFST1_OFFSET3_MASK     0x40U
  #define ADC12_OFFST1_OFFSET4_MASK     0x80U
  #define ADC12_OFFST1_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST1_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST1_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST1_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST1_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST1_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST1_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST1_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST1_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST1                  (*((volatile word *)0x0000E53F))


  /*** ADC12_OFFST2 - ADC Offset Registers; 0x0000E540 ***/
  union {
    word Word;
  } ADC12_OFFST2_STR;

  #define ADC12_OFFST2_OFFSET0_MASK     0x08U
  #define ADC12_OFFST2_OFFSET1_MASK     0x10U
  #define ADC12_OFFST2_OFFSET2_MASK     0x20U
  #define ADC12_OFFST2_OFFSET3_MASK     0x40U
  #define ADC12_OFFST2_OFFSET4_MASK     0x80U
  #define ADC12_OFFST2_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST2_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST2_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST2_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST2_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST2_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST2_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST2_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST2_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST2                  (*((volatile word *)0x0000E540))


  /*** ADC12_OFFST3 - ADC Offset Registers; 0x0000E541 ***/
  union {
    word Word;
  } ADC12_OFFST3_STR;

  #define ADC12_OFFST3_OFFSET0_MASK     0x08U
  #define ADC12_OFFST3_OFFSET1_MASK     0x10U
  #define ADC12_OFFST3_OFFSET2_MASK     0x20U
  #define ADC12_OFFST3_OFFSET3_MASK     0x40U
  #define ADC12_OFFST3_OFFSET4_MASK     0x80U
  #define ADC12_OFFST3_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST3_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST3_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST3_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST3_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST3_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST3_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST3_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST3_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST3                  (*((volatile word *)0x0000E541))


  /*** ADC12_OFFST4 - ADC Offset Registers; 0x0000E542 ***/
  union {
    word Word;
  } ADC12_OFFST4_STR;

  #define ADC12_OFFST4_OFFSET0_MASK     0x08U
  #define ADC12_OFFST4_OFFSET1_MASK     0x10U
  #define ADC12_OFFST4_OFFSET2_MASK     0x20U
  #define ADC12_OFFST4_OFFSET3_MASK     0x40U
  #define ADC12_OFFST4_OFFSET4_MASK     0x80U
  #define ADC12_OFFST4_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST4_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST4_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST4_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST4_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST4_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST4_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST4_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST4_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST4                  (*((volatile word *)0x0000E542))


  /*** ADC12_OFFST5 - ADC Offset Registers; 0x0000E543 ***/
  union {
    word Word;
  } ADC12_OFFST5_STR;

  #define ADC12_OFFST5_OFFSET0_MASK     0x08U
  #define ADC12_OFFST5_OFFSET1_MASK     0x10U
  #define ADC12_OFFST5_OFFSET2_MASK     0x20U
  #define ADC12_OFFST5_OFFSET3_MASK     0x40U
  #define ADC12_OFFST5_OFFSET4_MASK     0x80U
  #define ADC12_OFFST5_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST5_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST5_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST5_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST5_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST5_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST5_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST5_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST5_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST5                  (*((volatile word *)0x0000E543))


  /*** ADC12_OFFST6 - ADC Offset Registers; 0x0000E544 ***/
  union {
    word Word;
  } ADC12_OFFST6_STR;

  #define ADC12_OFFST6_OFFSET0_MASK     0x08U
  #define ADC12_OFFST6_OFFSET1_MASK     0x10U
  #define ADC12_OFFST6_OFFSET2_MASK     0x20U
  #define ADC12_OFFST6_OFFSET3_MASK     0x40U
  #define ADC12_OFFST6_OFFSET4_MASK     0x80U
  #define ADC12_OFFST6_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST6_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST6_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST6_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST6_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST6_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST6_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST6_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST6_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST6                  (*((volatile word *)0x0000E544))


  /*** ADC12_OFFST7 - ADC Offset Registers; 0x0000E545 ***/
  union {
    word Word;
  } ADC12_OFFST7_STR;

  #define ADC12_OFFST7_OFFSET0_MASK     0x08U
  #define ADC12_OFFST7_OFFSET1_MASK     0x10U
  #define ADC12_OFFST7_OFFSET2_MASK     0x20U
  #define ADC12_OFFST7_OFFSET3_MASK     0x40U
  #define ADC12_OFFST7_OFFSET4_MASK     0x80U
  #define ADC12_OFFST7_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST7_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST7_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST7_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST7_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST7_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST7_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST7_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST7_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST7                  (*((volatile word *)0x0000E545))


  /*** ADC12_OFFST8 - ADC Offset Registers; 0x0000E546 ***/
  union {
    word Word;
  } ADC12_OFFST8_STR;

  #define ADC12_OFFST8_OFFSET0_MASK     0x08U
  #define ADC12_OFFST8_OFFSET1_MASK     0x10U
  #define ADC12_OFFST8_OFFSET2_MASK     0x20U
  #define ADC12_OFFST8_OFFSET3_MASK     0x40U
  #define ADC12_OFFST8_OFFSET4_MASK     0x80U
  #define ADC12_OFFST8_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST8_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST8_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST8_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST8_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST8_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST8_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST8_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST8_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST8                  (*((volatile word *)0x0000E546))


  /*** ADC12_OFFST9 - ADC Offset Registers; 0x0000E547 ***/
  union {
    word Word;
  } ADC12_OFFST9_STR;

  #define ADC12_OFFST9_OFFSET0_MASK     0x08U
  #define ADC12_OFFST9_OFFSET1_MASK     0x10U
  #define ADC12_OFFST9_OFFSET2_MASK     0x20U
  #define ADC12_OFFST9_OFFSET3_MASK     0x40U
  #define ADC12_OFFST9_OFFSET4_MASK     0x80U
  #define ADC12_OFFST9_OFFSET5_MASK     0x0100U
  #define ADC12_OFFST9_OFFSET6_MASK     0x0200U
  #define ADC12_OFFST9_OFFSET7_MASK     0x0400U
  #define ADC12_OFFST9_OFFSET8_MASK     0x0800U
  #define ADC12_OFFST9_OFFSET9_MASK     0x1000U
  #define ADC12_OFFST9_OFFSET10_MASK    0x2000U
  #define ADC12_OFFST9_OFFSET11_MASK    0x4000U
  #define ADC12_OFFST9_OFFSET_MASK      0x7FF8U
  #define ADC12_OFFST9_OFFSET_BITNUM    0x03U
  #define ADC12_OFFST9                  (*((volatile word *)0x0000E547))


  /*** ADC12_OFFST10 - ADC Offset Registers; 0x0000E548 ***/
  union {
    word Word;
  } ADC12_OFFST10_STR;

  #define ADC12_OFFST10_OFFSET0_MASK    0x08U
  #define ADC12_OFFST10_OFFSET1_MASK    0x10U
  #define ADC12_OFFST10_OFFSET2_MASK    0x20U
  #define ADC12_OFFST10_OFFSET3_MASK    0x40U
  #define ADC12_OFFST10_OFFSET4_MASK    0x80U
  #define ADC12_OFFST10_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST10_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST10_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST10_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST10_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST10_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST10_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST10_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST10_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST10                 (*((volatile word *)0x0000E548))


  /*** ADC12_OFFST11 - ADC Offset Registers; 0x0000E549 ***/
  union {
    word Word;
  } ADC12_OFFST11_STR;

  #define ADC12_OFFST11_OFFSET0_MASK    0x08U
  #define ADC12_OFFST11_OFFSET1_MASK    0x10U
  #define ADC12_OFFST11_OFFSET2_MASK    0x20U
  #define ADC12_OFFST11_OFFSET3_MASK    0x40U
  #define ADC12_OFFST11_OFFSET4_MASK    0x80U
  #define ADC12_OFFST11_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST11_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST11_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST11_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST11_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST11_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST11_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST11_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST11_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST11                 (*((volatile word *)0x0000E549))


  /*** ADC12_OFFST12 - ADC Offset Registers; 0x0000E54A ***/
  union {
    word Word;
  } ADC12_OFFST12_STR;

  #define ADC12_OFFST12_OFFSET0_MASK    0x08U
  #define ADC12_OFFST12_OFFSET1_MASK    0x10U
  #define ADC12_OFFST12_OFFSET2_MASK    0x20U
  #define ADC12_OFFST12_OFFSET3_MASK    0x40U
  #define ADC12_OFFST12_OFFSET4_MASK    0x80U
  #define ADC12_OFFST12_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST12_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST12_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST12_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST12_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST12_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST12_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST12_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST12_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST12                 (*((volatile word *)0x0000E54A))


  /*** ADC12_OFFST13 - ADC Offset Registers; 0x0000E54B ***/
  union {
    word Word;
  } ADC12_OFFST13_STR;

  #define ADC12_OFFST13_OFFSET0_MASK    0x08U
  #define ADC12_OFFST13_OFFSET1_MASK    0x10U
  #define ADC12_OFFST13_OFFSET2_MASK    0x20U
  #define ADC12_OFFST13_OFFSET3_MASK    0x40U
  #define ADC12_OFFST13_OFFSET4_MASK    0x80U
  #define ADC12_OFFST13_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST13_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST13_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST13_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST13_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST13_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST13_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST13_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST13_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST13                 (*((volatile word *)0x0000E54B))


  /*** ADC12_OFFST14 - ADC Offset Registers; 0x0000E54C ***/
  union {
    word Word;
  } ADC12_OFFST14_STR;

  #define ADC12_OFFST14_OFFSET0_MASK    0x08U
  #define ADC12_OFFST14_OFFSET1_MASK    0x10U
  #define ADC12_OFFST14_OFFSET2_MASK    0x20U
  #define ADC12_OFFST14_OFFSET3_MASK    0x40U
  #define ADC12_OFFST14_OFFSET4_MASK    0x80U
  #define ADC12_OFFST14_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST14_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST14_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST14_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST14_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST14_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST14_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST14_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST14_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST14                 (*((volatile word *)0x0000E54C))


  /*** ADC12_OFFST15 - ADC Offset Registers; 0x0000E54D ***/
  union {
    word Word;
  } ADC12_OFFST15_STR;

  #define ADC12_OFFST15_OFFSET0_MASK    0x08U
  #define ADC12_OFFST15_OFFSET1_MASK    0x10U
  #define ADC12_OFFST15_OFFSET2_MASK    0x20U
  #define ADC12_OFFST15_OFFSET3_MASK    0x40U
  #define ADC12_OFFST15_OFFSET4_MASK    0x80U
  #define ADC12_OFFST15_OFFSET5_MASK    0x0100U
  #define ADC12_OFFST15_OFFSET6_MASK    0x0200U
  #define ADC12_OFFST15_OFFSET7_MASK    0x0400U
  #define ADC12_OFFST15_OFFSET8_MASK    0x0800U
  #define ADC12_OFFST15_OFFSET9_MASK    0x1000U
  #define ADC12_OFFST15_OFFSET10_MASK   0x2000U
  #define ADC12_OFFST15_OFFSET11_MASK   0x4000U
  #define ADC12_OFFST15_OFFSET_MASK     0x7FF8U
  #define ADC12_OFFST15_OFFSET_BITNUM   0x03U
  #define ADC12_OFFST15                 (*((volatile word *)0x0000E54D))


  /*** ADC12_PWR - ADC Power Control Register; 0x0000E54E ***/
  union {
    word Word;
  } ADC12_PWR_STR;

  #define ADC12_PWR_PD0_MASK            0x01U
  #define ADC12_PWR_PD1_MASK            0x02U
  #define ADC12_PWR_APD_MASK            0x08U
  #define ADC12_PWR_PUDELAY0_MASK       0x10U
  #define ADC12_PWR_PUDELAY1_MASK       0x20U
  #define ADC12_PWR_PUDELAY2_MASK       0x40U
  #define ADC12_PWR_PUDELAY3_MASK       0x80U
  #define ADC12_PWR_PUDELAY4_MASK       0x0100U
  #define ADC12_PWR_PUDELAY5_MASK       0x0200U
  #define ADC12_PWR_PSTS0_MASK          0x0400U
  #define ADC12_PWR_PSTS1_MASK          0x0800U
  #define ADC12_PWR_ASB_MASK            0x8000U
  #define ADC12_PWR_PUDELAY_MASK        0x03F0U
  #define ADC12_PWR_PUDELAY_BITNUM      0x04U
  #define ADC12_PWR                     (*((volatile word *)0x0000E54E))


  /*** ADC12_CAL - ADC Calibration Register; 0x0000E54F ***/
  union {
    word Word;
  } ADC12_CAL_STR;

  #define ADC12_CAL_SEL_DAC_A_MASK      0x01U
  #define ADC12_CAL_SEL_DAC_B_MASK      0x02U
  #define ADC12_CAL_SEL_VREFLO_A_MASK   0x1000U
  #define ADC12_CAL_SEL_VREFH_A_MASK    0x2000U
  #define ADC12_CAL_SEL_VREFLO_B_MASK   0x4000U
  #define ADC12_CAL_SEL_VREFH_B_MASK    0x8000U
  #define ADC12_CAL                     (*((volatile word *)0x0000E54F))


  /*** ADC12_GC1 - Gain Control 1 Register; 0x0000E550 ***/
  union {
    word Word;
  } ADC12_GC1_STR;

  #define ADC12_GC1_GAIN00_MASK         0x01U
  #define ADC12_GC1_GAIN01_MASK         0x02U
  #define ADC12_GC1_GAIN10_MASK         0x04U
  #define ADC12_GC1_GAIN11_MASK         0x08U
  #define ADC12_GC1_GAIN20_MASK         0x10U
  #define ADC12_GC1_GAIN21_MASK         0x20U
  #define ADC12_GC1_GAIN30_MASK         0x40U
  #define ADC12_GC1_GAIN31_MASK         0x80U
  #define ADC12_GC1_GAIN40_MASK         0x0100U
  #define ADC12_GC1_GAIN41_MASK         0x0200U
  #define ADC12_GC1_GAIN50_MASK         0x0400U
  #define ADC12_GC1_GAIN51_MASK         0x0800U
  #define ADC12_GC1_GAIN60_MASK         0x1000U
  #define ADC12_GC1_GAIN61_MASK         0x2000U
  #define ADC12_GC1_GAIN70_MASK         0x4000U
  #define ADC12_GC1_GAIN71_MASK         0x8000U
  #define ADC12_GC1_GAIN0_MASK          0x03U
  #define ADC12_GC1_GAIN0_BITNUM        0x00U
  #define ADC12_GC1_GAIN1_MASK          0x0CU
  #define ADC12_GC1_GAIN1_BITNUM        0x02U
  #define ADC12_GC1_GAIN2_MASK          0x30U
  #define ADC12_GC1_GAIN2_BITNUM        0x04U
  #define ADC12_GC1_GAIN3_MASK          0xC0U
  #define ADC12_GC1_GAIN3_BITNUM        0x06U
  #define ADC12_GC1_GAIN4_MASK          0x0300U
  #define ADC12_GC1_GAIN4_BITNUM        0x08U
  #define ADC12_GC1_GAIN5_MASK          0x0C00U
  #define ADC12_GC1_GAIN5_BITNUM        0x0AU
  #define ADC12_GC1_GAIN6_MASK          0x3000U
  #define ADC12_GC1_GAIN6_BITNUM        0x0CU
  #define ADC12_GC1_GAIN7_MASK          0xC000U
  #define ADC12_GC1_GAIN7_BITNUM        0x0EU
  #define ADC12_GC1                     (*((volatile word *)0x0000E550))


  /*** ADC12_GC2 - Gain Control 2 Register; 0x0000E551 ***/
  union {
    word Word;
  } ADC12_GC2_STR;

  #define ADC12_GC2_GAIN80_MASK         0x01U
  #define ADC12_GC2_GAIN81_MASK         0x02U
  #define ADC12_GC2_GAIN90_MASK         0x04U
  #define ADC12_GC2_GAIN91_MASK         0x08U
  #define ADC12_GC2_GAIN100_MASK        0x10U
  #define ADC12_GC2_GAIN101_MASK        0x20U
  #define ADC12_GC2_GAIN110_MASK        0x40U
  #define ADC12_GC2_GAIN111_MASK        0x80U
  #define ADC12_GC2_GAIN120_MASK        0x0100U
  #define ADC12_GC2_GAIN121_MASK        0x0200U
  #define ADC12_GC2_GAIN130_MASK        0x0400U
  #define ADC12_GC2_GAIN131_MASK        0x0800U
  #define ADC12_GC2_GAIN140_MASK        0x1000U
  #define ADC12_GC2_GAIN141_MASK        0x2000U
  #define ADC12_GC2_GAIN150_MASK        0x4000U
  #define ADC12_GC2_GAIN151_MASK        0x8000U
  #define ADC12_GC2_GAIN8_MASK          0x03U
  #define ADC12_GC2_GAIN8_BITNUM        0x00U
  #define ADC12_GC2_GAIN9_MASK          0x0CU
  #define ADC12_GC2_GAIN9_BITNUM        0x02U
  #define ADC12_GC2_GAIN10_MASK         0x30U
  #define ADC12_GC2_GAIN10_BITNUM       0x04U
  #define ADC12_GC2_GAIN11_MASK         0xC0U
  #define ADC12_GC2_GAIN11_BITNUM       0x06U
  #define ADC12_GC2_GAIN12_MASK         0x0300U
  #define ADC12_GC2_GAIN12_BITNUM       0x08U
  #define ADC12_GC2_GAIN13_MASK         0x0C00U
  #define ADC12_GC2_GAIN13_BITNUM       0x0AU
  #define ADC12_GC2_GAIN14_MASK         0x3000U
  #define ADC12_GC2_GAIN14_BITNUM       0x0CU
  #define ADC12_GC2_GAIN15_MASK         0xC000U
  #define ADC12_GC2_GAIN15_BITNUM       0x0EU
  #define ADC12_GC2                     (*((volatile word *)0x0000E551))


  /*** ADC12_SCTRL - ADC Scan Control Register; 0x0000E552 ***/
  union {
    word Word;
  } ADC12_SCTRL_STR;

  #define ADC12_SCTRL                   (*((volatile word *)0x0000E552))


  /*** ADC12_PWR2 - ADC Power Control Register; 0x0000E553 ***/
  union {
    word Word;
  } ADC12_PWR2_STR;

  #define ADC12_PWR2_SPEEDA0_MASK       0x01U
  #define ADC12_PWR2_SPEEDA1_MASK       0x02U
  #define ADC12_PWR2_SPEEDB0_MASK       0x04U
  #define ADC12_PWR2_SPEEDB1_MASK       0x08U
  #define ADC12_PWR2_DIV10_MASK         0x0100U
  #define ADC12_PWR2_DIV11_MASK         0x0200U
  #define ADC12_PWR2_DIV12_MASK         0x0400U
  #define ADC12_PWR2_DIV13_MASK         0x0800U
  #define ADC12_PWR2_DIV14_MASK         0x1000U
  #define ADC12_PWR2_DIV15_MASK         0x2000U
  #define ADC12_PWR2_SPEEDA_MASK        0x03U
  #define ADC12_PWR2_SPEEDA_BITNUM      0x00U
  #define ADC12_PWR2_SPEEDB_MASK        0x0CU
  #define ADC12_PWR2_SPEEDB_BITNUM      0x02U
  #define ADC12_PWR2_DIV1_MASK          0x3F00U
  #define ADC12_PWR2_DIV1_BITNUM        0x08U
  #define ADC12_PWR2                    (*((volatile word *)0x0000E553))


  /*** ADC12_CTRL3 - ADC Control Register 3; 0x0000E554 ***/
  union {
    word Word;
  } ADC12_CTRL3_STR;

  #define ADC12_CTRL3_SCNT00_MASK       0x01U
  #define ADC12_CTRL3_SCNT01_MASK       0x02U
  #define ADC12_CTRL3_SCNT02_MASK       0x04U
  #define ADC12_CTRL3_SCNT10_MASK       0x08U
  #define ADC12_CTRL3_SCNT11_MASK       0x10U
  #define ADC12_CTRL3_SCNT12_MASK       0x20U
  #define ADC12_CTRL3_DMASRC_MASK       0x40U
  #define ADC12_CTRL3_SCNT0_MASK        0x07U
  #define ADC12_CTRL3_SCNT0_BITNUM      0x00U
  #define ADC12_CTRL3_SCNT1_MASK        0x38U
  #define ADC12_CTRL3_SCNT1_BITNUM      0x03U
  #define ADC12_CTRL3                   (*((volatile word *)0x0000E554))


  /*** ADC12_SCHLTEN - ADC Scan Halted Interrupt Enable Register; 0x0000E555 ***/
  union {
    word Word;
  } ADC12_SCHLTEN_STR;

  #define ADC12_SCHLTEN                 (*((volatile word *)0x0000E555))


} ADC12_PRPH;
/******************************************
*** Peripheral ADC16
*******************************************/
typedef volatile struct {
  /*** ADC16_SC1A - ADC status and control registers 1; 0x0000E580 ***/
  union {
    dword Dword;
  } ADC16_SC1A_STR;

  #define ADC16_SC1A_ADCH0_MASK         0x01UL
  #define ADC16_SC1A_ADCH1_MASK         0x02UL
  #define ADC16_SC1A_ADCH2_MASK         0x04UL
  #define ADC16_SC1A_ADCH3_MASK         0x08UL
  #define ADC16_SC1A_ADCH4_MASK         0x10UL
  #define ADC16_SC1A_DIFF_MASK          0x20UL
  #define ADC16_SC1A_AIEN_MASK          0x40UL
  #define ADC16_SC1A_COCO_MASK          0x80UL
  #define ADC16_SC1A_ADCH_MASK          0x1FUL
  #define ADC16_SC1A_ADCH_BITNUM        0x00U
  #define ADC16_SC1A                    (*((volatile dword *)0x0000E580))


  dword Reserved0[1];                  /* Reserved (unused) registers */

  /*** ADC16_CFG1 - ADC configuration register 1; 0x0000E584 ***/
  union {
    dword Dword;
  } ADC16_CFG1_STR;

  #define ADC16_CFG1_ADICLK0_MASK       0x01UL
  #define ADC16_CFG1_ADICLK1_MASK       0x02UL
  #define ADC16_CFG1_MODE0_MASK         0x04UL
  #define ADC16_CFG1_MODE1_MASK         0x08UL
  #define ADC16_CFG1_ADLSMP_MASK        0x10UL
  #define ADC16_CFG1_ADIV0_MASK         0x20UL
  #define ADC16_CFG1_ADIV1_MASK         0x40UL
  #define ADC16_CFG1_ADLPC_MASK         0x80UL
  #define ADC16_CFG1_ADICLK_MASK        0x03UL
  #define ADC16_CFG1_ADICLK_BITNUM      0x00U
  #define ADC16_CFG1_MODE_MASK          0x0CUL
  #define ADC16_CFG1_MODE_BITNUM        0x02U
  #define ADC16_CFG1_ADIV_MASK          0x60UL
  #define ADC16_CFG1_ADIV_BITNUM        0x05U
  #define ADC16_CFG1                    (*((volatile dword *)0x0000E584))


  /*** ADC16_CFG2 - Configuration register 2; 0x0000E586 ***/
  union {
    dword Dword;
  } ADC16_CFG2_STR;

  #define ADC16_CFG2_ADLSTS0_MASK       0x01UL
  #define ADC16_CFG2_ADLSTS1_MASK       0x02UL
  #define ADC16_CFG2_ADHSC_MASK         0x04UL
  #define ADC16_CFG2_ADACKEN_MASK       0x08UL
  #define ADC16_CFG2_ADLSTS_MASK        0x03UL
  #define ADC16_CFG2_ADLSTS_BITNUM      0x00U
  #define ADC16_CFG2                    (*((volatile dword *)0x0000E586))


  /*** ADC16_RA - ADC data result register; 0x0000E588 ***/
  union {
    dword Dword;
  } ADC16_RA_STR;

  #define ADC16_RA_D0_MASK              0x01UL
  #define ADC16_RA_D1_MASK              0x02UL
  #define ADC16_RA_D2_MASK              0x04UL
  #define ADC16_RA_D3_MASK              0x08UL
  #define ADC16_RA_D4_MASK              0x10UL
  #define ADC16_RA_D5_MASK              0x20UL
  #define ADC16_RA_D6_MASK              0x40UL
  #define ADC16_RA_D7_MASK              0x80UL
  #define ADC16_RA_D8_MASK              0x0100UL
  #define ADC16_RA_D9_MASK              0x0200UL
  #define ADC16_RA_D10_MASK             0x0400UL
  #define ADC16_RA_D11_MASK             0x0800UL
  #define ADC16_RA_D12_MASK             0x1000UL
  #define ADC16_RA_D13_MASK             0x2000UL
  #define ADC16_RA_D14_MASK             0x4000UL
  #define ADC16_RA_D15_MASK             0x8000UL
  #define ADC16_RA_D_MASK               0xFFFFUL
  #define ADC16_RA_D_BITNUM             0x00U
  #define ADC16_RA                      (*((volatile dword *)0x0000E588))


  dword Reserved1[1];                  /* Reserved (unused) registers */

  /*** ADC16_CV1 - Compare value registers; 0x0000E58C ***/
  union {
    dword Dword;
  } ADC16_CV1_STR;

  #define ADC16_CV1_CV0_MASK            0x01UL
  #define ADC16_CV1_CV1_MASK            0x02UL
  #define ADC16_CV1_CV2_MASK            0x04UL
  #define ADC16_CV1_CV3_MASK            0x08UL
  #define ADC16_CV1_CV4_MASK            0x10UL
  #define ADC16_CV1_CV5_MASK            0x20UL
  #define ADC16_CV1_CV6_MASK            0x40UL
  #define ADC16_CV1_CV7_MASK            0x80UL
  #define ADC16_CV1_CV8_MASK            0x0100UL
  #define ADC16_CV1_CV9_MASK            0x0200UL
  #define ADC16_CV1_CV10_MASK           0x0400UL
  #define ADC16_CV1_CV11_MASK           0x0800UL
  #define ADC16_CV1_CV12_MASK           0x1000UL
  #define ADC16_CV1_CV13_MASK           0x2000UL
  #define ADC16_CV1_CV14_MASK           0x4000UL
  #define ADC16_CV1_CV15_MASK           0x8000UL
  #define ADC16_CV1_CV_MASK             0xFFFFUL
  #define ADC16_CV1_CV_BITNUM           0x00U
  #define ADC16_CV1                     (*((volatile dword *)0x0000E58C))


  /*** ADC16_CV2 - Compare value registers; 0x0000E58E ***/
  union {
    dword Dword;
  } ADC16_CV2_STR;

  #define ADC16_CV2_CV0_MASK            0x01UL
  #define ADC16_CV2_CV1_MASK            0x02UL
  #define ADC16_CV2_CV2_MASK            0x04UL
  #define ADC16_CV2_CV3_MASK            0x08UL
  #define ADC16_CV2_CV4_MASK            0x10UL
  #define ADC16_CV2_CV5_MASK            0x20UL
  #define ADC16_CV2_CV6_MASK            0x40UL
  #define ADC16_CV2_CV7_MASK            0x80UL
  #define ADC16_CV2_CV8_MASK            0x0100UL
  #define ADC16_CV2_CV9_MASK            0x0200UL
  #define ADC16_CV2_CV10_MASK           0x0400UL
  #define ADC16_CV2_CV11_MASK           0x0800UL
  #define ADC16_CV2_CV12_MASK           0x1000UL
  #define ADC16_CV2_CV13_MASK           0x2000UL
  #define ADC16_CV2_CV14_MASK           0x4000UL
  #define ADC16_CV2_CV15_MASK           0x8000UL
  #define ADC16_CV2_CV_MASK             0xFFFFUL
  #define ADC16_CV2_CV_BITNUM           0x00U
  #define ADC16_CV2                     (*((volatile dword *)0x0000E58E))


  /*** ADC16_SC2 - Status and control register 2; 0x0000E590 ***/
  union {
    dword Dword;
  } ADC16_SC2_STR;

  #define ADC16_SC2_REFSEL0_MASK        0x01UL
  #define ADC16_SC2_REFSEL1_MASK        0x02UL
  #define ADC16_SC2_DMAEN_MASK          0x04UL
  #define ADC16_SC2_ACREN_MASK          0x08UL
  #define ADC16_SC2_ACFGT_MASK          0x10UL
  #define ADC16_SC2_ACFE_MASK           0x20UL
  #define ADC16_SC2_ADTRG_MASK          0x40UL
  #define ADC16_SC2_ADACT_MASK          0x80UL
  #define ADC16_SC2_REFSEL_MASK         0x03UL
  #define ADC16_SC2_REFSEL_BITNUM       0x00U
  #define ADC16_SC2                     (*((volatile dword *)0x0000E590))


  /*** ADC16_SC3 - Status and control register 3; 0x0000E592 ***/
  union {
    dword Dword;
  } ADC16_SC3_STR;

  #define ADC16_SC3_AVGS0_MASK          0x01UL
  #define ADC16_SC3_AVGS1_MASK          0x02UL
  #define ADC16_SC3_AVGE_MASK           0x04UL
  #define ADC16_SC3_ADCO_MASK           0x08UL
  #define ADC16_SC3_ASSITRGEN_MASK      0x10UL
  #define ADC16_SC3_CALF_MASK           0x40UL
  #define ADC16_SC3_CAL_MASK            0x80UL
  #define ADC16_SC3_AVGS_MASK           0x03UL
  #define ADC16_SC3_AVGS_BITNUM         0x00U
  #define ADC16_SC3                     (*((volatile dword *)0x0000E592))


  /*** ADC16_OFS - ADC offset correction register; 0x0000E594 ***/
  union {
    dword Dword;
  } ADC16_OFS_STR;

  #define ADC16_OFS_OFS0_MASK           0x01UL
  #define ADC16_OFS_OFS1_MASK           0x02UL
  #define ADC16_OFS_OFS2_MASK           0x04UL
  #define ADC16_OFS_OFS3_MASK           0x08UL
  #define ADC16_OFS_OFS4_MASK           0x10UL
  #define ADC16_OFS_OFS5_MASK           0x20UL
  #define ADC16_OFS_OFS6_MASK           0x40UL
  #define ADC16_OFS_OFS7_MASK           0x80UL
  #define ADC16_OFS_OFS8_MASK           0x0100UL
  #define ADC16_OFS_OFS9_MASK           0x0200UL
  #define ADC16_OFS_OFS10_MASK          0x0400UL
  #define ADC16_OFS_OFS11_MASK          0x0800UL
  #define ADC16_OFS_OFS12_MASK          0x1000UL
  #define ADC16_OFS_OFS13_MASK          0x2000UL
  #define ADC16_OFS_OFS14_MASK          0x4000UL
  #define ADC16_OFS_OFS15_MASK          0x8000UL
  #define ADC16_OFS_OFS_MASK            0xFFFFUL
  #define ADC16_OFS_OFS_BITNUM          0x00U
  #define ADC16_OFS                     (*((volatile dword *)0x0000E594))


  /*** ADC16_PG - ADC plus-side gain register; 0x0000E596 ***/
  union {
    dword Dword;
  } ADC16_PG_STR;

  #define ADC16_PG_PG0_MASK             0x01UL
  #define ADC16_PG_PG1_MASK             0x02UL
  #define ADC16_PG_PG2_MASK             0x04UL
  #define ADC16_PG_PG3_MASK             0x08UL
  #define ADC16_PG_PG4_MASK             0x10UL
  #define ADC16_PG_PG5_MASK             0x20UL
  #define ADC16_PG_PG6_MASK             0x40UL
  #define ADC16_PG_PG7_MASK             0x80UL
  #define ADC16_PG_PG8_MASK             0x0100UL
  #define ADC16_PG_PG9_MASK             0x0200UL
  #define ADC16_PG_PG10_MASK            0x0400UL
  #define ADC16_PG_PG11_MASK            0x0800UL
  #define ADC16_PG_PG12_MASK            0x1000UL
  #define ADC16_PG_PG13_MASK            0x2000UL
  #define ADC16_PG_PG14_MASK            0x4000UL
  #define ADC16_PG_PG15_MASK            0x8000UL
  #define ADC16_PG_PG_MASK              0xFFFFUL
  #define ADC16_PG_PG_BITNUM            0x00U
  #define ADC16_PG                      (*((volatile dword *)0x0000E596))


  /*** ADC16_MG - ADC minus-side gain register; 0x0000E598 ***/
  union {
    dword Dword;
  } ADC16_MG_STR;

  #define ADC16_MG_MG0_MASK             0x01UL
  #define ADC16_MG_MG1_MASK             0x02UL
  #define ADC16_MG_MG2_MASK             0x04UL
  #define ADC16_MG_MG3_MASK             0x08UL
  #define ADC16_MG_MG4_MASK             0x10UL
  #define ADC16_MG_MG5_MASK             0x20UL
  #define ADC16_MG_MG6_MASK             0x40UL
  #define ADC16_MG_MG7_MASK             0x80UL
  #define ADC16_MG_MG8_MASK             0x0100UL
  #define ADC16_MG_MG9_MASK             0x0200UL
  #define ADC16_MG_MG10_MASK            0x0400UL
  #define ADC16_MG_MG11_MASK            0x0800UL
  #define ADC16_MG_MG12_MASK            0x1000UL
  #define ADC16_MG_MG13_MASK            0x2000UL
  #define ADC16_MG_MG14_MASK            0x4000UL
  #define ADC16_MG_MG15_MASK            0x8000UL
  #define ADC16_MG_MG_MASK              0xFFFFUL
  #define ADC16_MG_MG_BITNUM            0x00U
  #define ADC16_MG                      (*((volatile dword *)0x0000E598))


  /*** ADC16_CLPD - ADC plus-side general calibration value register; 0x0000E59A ***/
  union {
    dword Dword;
  } ADC16_CLPD_STR;

  #define ADC16_CLPD_CLPD0_MASK         0x01UL
  #define ADC16_CLPD_CLPD1_MASK         0x02UL
  #define ADC16_CLPD_CLPD2_MASK         0x04UL
  #define ADC16_CLPD_CLPD3_MASK         0x08UL
  #define ADC16_CLPD_CLPD4_MASK         0x10UL
  #define ADC16_CLPD_CLPD5_MASK         0x20UL
  #define ADC16_CLPD_CLPD_MASK          0x3FUL
  #define ADC16_CLPD_CLPD_BITNUM        0x00U
  #define ADC16_CLPD                    (*((volatile dword *)0x0000E59A))


  /*** ADC16_CLPS - ADC plus-side general calibration value register; 0x0000E59C ***/
  union {
    dword Dword;
  } ADC16_CLPS_STR;

  #define ADC16_CLPS_CLPS0_MASK         0x01UL
  #define ADC16_CLPS_CLPS1_MASK         0x02UL
  #define ADC16_CLPS_CLPS2_MASK         0x04UL
  #define ADC16_CLPS_CLPS3_MASK         0x08UL
  #define ADC16_CLPS_CLPS4_MASK         0x10UL
  #define ADC16_CLPS_CLPS5_MASK         0x20UL
  #define ADC16_CLPS_CLPS_MASK          0x3FUL
  #define ADC16_CLPS_CLPS_BITNUM        0x00U
  #define ADC16_CLPS                    (*((volatile dword *)0x0000E59C))


  /*** ADC16_CLP4 - ADC plus-side general calibration value register; 0x0000E59E ***/
  union {
    dword Dword;
  } ADC16_CLP4_STR;

  #define ADC16_CLP4_CLP40_MASK         0x01UL
  #define ADC16_CLP4_CLP41_MASK         0x02UL
  #define ADC16_CLP4_CLP42_MASK         0x04UL
  #define ADC16_CLP4_CLP43_MASK         0x08UL
  #define ADC16_CLP4_CLP44_MASK         0x10UL
  #define ADC16_CLP4_CLP45_MASK         0x20UL
  #define ADC16_CLP4_CLP46_MASK         0x40UL
  #define ADC16_CLP4_CLP47_MASK         0x80UL
  #define ADC16_CLP4_CLP48_MASK         0x0100UL
  #define ADC16_CLP4_CLP49_MASK         0x0200UL
  #define ADC16_CLP4_CLP4_MASK          0x03FFUL
  #define ADC16_CLP4_CLP4_BITNUM        0x00U
  #define ADC16_CLP4                    (*((volatile dword *)0x0000E59E))


  /*** ADC16_CLP3 - ADC plus-side general calibration value register; 0x0000E5A0 ***/
  union {
    dword Dword;
  } ADC16_CLP3_STR;

  #define ADC16_CLP3_CLP30_MASK         0x01UL
  #define ADC16_CLP3_CLP31_MASK         0x02UL
  #define ADC16_CLP3_CLP32_MASK         0x04UL
  #define ADC16_CLP3_CLP33_MASK         0x08UL
  #define ADC16_CLP3_CLP34_MASK         0x10UL
  #define ADC16_CLP3_CLP35_MASK         0x20UL
  #define ADC16_CLP3_CLP36_MASK         0x40UL
  #define ADC16_CLP3_CLP37_MASK         0x80UL
  #define ADC16_CLP3_CLP38_MASK         0x0100UL
  #define ADC16_CLP3_CLP3_MASK          0x01FFUL
  #define ADC16_CLP3_CLP3_BITNUM        0x00U
  #define ADC16_CLP3                    (*((volatile dword *)0x0000E5A0))


  /*** ADC16_CLP2 - ADC plus-side general calibration value register; 0x0000E5A2 ***/
  union {
    dword Dword;
  } ADC16_CLP2_STR;

  #define ADC16_CLP2_CLP20_MASK         0x01UL
  #define ADC16_CLP2_CLP21_MASK         0x02UL
  #define ADC16_CLP2_CLP22_MASK         0x04UL
  #define ADC16_CLP2_CLP23_MASK         0x08UL
  #define ADC16_CLP2_CLP24_MASK         0x10UL
  #define ADC16_CLP2_CLP25_MASK         0x20UL
  #define ADC16_CLP2_CLP26_MASK         0x40UL
  #define ADC16_CLP2_CLP27_MASK         0x80UL
  #define ADC16_CLP2_CLP2_MASK          0xFFUL
  #define ADC16_CLP2_CLP2_BITNUM        0x00U
  #define ADC16_CLP2                    (*((volatile dword *)0x0000E5A2))


  /*** ADC16_CLP1 - ADC plus-side general calibration value register; 0x0000E5A4 ***/
  union {
    dword Dword;
  } ADC16_CLP1_STR;

  #define ADC16_CLP1_CLP10_MASK         0x01UL
  #define ADC16_CLP1_CLP11_MASK         0x02UL
  #define ADC16_CLP1_CLP12_MASK         0x04UL
  #define ADC16_CLP1_CLP13_MASK         0x08UL
  #define ADC16_CLP1_CLP14_MASK         0x10UL
  #define ADC16_CLP1_CLP15_MASK         0x20UL
  #define ADC16_CLP1_CLP16_MASK         0x40UL
  #define ADC16_CLP1_CLP1_MASK          0x7FUL
  #define ADC16_CLP1_CLP1_BITNUM        0x00U
  #define ADC16_CLP1                    (*((volatile dword *)0x0000E5A4))


  /*** ADC16_CLP0 - ADC plus-side general calibration value register; 0x0000E5A6 ***/
  union {
    dword Dword;
  } ADC16_CLP0_STR;

  #define ADC16_CLP0_CLP00_MASK         0x01UL
  #define ADC16_CLP0_CLP01_MASK         0x02UL
  #define ADC16_CLP0_CLP02_MASK         0x04UL
  #define ADC16_CLP0_CLP03_MASK         0x08UL
  #define ADC16_CLP0_CLP04_MASK         0x10UL
  #define ADC16_CLP0_CLP05_MASK         0x20UL
  #define ADC16_CLP0_CLP0_MASK          0x3FUL
  #define ADC16_CLP0_CLP0_BITNUM        0x00U
  #define ADC16_CLP0                    (*((volatile dword *)0x0000E5A6))


  dword Reserved2[1];                  /* Reserved (unused) registers */

  /*** ADC16_CLMD - ADC minus-side general calibration value register; 0x0000E5AA ***/
  union {
    dword Dword;
  } ADC16_CLMD_STR;

  #define ADC16_CLMD_CLMD0_MASK         0x01UL
  #define ADC16_CLMD_CLMD1_MASK         0x02UL
  #define ADC16_CLMD_CLMD2_MASK         0x04UL
  #define ADC16_CLMD_CLMD3_MASK         0x08UL
  #define ADC16_CLMD_CLMD4_MASK         0x10UL
  #define ADC16_CLMD_CLMD5_MASK         0x20UL
  #define ADC16_CLMD_CLMD_MASK          0x3FUL
  #define ADC16_CLMD_CLMD_BITNUM        0x00U
  #define ADC16_CLMD                    (*((volatile dword *)0x0000E5AA))


  /*** ADC16_CLMS - ADC minus-side general calibration value register; 0x0000E5AC ***/
  union {
    dword Dword;
  } ADC16_CLMS_STR;

  #define ADC16_CLMS_CLMS0_MASK         0x01UL
  #define ADC16_CLMS_CLMS1_MASK         0x02UL
  #define ADC16_CLMS_CLMS2_MASK         0x04UL
  #define ADC16_CLMS_CLMS3_MASK         0x08UL
  #define ADC16_CLMS_CLMS4_MASK         0x10UL
  #define ADC16_CLMS_CLMS5_MASK         0x20UL
  #define ADC16_CLMS_CLMS_MASK          0x3FUL
  #define ADC16_CLMS_CLMS_BITNUM        0x00U
  #define ADC16_CLMS                    (*((volatile dword *)0x0000E5AC))


  /*** ADC16_CLM4 - ADC minus-side general calibration value register; 0x0000E5AE ***/
  union {
    dword Dword;
  } ADC16_CLM4_STR;

  #define ADC16_CLM4_CLM40_MASK         0x01UL
  #define ADC16_CLM4_CLM41_MASK         0x02UL
  #define ADC16_CLM4_CLM42_MASK         0x04UL
  #define ADC16_CLM4_CLM43_MASK         0x08UL
  #define ADC16_CLM4_CLM44_MASK         0x10UL
  #define ADC16_CLM4_CLM45_MASK         0x20UL
  #define ADC16_CLM4_CLM46_MASK         0x40UL
  #define ADC16_CLM4_CLM47_MASK         0x80UL
  #define ADC16_CLM4_CLM48_MASK         0x0100UL
  #define ADC16_CLM4_CLM49_MASK         0x0200UL
  #define ADC16_CLM4_CLM4_MASK          0x03FFUL
  #define ADC16_CLM4_CLM4_BITNUM        0x00U
  #define ADC16_CLM4                    (*((volatile dword *)0x0000E5AE))


  /*** ADC16_CLM3 - ADC minus-side general calibration value register; 0x0000E5B0 ***/
  union {
    dword Dword;
  } ADC16_CLM3_STR;

  #define ADC16_CLM3_CLM30_MASK         0x01UL
  #define ADC16_CLM3_CLM31_MASK         0x02UL
  #define ADC16_CLM3_CLM32_MASK         0x04UL
  #define ADC16_CLM3_CLM33_MASK         0x08UL
  #define ADC16_CLM3_CLM34_MASK         0x10UL
  #define ADC16_CLM3_CLM35_MASK         0x20UL
  #define ADC16_CLM3_CLM36_MASK         0x40UL
  #define ADC16_CLM3_CLM37_MASK         0x80UL
  #define ADC16_CLM3_CLM38_MASK         0x0100UL
  #define ADC16_CLM3_CLM3_MASK          0x01FFUL
  #define ADC16_CLM3_CLM3_BITNUM        0x00U
  #define ADC16_CLM3                    (*((volatile dword *)0x0000E5B0))


  /*** ADC16_CLM2 - ADC minus-side general calibration value register; 0x0000E5B2 ***/
  union {
    dword Dword;
  } ADC16_CLM2_STR;

  #define ADC16_CLM2_CLM20_MASK         0x01UL
  #define ADC16_CLM2_CLM21_MASK         0x02UL
  #define ADC16_CLM2_CLM22_MASK         0x04UL
  #define ADC16_CLM2_CLM23_MASK         0x08UL
  #define ADC16_CLM2_CLM24_MASK         0x10UL
  #define ADC16_CLM2_CLM25_MASK         0x20UL
  #define ADC16_CLM2_CLM26_MASK         0x40UL
  #define ADC16_CLM2_CLM27_MASK         0x80UL
  #define ADC16_CLM2_CLM2_MASK          0xFFUL
  #define ADC16_CLM2_CLM2_BITNUM        0x00U
  #define ADC16_CLM2                    (*((volatile dword *)0x0000E5B2))


  /*** ADC16_CLM1 - ADC minus-side general calibration value register; 0x0000E5B4 ***/
  union {
    dword Dword;
  } ADC16_CLM1_STR;

  #define ADC16_CLM1_CLM10_MASK         0x01UL
  #define ADC16_CLM1_CLM11_MASK         0x02UL
  #define ADC16_CLM1_CLM12_MASK         0x04UL
  #define ADC16_CLM1_CLM13_MASK         0x08UL
  #define ADC16_CLM1_CLM14_MASK         0x10UL
  #define ADC16_CLM1_CLM15_MASK         0x20UL
  #define ADC16_CLM1_CLM16_MASK         0x40UL
  #define ADC16_CLM1_CLM1_MASK          0x7FUL
  #define ADC16_CLM1_CLM1_BITNUM        0x00U
  #define ADC16_CLM1                    (*((volatile dword *)0x0000E5B4))


  /*** ADC16_CLM0 - ADC minus-side general calibration value register; 0x0000E5B6 ***/
  union {
    dword Dword;
  } ADC16_CLM0_STR;

  #define ADC16_CLM0_CLM00_MASK         0x01UL
  #define ADC16_CLM0_CLM01_MASK         0x02UL
  #define ADC16_CLM0_CLM02_MASK         0x04UL
  #define ADC16_CLM0_CLM03_MASK         0x08UL
  #define ADC16_CLM0_CLM04_MASK         0x10UL
  #define ADC16_CLM0_CLM05_MASK         0x20UL
  #define ADC16_CLM0_CLM0_MASK          0x3FUL
  #define ADC16_CLM0_CLM0_BITNUM        0x00U
  #define ADC16_CLM0                    (*((volatile dword *)0x0000E5B6))


} ADC16_PRPH;
/******************************************
*** Peripheral PWMA
*******************************************/
typedef volatile struct {
  /*** PWMA_SM0CNT - Counter Register; 0x0000E600 ***/
  union {
    word Word;
  } PWMA_SM0CNT_STR;

  #define PWMA_SM0CNT                   (*((volatile word *)0x0000E600))


  /*** PWMA_SM0INIT - Initial Count Register; 0x0000E601 ***/
  union {
    word Word;
  } PWMA_SM0INIT_STR;

  #define PWMA_SM0INIT                  (*((volatile word *)0x0000E601))


  /*** PWMA_SM0CTRL2 - Control 2 Register; 0x0000E602 ***/
  union {
    word Word;
  } PWMA_SM0CTRL2_STR;

  #define PWMA_SM0CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMA_SM0CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMA_SM0CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMA_SM0CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMA_SM0CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMA_SM0CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMA_SM0CTRL2_FORCE_MASK      0x40U
  #define PWMA_SM0CTRL2_FRCEN_MASK      0x80U
  #define PWMA_SM0CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMA_SM0CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMA_SM0CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMA_SM0CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMA_SM0CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMA_SM0CTRL2_INDEP_MASK      0x2000U
  #define PWMA_SM0CTRL2_WAITEN_MASK     0x4000U
  #define PWMA_SM0CTRL2_DBGEN_MASK      0x8000U
  #define PWMA_SM0CTRL2_CLK_SEL_MASK    0x03U
  #define PWMA_SM0CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMA_SM0CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMA_SM0CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMA_SM0CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMA_SM0CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMA_SM0CTRL2                 (*((volatile word *)0x0000E602))


  /*** PWMA_SM0CTRL - Control Register; 0x0000E603 ***/
  union {
    word Word;
  } PWMA_SM0CTRL_STR;

  #define PWMA_SM0CTRL_DBLEN_MASK       0x01U
  #define PWMA_SM0CTRL_DBLX_MASK        0x02U
  #define PWMA_SM0CTRL_LDMOD_MASK       0x04U
  #define PWMA_SM0CTRL_PRSC0_MASK       0x10U
  #define PWMA_SM0CTRL_PRSC1_MASK       0x20U
  #define PWMA_SM0CTRL_PRSC2_MASK       0x40U
  #define PWMA_SM0CTRL_DT0_MASK         0x0100U
  #define PWMA_SM0CTRL_DT1_MASK         0x0200U
  #define PWMA_SM0CTRL_FULL_MASK        0x0400U
  #define PWMA_SM0CTRL_HALF_MASK        0x0800U
  #define PWMA_SM0CTRL_LDFQ0_MASK       0x1000U
  #define PWMA_SM0CTRL_LDFQ1_MASK       0x2000U
  #define PWMA_SM0CTRL_LDFQ2_MASK       0x4000U
  #define PWMA_SM0CTRL_LDFQ3_MASK       0x8000U
  #define PWMA_SM0CTRL_PRSC_MASK        0x70U
  #define PWMA_SM0CTRL_PRSC_BITNUM      0x04U
  #define PWMA_SM0CTRL_DT_MASK          0x0300U
  #define PWMA_SM0CTRL_DT_BITNUM        0x08U
  #define PWMA_SM0CTRL_LDFQ_MASK        0xF000U
  #define PWMA_SM0CTRL_LDFQ_BITNUM      0x0CU
  #define PWMA_SM0CTRL                  (*((volatile word *)0x0000E603))


  word Reserved0[1];                   /* Reserved (unused) registers */

  /*** PWMA_SM0VAL0 - Value Register 0; 0x0000E605 ***/
  union {
    word Word;
  } PWMA_SM0VAL0_STR;

  #define PWMA_SM0VAL0                  (*((volatile word *)0x0000E605))


  /*** PWMA_SM0FRACVAL1 - Fractional Value Register 1; 0x0000E606 ***/
  union {
    word Word;
  } PWMA_SM0FRACVAL1_STR;

  #define PWMA_SM0FRACVAL1_FRACVAL10_MASK 0x0800U
  #define PWMA_SM0FRACVAL1_FRACVAL11_MASK 0x1000U
  #define PWMA_SM0FRACVAL1_FRACVAL12_MASK 0x2000U
  #define PWMA_SM0FRACVAL1_FRACVAL13_MASK 0x4000U
  #define PWMA_SM0FRACVAL1_FRACVAL14_MASK 0x8000U
  #define PWMA_SM0FRACVAL1_FRACVAL1_MASK 0xF800U
  #define PWMA_SM0FRACVAL1_FRACVAL1_BITNUM 0x0BU
  #define PWMA_SM0FRACVAL1              (*((volatile word *)0x0000E606))


  /*** PWMA_SM0VAL1 - Value Register 1; 0x0000E607 ***/
  union {
    word Word;
  } PWMA_SM0VAL1_STR;

  #define PWMA_SM0VAL1                  (*((volatile word *)0x0000E607))


  /*** PWMA_SM0FRACVAL2 - Fractional Value Register 2; 0x0000E608 ***/
  union {
    word Word;
  } PWMA_SM0FRACVAL2_STR;

  #define PWMA_SM0FRACVAL2_FRACVAL20_MASK 0x0800U
  #define PWMA_SM0FRACVAL2_FRACVAL21_MASK 0x1000U
  #define PWMA_SM0FRACVAL2_FRACVAL22_MASK 0x2000U
  #define PWMA_SM0FRACVAL2_FRACVAL23_MASK 0x4000U
  #define PWMA_SM0FRACVAL2_FRACVAL24_MASK 0x8000U
  #define PWMA_SM0FRACVAL2_FRACVAL2_MASK 0xF800U
  #define PWMA_SM0FRACVAL2_FRACVAL2_BITNUM 0x0BU
  #define PWMA_SM0FRACVAL2              (*((volatile word *)0x0000E608))


  /*** PWMA_SM0VAL2 - Value Register 2; 0x0000E609 ***/
  union {
    word Word;
  } PWMA_SM0VAL2_STR;

  #define PWMA_SM0VAL2                  (*((volatile word *)0x0000E609))


  /*** PWMA_SM0FRACVAL3 - Fractional Value Register 3; 0x0000E60A ***/
  union {
    word Word;
  } PWMA_SM0FRACVAL3_STR;

  #define PWMA_SM0FRACVAL3_FRACVAL30_MASK 0x0800U
  #define PWMA_SM0FRACVAL3_FRACVAL31_MASK 0x1000U
  #define PWMA_SM0FRACVAL3_FRACVAL32_MASK 0x2000U
  #define PWMA_SM0FRACVAL3_FRACVAL33_MASK 0x4000U
  #define PWMA_SM0FRACVAL3_FRACVAL34_MASK 0x8000U
  #define PWMA_SM0FRACVAL3_FRACVAL3_MASK 0xF800U
  #define PWMA_SM0FRACVAL3_FRACVAL3_BITNUM 0x0BU
  #define PWMA_SM0FRACVAL3              (*((volatile word *)0x0000E60A))


  /*** PWMA_SM0VAL3 - Value Register 3; 0x0000E60B ***/
  union {
    word Word;
  } PWMA_SM0VAL3_STR;

  #define PWMA_SM0VAL3                  (*((volatile word *)0x0000E60B))


  /*** PWMA_SM0FRACVAL4 - Fractional Value Register 4; 0x0000E60C ***/
  union {
    word Word;
  } PWMA_SM0FRACVAL4_STR;

  #define PWMA_SM0FRACVAL4_FRACVAL40_MASK 0x0800U
  #define PWMA_SM0FRACVAL4_FRACVAL41_MASK 0x1000U
  #define PWMA_SM0FRACVAL4_FRACVAL42_MASK 0x2000U
  #define PWMA_SM0FRACVAL4_FRACVAL43_MASK 0x4000U
  #define PWMA_SM0FRACVAL4_FRACVAL44_MASK 0x8000U
  #define PWMA_SM0FRACVAL4_FRACVAL4_MASK 0xF800U
  #define PWMA_SM0FRACVAL4_FRACVAL4_BITNUM 0x0BU
  #define PWMA_SM0FRACVAL4              (*((volatile word *)0x0000E60C))


  /*** PWMA_SM0VAL4 - Value Register 4; 0x0000E60D ***/
  union {
    word Word;
  } PWMA_SM0VAL4_STR;

  #define PWMA_SM0VAL4                  (*((volatile word *)0x0000E60D))


  /*** PWMA_SM0FRACVAL5 - Fractional Value Register 5; 0x0000E60E ***/
  union {
    word Word;
  } PWMA_SM0FRACVAL5_STR;

  #define PWMA_SM0FRACVAL5_FRACVAL50_MASK 0x0800U
  #define PWMA_SM0FRACVAL5_FRACVAL51_MASK 0x1000U
  #define PWMA_SM0FRACVAL5_FRACVAL52_MASK 0x2000U
  #define PWMA_SM0FRACVAL5_FRACVAL53_MASK 0x4000U
  #define PWMA_SM0FRACVAL5_FRACVAL54_MASK 0x8000U
  #define PWMA_SM0FRACVAL5_FRACVAL5_MASK 0xF800U
  #define PWMA_SM0FRACVAL5_FRACVAL5_BITNUM 0x0BU
  #define PWMA_SM0FRACVAL5              (*((volatile word *)0x0000E60E))


  /*** PWMA_SM0VAL5 - Value Register 5; 0x0000E60F ***/
  union {
    word Word;
  } PWMA_SM0VAL5_STR;

  #define PWMA_SM0VAL5                  (*((volatile word *)0x0000E60F))


  /*** PWMA_SM0FRCTRL - Fractional Control Register; 0x0000E610 ***/
  union {
    word Word;
  } PWMA_SM0FRCTRL_STR;

  #define PWMA_SM0FRCTRL_FRAC1_EN_MASK  0x02U
  #define PWMA_SM0FRCTRL_FRAC23_EN_MASK 0x04U
  #define PWMA_SM0FRCTRL_FRAC45_EN_MASK 0x10U
  #define PWMA_SM0FRCTRL_FRAC_PU_MASK   0x0100U
  #define PWMA_SM0FRCTRL_TEST_MASK      0x8000U
  #define PWMA_SM0FRCTRL                (*((volatile word *)0x0000E610))


  /*** PWMA_SM0OCTRL - Output Control Register; 0x0000E611 ***/
  union {
    word Word;
  } PWMA_SM0OCTRL_STR;

  #define PWMA_SM0OCTRL_PWMXFS0_MASK    0x01U
  #define PWMA_SM0OCTRL_PWMXFS1_MASK    0x02U
  #define PWMA_SM0OCTRL_PWMBFS0_MASK    0x04U
  #define PWMA_SM0OCTRL_PWMBFS1_MASK    0x08U
  #define PWMA_SM0OCTRL_PWMAFS0_MASK    0x10U
  #define PWMA_SM0OCTRL_PWMAFS1_MASK    0x20U
  #define PWMA_SM0OCTRL_POLX_MASK       0x0100U
  #define PWMA_SM0OCTRL_POLB_MASK       0x0200U
  #define PWMA_SM0OCTRL_POLA_MASK       0x0400U
  #define PWMA_SM0OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMA_SM0OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMA_SM0OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMA_SM0OCTRL_PWMXFS_MASK     0x03U
  #define PWMA_SM0OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMA_SM0OCTRL_PWMBFS_MASK     0x0CU
  #define PWMA_SM0OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMA_SM0OCTRL_PWMAFS_MASK     0x30U
  #define PWMA_SM0OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMA_SM0OCTRL                 (*((volatile word *)0x0000E611))


  /*** PWMA_SM0STS - Status Register; 0x0000E612 ***/
  union {
    word Word;
  } PWMA_SM0STS_STR;

  #define PWMA_SM0STS_CMPF0_MASK        0x01U
  #define PWMA_SM0STS_CMPF1_MASK        0x02U
  #define PWMA_SM0STS_CMPF2_MASK        0x04U
  #define PWMA_SM0STS_CMPF3_MASK        0x08U
  #define PWMA_SM0STS_CMPF4_MASK        0x10U
  #define PWMA_SM0STS_CMPF5_MASK        0x20U
  #define PWMA_SM0STS_CFX0_MASK         0x40U
  #define PWMA_SM0STS_CFX1_MASK         0x80U
  #define PWMA_SM0STS_CFB0_MASK         0x0100U
  #define PWMA_SM0STS_CFB1_MASK         0x0200U
  #define PWMA_SM0STS_CFA0_MASK         0x0400U
  #define PWMA_SM0STS_CFA1_MASK         0x0800U
  #define PWMA_SM0STS_RF_MASK           0x1000U
  #define PWMA_SM0STS_REF_MASK          0x2000U
  #define PWMA_SM0STS_RUF_MASK          0x4000U
  #define PWMA_SM0STS_CMPF_MASK         0x3FU
  #define PWMA_SM0STS_CMPF_BITNUM       0x00U
  #define PWMA_SM0STS                   (*((volatile word *)0x0000E612))


  /*** PWMA_SM0INTEN - Interrupt Enable Register; 0x0000E613 ***/
  union {
    word Word;
  } PWMA_SM0INTEN_STR;

  #define PWMA_SM0INTEN_CMPIE0_MASK     0x01U
  #define PWMA_SM0INTEN_CMPIE1_MASK     0x02U
  #define PWMA_SM0INTEN_CMPIE2_MASK     0x04U
  #define PWMA_SM0INTEN_CMPIE3_MASK     0x08U
  #define PWMA_SM0INTEN_CMPIE4_MASK     0x10U
  #define PWMA_SM0INTEN_CMPIE5_MASK     0x20U
  #define PWMA_SM0INTEN_CX0IE_MASK      0x40U
  #define PWMA_SM0INTEN_CX1IE_MASK      0x80U
  #define PWMA_SM0INTEN_CB0IE_MASK      0x0100U
  #define PWMA_SM0INTEN_CB1IE_MASK      0x0200U
  #define PWMA_SM0INTEN_CA0IE_MASK      0x0400U
  #define PWMA_SM0INTEN_CA1IE_MASK      0x0800U
  #define PWMA_SM0INTEN_RIE_MASK        0x1000U
  #define PWMA_SM0INTEN_REIE_MASK       0x2000U
  #define PWMA_SM0INTEN_CMPIE_MASK      0x3FU
  #define PWMA_SM0INTEN_CMPIE_BITNUM    0x00U
  #define PWMA_SM0INTEN                 (*((volatile word *)0x0000E613))


  /*** PWMA_SM0DMAEN - DMA Enable Register; 0x0000E614 ***/
  union {
    word Word;
  } PWMA_SM0DMAEN_STR;

  #define PWMA_SM0DMAEN_CX0DE_MASK      0x01U
  #define PWMA_SM0DMAEN_CX1DE_MASK      0x02U
  #define PWMA_SM0DMAEN_CB0DE_MASK      0x04U
  #define PWMA_SM0DMAEN_CB1DE_MASK      0x08U
  #define PWMA_SM0DMAEN_CA0DE_MASK      0x10U
  #define PWMA_SM0DMAEN_CA1DE_MASK      0x20U
  #define PWMA_SM0DMAEN_CAPTDE0_MASK    0x40U
  #define PWMA_SM0DMAEN_CAPTDE1_MASK    0x80U
  #define PWMA_SM0DMAEN_FAND_MASK       0x0100U
  #define PWMA_SM0DMAEN_VALDE_MASK      0x0200U
  #define PWMA_SM0DMAEN_CAPTDE_MASK     0xC0U
  #define PWMA_SM0DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMA_SM0DMAEN                 (*((volatile word *)0x0000E614))


  /*** PWMA_SM0TCTRL - Output Trigger Control Register; 0x0000E615 ***/
  union {
    word Word;
  } PWMA_SM0TCTRL_STR;

  #define PWMA_SM0TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMA_SM0TCTRL_PWBOT1_MASK     0x4000U
  #define PWMA_SM0TCTRL_PWAOT0_MASK     0x8000U
  #define PWMA_SM0TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMA_SM0TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMA_SM0TCTRL                 (*((volatile word *)0x0000E615))


  /*** PWMA_SM0DISMAP0 - Fault Disable Mapping Register 0; 0x0000E616 ***/
  union {
    word Word;
  } PWMA_SM0DISMAP0_STR;

  #define PWMA_SM0DISMAP0_DIS0A0_MASK   0x01U
  #define PWMA_SM0DISMAP0_DIS0A1_MASK   0x02U
  #define PWMA_SM0DISMAP0_DIS0A2_MASK   0x04U
  #define PWMA_SM0DISMAP0_DIS0A3_MASK   0x08U
  #define PWMA_SM0DISMAP0_DIS0B0_MASK   0x10U
  #define PWMA_SM0DISMAP0_DIS0B1_MASK   0x20U
  #define PWMA_SM0DISMAP0_DIS0B2_MASK   0x40U
  #define PWMA_SM0DISMAP0_DIS0B3_MASK   0x80U
  #define PWMA_SM0DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMA_SM0DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMA_SM0DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMA_SM0DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMA_SM0DISMAP0_DIS0A_MASK    0x0FU
  #define PWMA_SM0DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMA_SM0DISMAP0_DIS0B_MASK    0xF0U
  #define PWMA_SM0DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMA_SM0DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMA_SM0DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMA_SM0DISMAP0               (*((volatile word *)0x0000E616))


  /*** PWMA_SM0DISMAP1 - Fault Disable Mapping Register 1; 0x0000E617 ***/
  union {
    word Word;
  } PWMA_SM0DISMAP1_STR;

  #define PWMA_SM0DISMAP1_DIS1A0_MASK   0x01U
  #define PWMA_SM0DISMAP1_DIS1A1_MASK   0x02U
  #define PWMA_SM0DISMAP1_DIS1A2_MASK   0x04U
  #define PWMA_SM0DISMAP1_DIS1A3_MASK   0x08U
  #define PWMA_SM0DISMAP1_DIS1B0_MASK   0x10U
  #define PWMA_SM0DISMAP1_DIS1B1_MASK   0x20U
  #define PWMA_SM0DISMAP1_DIS1B2_MASK   0x40U
  #define PWMA_SM0DISMAP1_DIS1B3_MASK   0x80U
  #define PWMA_SM0DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMA_SM0DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMA_SM0DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMA_SM0DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMA_SM0DISMAP1_DIS1A_MASK    0x0FU
  #define PWMA_SM0DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMA_SM0DISMAP1_DIS1B_MASK    0xF0U
  #define PWMA_SM0DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMA_SM0DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMA_SM0DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMA_SM0DISMAP1               (*((volatile word *)0x0000E617))


  /*** PWMA_SM0DTCNT0 - Deadtime Count Register 0; 0x0000E618 ***/
  union {
    word Word;
  } PWMA_SM0DTCNT0_STR;

  #define PWMA_SM0DTCNT0_DTCNT00_MASK   0x01U
  #define PWMA_SM0DTCNT0_DTCNT01_MASK   0x02U
  #define PWMA_SM0DTCNT0_DTCNT02_MASK   0x04U
  #define PWMA_SM0DTCNT0_DTCNT03_MASK   0x08U
  #define PWMA_SM0DTCNT0_DTCNT04_MASK   0x10U
  #define PWMA_SM0DTCNT0_DTCNT05_MASK   0x20U
  #define PWMA_SM0DTCNT0_DTCNT06_MASK   0x40U
  #define PWMA_SM0DTCNT0_DTCNT07_MASK   0x80U
  #define PWMA_SM0DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMA_SM0DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMA_SM0DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMA_SM0DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMA_SM0DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMA_SM0DTCNT0                (*((volatile word *)0x0000E618))


  /*** PWMA_SM0DTCNT1 - Deadtime Count Register 1; 0x0000E619 ***/
  union {
    word Word;
  } PWMA_SM0DTCNT1_STR;

  #define PWMA_SM0DTCNT1_DTCNT10_MASK   0x01U
  #define PWMA_SM0DTCNT1_DTCNT11_MASK   0x02U
  #define PWMA_SM0DTCNT1_DTCNT12_MASK   0x04U
  #define PWMA_SM0DTCNT1_DTCNT13_MASK   0x08U
  #define PWMA_SM0DTCNT1_DTCNT14_MASK   0x10U
  #define PWMA_SM0DTCNT1_DTCNT15_MASK   0x20U
  #define PWMA_SM0DTCNT1_DTCNT16_MASK   0x40U
  #define PWMA_SM0DTCNT1_DTCNT17_MASK   0x80U
  #define PWMA_SM0DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMA_SM0DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMA_SM0DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMA_SM0DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMA_SM0DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMA_SM0DTCNT1                (*((volatile word *)0x0000E619))


  /*** PWMA_SM0CAPTCTRLA - Capture Control A Register; 0x0000E61A ***/
  union {
    word Word;
  } PWMA_SM0CAPTCTRLA_STR;

  #define PWMA_SM0CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMA_SM0CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMA_SM0CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMA_SM0CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMA_SM0CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMA_SM0CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMA_SM0CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMA_SM0CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMA_SM0CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMA_SM0CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMA_SM0CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMA_SM0CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMA_SM0CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMA_SM0CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMA_SM0CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMA_SM0CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMA_SM0CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMA_SM0CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMA_SM0CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMA_SM0CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMA_SM0CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMA_SM0CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMA_SM0CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMA_SM0CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMA_SM0CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMA_SM0CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMA_SM0CAPTCTRLA             (*((volatile word *)0x0000E61A))


  /*** PWMA_SM0CAPTCOMPA - Capture Compare A Register; 0x0000E61B ***/
  union {
    word Word;
  } PWMA_SM0CAPTCOMPA_STR;

  #define PWMA_SM0CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMA_SM0CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMA_SM0CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMA_SM0CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMA_SM0CAPTCOMPA             (*((volatile word *)0x0000E61B))


  /*** PWMA_SM0CAPTCTRLB - Capture Control B Register; 0x0000E61C ***/
  union {
    word Word;
  } PWMA_SM0CAPTCTRLB_STR;

  #define PWMA_SM0CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMA_SM0CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMA_SM0CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMA_SM0CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMA_SM0CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMA_SM0CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMA_SM0CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMA_SM0CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMA_SM0CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMA_SM0CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMA_SM0CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMA_SM0CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMA_SM0CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMA_SM0CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMA_SM0CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMA_SM0CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMA_SM0CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMA_SM0CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMA_SM0CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMA_SM0CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMA_SM0CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMA_SM0CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMA_SM0CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMA_SM0CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMA_SM0CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMA_SM0CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMA_SM0CAPTCTRLB             (*((volatile word *)0x0000E61C))


  /*** PWMA_SM0CAPTCOMPB - Capture Compare B Register; 0x0000E61D ***/
  union {
    word Word;
  } PWMA_SM0CAPTCOMPB_STR;

  #define PWMA_SM0CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMA_SM0CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMA_SM0CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMA_SM0CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMA_SM0CAPTCOMPB             (*((volatile word *)0x0000E61D))


  /*** PWMA_SM0CAPTCTRLX - Capture Control X Register; 0x0000E61E ***/
  union {
    word Word;
  } PWMA_SM0CAPTCTRLX_STR;

  #define PWMA_SM0CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMA_SM0CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMA_SM0CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMA_SM0CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMA_SM0CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMA_SM0CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMA_SM0CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMA_SM0CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMA_SM0CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMA_SM0CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMA_SM0CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMA_SM0CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMA_SM0CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMA_SM0CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMA_SM0CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMA_SM0CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMA_SM0CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMA_SM0CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMA_SM0CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMA_SM0CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMA_SM0CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMA_SM0CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMA_SM0CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMA_SM0CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMA_SM0CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMA_SM0CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMA_SM0CAPTCTRLX             (*((volatile word *)0x0000E61E))


  /*** PWMA_SM0CAPTCOMPX - Capture Compare X Register; 0x0000E61F ***/
  union {
    word Word;
  } PWMA_SM0CAPTCOMPX_STR;

  #define PWMA_SM0CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMA_SM0CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMA_SM0CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMA_SM0CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMA_SM0CAPTCOMPX             (*((volatile word *)0x0000E61F))


  /*** PWMA_SM0CVAL0 - Capture Value 0 Register; 0x0000E620 ***/
  union {
    word Word;
  } PWMA_SM0CVAL0_STR;

  #define PWMA_SM0CVAL0                 (*((volatile word *)0x0000E620))


  /*** PWMA_SM0CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E621 ***/
  union {
    word Word;
  } PWMA_SM0CVAL0CYC_STR;

  #define PWMA_SM0CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMA_SM0CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMA_SM0CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMA_SM0CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMA_SM0CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMA_SM0CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL0CYC              (*((volatile word *)0x0000E621))


  /*** PWMA_SM0CVAL1 - Capture Value 1 Register; 0x0000E622 ***/
  union {
    word Word;
  } PWMA_SM0CVAL1_STR;

  #define PWMA_SM0CVAL1                 (*((volatile word *)0x0000E622))


  /*** PWMA_SM0CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E623 ***/
  union {
    word Word;
  } PWMA_SM0CVAL1CYC_STR;

  #define PWMA_SM0CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMA_SM0CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMA_SM0CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMA_SM0CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMA_SM0CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMA_SM0CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL1CYC              (*((volatile word *)0x0000E623))


  /*** PWMA_SM0CVAL2 - Capture Value 2 Register; 0x0000E624 ***/
  union {
    word Word;
  } PWMA_SM0CVAL2_STR;

  #define PWMA_SM0CVAL2                 (*((volatile word *)0x0000E624))


  /*** PWMA_SM0CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E625 ***/
  union {
    word Word;
  } PWMA_SM0CVAL2CYC_STR;

  #define PWMA_SM0CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMA_SM0CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMA_SM0CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMA_SM0CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMA_SM0CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMA_SM0CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL2CYC              (*((volatile word *)0x0000E625))


  /*** PWMA_SM0CVAL3 - Capture Value 3 Register; 0x0000E626 ***/
  union {
    word Word;
  } PWMA_SM0CVAL3_STR;

  #define PWMA_SM0CVAL3                 (*((volatile word *)0x0000E626))


  /*** PWMA_SM0CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E627 ***/
  union {
    word Word;
  } PWMA_SM0CVAL3CYC_STR;

  #define PWMA_SM0CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMA_SM0CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMA_SM0CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMA_SM0CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMA_SM0CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMA_SM0CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL3CYC              (*((volatile word *)0x0000E627))


  /*** PWMA_SM0CVAL4 - Capture Value 4 Register; 0x0000E628 ***/
  union {
    word Word;
  } PWMA_SM0CVAL4_STR;

  #define PWMA_SM0CVAL4                 (*((volatile word *)0x0000E628))


  /*** PWMA_SM0CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E629 ***/
  union {
    word Word;
  } PWMA_SM0CVAL4CYC_STR;

  #define PWMA_SM0CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMA_SM0CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMA_SM0CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMA_SM0CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMA_SM0CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMA_SM0CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL4CYC              (*((volatile word *)0x0000E629))


  /*** PWMA_SM0CVAL5 - Capture Value 5 Register; 0x0000E62A ***/
  union {
    word Word;
  } PWMA_SM0CVAL5_STR;

  #define PWMA_SM0CVAL5                 (*((volatile word *)0x0000E62A))


  /*** PWMA_SM0CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E62B ***/
  union {
    word Word;
  } PWMA_SM0CVAL5CYC_STR;

  #define PWMA_SM0CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMA_SM0CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMA_SM0CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMA_SM0CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMA_SM0CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMA_SM0CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMA_SM0CVAL5CYC              (*((volatile word *)0x0000E62B))


  word Reserved1[4];                   /* Reserved (unused) registers */

  /*** PWMA_SM1CNT - Counter Register; 0x0000E630 ***/
  union {
    word Word;
  } PWMA_SM1CNT_STR;

  #define PWMA_SM1CNT                   (*((volatile word *)0x0000E630))


  /*** PWMA_SM1INIT - Initial Count Register; 0x0000E631 ***/
  union {
    word Word;
  } PWMA_SM1INIT_STR;

  #define PWMA_SM1INIT                  (*((volatile word *)0x0000E631))


  /*** PWMA_SM1CTRL2 - Control 2 Register; 0x0000E632 ***/
  union {
    word Word;
  } PWMA_SM1CTRL2_STR;

  #define PWMA_SM1CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMA_SM1CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMA_SM1CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMA_SM1CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMA_SM1CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMA_SM1CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMA_SM1CTRL2_FORCE_MASK      0x40U
  #define PWMA_SM1CTRL2_FRCEN_MASK      0x80U
  #define PWMA_SM1CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMA_SM1CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMA_SM1CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMA_SM1CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMA_SM1CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMA_SM1CTRL2_INDEP_MASK      0x2000U
  #define PWMA_SM1CTRL2_WAITEN_MASK     0x4000U
  #define PWMA_SM1CTRL2_DBGEN_MASK      0x8000U
  #define PWMA_SM1CTRL2_CLK_SEL_MASK    0x03U
  #define PWMA_SM1CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMA_SM1CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMA_SM1CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMA_SM1CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMA_SM1CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMA_SM1CTRL2                 (*((volatile word *)0x0000E632))


  /*** PWMA_SM1CTRL - Control Register; 0x0000E633 ***/
  union {
    word Word;
  } PWMA_SM1CTRL_STR;

  #define PWMA_SM1CTRL_DBLEN_MASK       0x01U
  #define PWMA_SM1CTRL_DBLX_MASK        0x02U
  #define PWMA_SM1CTRL_LDMOD_MASK       0x04U
  #define PWMA_SM1CTRL_PRSC0_MASK       0x10U
  #define PWMA_SM1CTRL_PRSC1_MASK       0x20U
  #define PWMA_SM1CTRL_PRSC2_MASK       0x40U
  #define PWMA_SM1CTRL_DT0_MASK         0x0100U
  #define PWMA_SM1CTRL_DT1_MASK         0x0200U
  #define PWMA_SM1CTRL_FULL_MASK        0x0400U
  #define PWMA_SM1CTRL_HALF_MASK        0x0800U
  #define PWMA_SM1CTRL_LDFQ0_MASK       0x1000U
  #define PWMA_SM1CTRL_LDFQ1_MASK       0x2000U
  #define PWMA_SM1CTRL_LDFQ2_MASK       0x4000U
  #define PWMA_SM1CTRL_LDFQ3_MASK       0x8000U
  #define PWMA_SM1CTRL_PRSC_MASK        0x70U
  #define PWMA_SM1CTRL_PRSC_BITNUM      0x04U
  #define PWMA_SM1CTRL_DT_MASK          0x0300U
  #define PWMA_SM1CTRL_DT_BITNUM        0x08U
  #define PWMA_SM1CTRL_LDFQ_MASK        0xF000U
  #define PWMA_SM1CTRL_LDFQ_BITNUM      0x0CU
  #define PWMA_SM1CTRL                  (*((volatile word *)0x0000E633))


  word Reserved2[1];                   /* Reserved (unused) registers */

  /*** PWMA_SM1VAL0 - Value Register 0; 0x0000E635 ***/
  union {
    word Word;
  } PWMA_SM1VAL0_STR;

  #define PWMA_SM1VAL0                  (*((volatile word *)0x0000E635))


  /*** PWMA_SM1FRACVAL1 - Fractional Value Register 1; 0x0000E636 ***/
  union {
    word Word;
  } PWMA_SM1FRACVAL1_STR;

  #define PWMA_SM1FRACVAL1_FRACVAL10_MASK 0x0800U
  #define PWMA_SM1FRACVAL1_FRACVAL11_MASK 0x1000U
  #define PWMA_SM1FRACVAL1_FRACVAL12_MASK 0x2000U
  #define PWMA_SM1FRACVAL1_FRACVAL13_MASK 0x4000U
  #define PWMA_SM1FRACVAL1_FRACVAL14_MASK 0x8000U
  #define PWMA_SM1FRACVAL1_FRACVAL1_MASK 0xF800U
  #define PWMA_SM1FRACVAL1_FRACVAL1_BITNUM 0x0BU
  #define PWMA_SM1FRACVAL1              (*((volatile word *)0x0000E636))


  /*** PWMA_SM1VAL1 - Value Register 1; 0x0000E637 ***/
  union {
    word Word;
  } PWMA_SM1VAL1_STR;

  #define PWMA_SM1VAL1                  (*((volatile word *)0x0000E637))


  /*** PWMA_SM1FRACVAL2 - Fractional Value Register 2; 0x0000E638 ***/
  union {
    word Word;
  } PWMA_SM1FRACVAL2_STR;

  #define PWMA_SM1FRACVAL2_FRACVAL20_MASK 0x0800U
  #define PWMA_SM1FRACVAL2_FRACVAL21_MASK 0x1000U
  #define PWMA_SM1FRACVAL2_FRACVAL22_MASK 0x2000U
  #define PWMA_SM1FRACVAL2_FRACVAL23_MASK 0x4000U
  #define PWMA_SM1FRACVAL2_FRACVAL24_MASK 0x8000U
  #define PWMA_SM1FRACVAL2_FRACVAL2_MASK 0xF800U
  #define PWMA_SM1FRACVAL2_FRACVAL2_BITNUM 0x0BU
  #define PWMA_SM1FRACVAL2              (*((volatile word *)0x0000E638))


  /*** PWMA_SM1VAL2 - Value Register 2; 0x0000E639 ***/
  union {
    word Word;
  } PWMA_SM1VAL2_STR;

  #define PWMA_SM1VAL2                  (*((volatile word *)0x0000E639))


  /*** PWMA_SM1FRACVAL3 - Fractional Value Register 3; 0x0000E63A ***/
  union {
    word Word;
  } PWMA_SM1FRACVAL3_STR;

  #define PWMA_SM1FRACVAL3_FRACVAL30_MASK 0x0800U
  #define PWMA_SM1FRACVAL3_FRACVAL31_MASK 0x1000U
  #define PWMA_SM1FRACVAL3_FRACVAL32_MASK 0x2000U
  #define PWMA_SM1FRACVAL3_FRACVAL33_MASK 0x4000U
  #define PWMA_SM1FRACVAL3_FRACVAL34_MASK 0x8000U
  #define PWMA_SM1FRACVAL3_FRACVAL3_MASK 0xF800U
  #define PWMA_SM1FRACVAL3_FRACVAL3_BITNUM 0x0BU
  #define PWMA_SM1FRACVAL3              (*((volatile word *)0x0000E63A))


  /*** PWMA_SM1VAL3 - Value Register 3; 0x0000E63B ***/
  union {
    word Word;
  } PWMA_SM1VAL3_STR;

  #define PWMA_SM1VAL3                  (*((volatile word *)0x0000E63B))


  /*** PWMA_SM1FRACVAL4 - Fractional Value Register 4; 0x0000E63C ***/
  union {
    word Word;
  } PWMA_SM1FRACVAL4_STR;

  #define PWMA_SM1FRACVAL4_FRACVAL40_MASK 0x0800U
  #define PWMA_SM1FRACVAL4_FRACVAL41_MASK 0x1000U
  #define PWMA_SM1FRACVAL4_FRACVAL42_MASK 0x2000U
  #define PWMA_SM1FRACVAL4_FRACVAL43_MASK 0x4000U
  #define PWMA_SM1FRACVAL4_FRACVAL44_MASK 0x8000U
  #define PWMA_SM1FRACVAL4_FRACVAL4_MASK 0xF800U
  #define PWMA_SM1FRACVAL4_FRACVAL4_BITNUM 0x0BU
  #define PWMA_SM1FRACVAL4              (*((volatile word *)0x0000E63C))


  /*** PWMA_SM1VAL4 - Value Register 4; 0x0000E63D ***/
  union {
    word Word;
  } PWMA_SM1VAL4_STR;

  #define PWMA_SM1VAL4                  (*((volatile word *)0x0000E63D))


  /*** PWMA_SM1FRACVAL5 - Fractional Value Register 5; 0x0000E63E ***/
  union {
    word Word;
  } PWMA_SM1FRACVAL5_STR;

  #define PWMA_SM1FRACVAL5_FRACVAL50_MASK 0x0800U
  #define PWMA_SM1FRACVAL5_FRACVAL51_MASK 0x1000U
  #define PWMA_SM1FRACVAL5_FRACVAL52_MASK 0x2000U
  #define PWMA_SM1FRACVAL5_FRACVAL53_MASK 0x4000U
  #define PWMA_SM1FRACVAL5_FRACVAL54_MASK 0x8000U
  #define PWMA_SM1FRACVAL5_FRACVAL5_MASK 0xF800U
  #define PWMA_SM1FRACVAL5_FRACVAL5_BITNUM 0x0BU
  #define PWMA_SM1FRACVAL5              (*((volatile word *)0x0000E63E))


  /*** PWMA_SM1VAL5 - Value Register 5; 0x0000E63F ***/
  union {
    word Word;
  } PWMA_SM1VAL5_STR;

  #define PWMA_SM1VAL5                  (*((volatile word *)0x0000E63F))


  /*** PWMA_SM1FRCTRL - Fractional Control Register; 0x0000E640 ***/
  union {
    word Word;
  } PWMA_SM1FRCTRL_STR;

  #define PWMA_SM1FRCTRL_FRAC1_EN_MASK  0x02U
  #define PWMA_SM1FRCTRL_FRAC23_EN_MASK 0x04U
  #define PWMA_SM1FRCTRL_FRAC45_EN_MASK 0x10U
  #define PWMA_SM1FRCTRL_FRAC_PU_MASK   0x0100U
  #define PWMA_SM1FRCTRL_TEST_MASK      0x8000U
  #define PWMA_SM1FRCTRL                (*((volatile word *)0x0000E640))


  /*** PWMA_SM1OCTRL - Output Control Register; 0x0000E641 ***/
  union {
    word Word;
  } PWMA_SM1OCTRL_STR;

  #define PWMA_SM1OCTRL_PWMXFS0_MASK    0x01U
  #define PWMA_SM1OCTRL_PWMXFS1_MASK    0x02U
  #define PWMA_SM1OCTRL_PWMBFS0_MASK    0x04U
  #define PWMA_SM1OCTRL_PWMBFS1_MASK    0x08U
  #define PWMA_SM1OCTRL_PWMAFS0_MASK    0x10U
  #define PWMA_SM1OCTRL_PWMAFS1_MASK    0x20U
  #define PWMA_SM1OCTRL_POLX_MASK       0x0100U
  #define PWMA_SM1OCTRL_POLB_MASK       0x0200U
  #define PWMA_SM1OCTRL_POLA_MASK       0x0400U
  #define PWMA_SM1OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMA_SM1OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMA_SM1OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMA_SM1OCTRL_PWMXFS_MASK     0x03U
  #define PWMA_SM1OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMA_SM1OCTRL_PWMBFS_MASK     0x0CU
  #define PWMA_SM1OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMA_SM1OCTRL_PWMAFS_MASK     0x30U
  #define PWMA_SM1OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMA_SM1OCTRL                 (*((volatile word *)0x0000E641))


  /*** PWMA_SM1STS - Status Register; 0x0000E642 ***/
  union {
    word Word;
  } PWMA_SM1STS_STR;

  #define PWMA_SM1STS_CMPF0_MASK        0x01U
  #define PWMA_SM1STS_CMPF1_MASK        0x02U
  #define PWMA_SM1STS_CMPF2_MASK        0x04U
  #define PWMA_SM1STS_CMPF3_MASK        0x08U
  #define PWMA_SM1STS_CMPF4_MASK        0x10U
  #define PWMA_SM1STS_CMPF5_MASK        0x20U
  #define PWMA_SM1STS_CFX0_MASK         0x40U
  #define PWMA_SM1STS_CFX1_MASK         0x80U
  #define PWMA_SM1STS_CFB0_MASK         0x0100U
  #define PWMA_SM1STS_CFB1_MASK         0x0200U
  #define PWMA_SM1STS_CFA0_MASK         0x0400U
  #define PWMA_SM1STS_CFA1_MASK         0x0800U
  #define PWMA_SM1STS_RF_MASK           0x1000U
  #define PWMA_SM1STS_REF_MASK          0x2000U
  #define PWMA_SM1STS_RUF_MASK          0x4000U
  #define PWMA_SM1STS_CMPF_MASK         0x3FU
  #define PWMA_SM1STS_CMPF_BITNUM       0x00U
  #define PWMA_SM1STS                   (*((volatile word *)0x0000E642))


  /*** PWMA_SM1INTEN - Interrupt Enable Register; 0x0000E643 ***/
  union {
    word Word;
  } PWMA_SM1INTEN_STR;

  #define PWMA_SM1INTEN_CMPIE0_MASK     0x01U
  #define PWMA_SM1INTEN_CMPIE1_MASK     0x02U
  #define PWMA_SM1INTEN_CMPIE2_MASK     0x04U
  #define PWMA_SM1INTEN_CMPIE3_MASK     0x08U
  #define PWMA_SM1INTEN_CMPIE4_MASK     0x10U
  #define PWMA_SM1INTEN_CMPIE5_MASK     0x20U
  #define PWMA_SM1INTEN_CX0IE_MASK      0x40U
  #define PWMA_SM1INTEN_CX1IE_MASK      0x80U
  #define PWMA_SM1INTEN_CB0IE_MASK      0x0100U
  #define PWMA_SM1INTEN_CB1IE_MASK      0x0200U
  #define PWMA_SM1INTEN_CA0IE_MASK      0x0400U
  #define PWMA_SM1INTEN_CA1IE_MASK      0x0800U
  #define PWMA_SM1INTEN_RIE_MASK        0x1000U
  #define PWMA_SM1INTEN_REIE_MASK       0x2000U
  #define PWMA_SM1INTEN_CMPIE_MASK      0x3FU
  #define PWMA_SM1INTEN_CMPIE_BITNUM    0x00U
  #define PWMA_SM1INTEN                 (*((volatile word *)0x0000E643))


  /*** PWMA_SM1DMAEN - DMA Enable Register; 0x0000E644 ***/
  union {
    word Word;
  } PWMA_SM1DMAEN_STR;

  #define PWMA_SM1DMAEN_CX0DE_MASK      0x01U
  #define PWMA_SM1DMAEN_CX1DE_MASK      0x02U
  #define PWMA_SM1DMAEN_CB0DE_MASK      0x04U
  #define PWMA_SM1DMAEN_CB1DE_MASK      0x08U
  #define PWMA_SM1DMAEN_CA0DE_MASK      0x10U
  #define PWMA_SM1DMAEN_CA1DE_MASK      0x20U
  #define PWMA_SM1DMAEN_CAPTDE0_MASK    0x40U
  #define PWMA_SM1DMAEN_CAPTDE1_MASK    0x80U
  #define PWMA_SM1DMAEN_FAND_MASK       0x0100U
  #define PWMA_SM1DMAEN_VALDE_MASK      0x0200U
  #define PWMA_SM1DMAEN_CAPTDE_MASK     0xC0U
  #define PWMA_SM1DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMA_SM1DMAEN                 (*((volatile word *)0x0000E644))


  /*** PWMA_SM1TCTRL - Output Trigger Control Register; 0x0000E645 ***/
  union {
    word Word;
  } PWMA_SM1TCTRL_STR;

  #define PWMA_SM1TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMA_SM1TCTRL_PWBOT1_MASK     0x4000U
  #define PWMA_SM1TCTRL_PWAOT0_MASK     0x8000U
  #define PWMA_SM1TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMA_SM1TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMA_SM1TCTRL                 (*((volatile word *)0x0000E645))


  /*** PWMA_SM1DISMAP0 - Fault Disable Mapping Register 0; 0x0000E646 ***/
  union {
    word Word;
  } PWMA_SM1DISMAP0_STR;

  #define PWMA_SM1DISMAP0_DIS0A0_MASK   0x01U
  #define PWMA_SM1DISMAP0_DIS0A1_MASK   0x02U
  #define PWMA_SM1DISMAP0_DIS0A2_MASK   0x04U
  #define PWMA_SM1DISMAP0_DIS0A3_MASK   0x08U
  #define PWMA_SM1DISMAP0_DIS0B0_MASK   0x10U
  #define PWMA_SM1DISMAP0_DIS0B1_MASK   0x20U
  #define PWMA_SM1DISMAP0_DIS0B2_MASK   0x40U
  #define PWMA_SM1DISMAP0_DIS0B3_MASK   0x80U
  #define PWMA_SM1DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMA_SM1DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMA_SM1DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMA_SM1DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMA_SM1DISMAP0_DIS0A_MASK    0x0FU
  #define PWMA_SM1DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMA_SM1DISMAP0_DIS0B_MASK    0xF0U
  #define PWMA_SM1DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMA_SM1DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMA_SM1DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMA_SM1DISMAP0               (*((volatile word *)0x0000E646))


  /*** PWMA_SM1DISMAP1 - Fault Disable Mapping Register 1; 0x0000E647 ***/
  union {
    word Word;
  } PWMA_SM1DISMAP1_STR;

  #define PWMA_SM1DISMAP1_DIS1A0_MASK   0x01U
  #define PWMA_SM1DISMAP1_DIS1A1_MASK   0x02U
  #define PWMA_SM1DISMAP1_DIS1A2_MASK   0x04U
  #define PWMA_SM1DISMAP1_DIS1A3_MASK   0x08U
  #define PWMA_SM1DISMAP1_DIS1B0_MASK   0x10U
  #define PWMA_SM1DISMAP1_DIS1B1_MASK   0x20U
  #define PWMA_SM1DISMAP1_DIS1B2_MASK   0x40U
  #define PWMA_SM1DISMAP1_DIS1B3_MASK   0x80U
  #define PWMA_SM1DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMA_SM1DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMA_SM1DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMA_SM1DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMA_SM1DISMAP1_DIS1A_MASK    0x0FU
  #define PWMA_SM1DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMA_SM1DISMAP1_DIS1B_MASK    0xF0U
  #define PWMA_SM1DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMA_SM1DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMA_SM1DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMA_SM1DISMAP1               (*((volatile word *)0x0000E647))


  /*** PWMA_SM1DTCNT0 - Deadtime Count Register 0; 0x0000E648 ***/
  union {
    word Word;
  } PWMA_SM1DTCNT0_STR;

  #define PWMA_SM1DTCNT0_DTCNT00_MASK   0x01U
  #define PWMA_SM1DTCNT0_DTCNT01_MASK   0x02U
  #define PWMA_SM1DTCNT0_DTCNT02_MASK   0x04U
  #define PWMA_SM1DTCNT0_DTCNT03_MASK   0x08U
  #define PWMA_SM1DTCNT0_DTCNT04_MASK   0x10U
  #define PWMA_SM1DTCNT0_DTCNT05_MASK   0x20U
  #define PWMA_SM1DTCNT0_DTCNT06_MASK   0x40U
  #define PWMA_SM1DTCNT0_DTCNT07_MASK   0x80U
  #define PWMA_SM1DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMA_SM1DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMA_SM1DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMA_SM1DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMA_SM1DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMA_SM1DTCNT0                (*((volatile word *)0x0000E648))


  /*** PWMA_SM1DTCNT1 - Deadtime Count Register 1; 0x0000E649 ***/
  union {
    word Word;
  } PWMA_SM1DTCNT1_STR;

  #define PWMA_SM1DTCNT1_DTCNT10_MASK   0x01U
  #define PWMA_SM1DTCNT1_DTCNT11_MASK   0x02U
  #define PWMA_SM1DTCNT1_DTCNT12_MASK   0x04U
  #define PWMA_SM1DTCNT1_DTCNT13_MASK   0x08U
  #define PWMA_SM1DTCNT1_DTCNT14_MASK   0x10U
  #define PWMA_SM1DTCNT1_DTCNT15_MASK   0x20U
  #define PWMA_SM1DTCNT1_DTCNT16_MASK   0x40U
  #define PWMA_SM1DTCNT1_DTCNT17_MASK   0x80U
  #define PWMA_SM1DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMA_SM1DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMA_SM1DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMA_SM1DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMA_SM1DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMA_SM1DTCNT1                (*((volatile word *)0x0000E649))


  /*** PWMA_SM1CAPTCTRLA - Capture Control A Register; 0x0000E64A ***/
  union {
    word Word;
  } PWMA_SM1CAPTCTRLA_STR;

  #define PWMA_SM1CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMA_SM1CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMA_SM1CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMA_SM1CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMA_SM1CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMA_SM1CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMA_SM1CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMA_SM1CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMA_SM1CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMA_SM1CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMA_SM1CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMA_SM1CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMA_SM1CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMA_SM1CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMA_SM1CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMA_SM1CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMA_SM1CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMA_SM1CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMA_SM1CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMA_SM1CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMA_SM1CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMA_SM1CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMA_SM1CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMA_SM1CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMA_SM1CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMA_SM1CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMA_SM1CAPTCTRLA             (*((volatile word *)0x0000E64A))


  /*** PWMA_SM1CAPTCOMPA - Capture Compare A Register; 0x0000E64B ***/
  union {
    word Word;
  } PWMA_SM1CAPTCOMPA_STR;

  #define PWMA_SM1CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMA_SM1CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMA_SM1CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMA_SM1CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMA_SM1CAPTCOMPA             (*((volatile word *)0x0000E64B))


  /*** PWMA_SM1CAPTCTRLB - Capture Control B Register; 0x0000E64C ***/
  union {
    word Word;
  } PWMA_SM1CAPTCTRLB_STR;

  #define PWMA_SM1CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMA_SM1CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMA_SM1CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMA_SM1CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMA_SM1CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMA_SM1CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMA_SM1CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMA_SM1CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMA_SM1CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMA_SM1CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMA_SM1CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMA_SM1CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMA_SM1CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMA_SM1CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMA_SM1CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMA_SM1CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMA_SM1CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMA_SM1CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMA_SM1CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMA_SM1CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMA_SM1CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMA_SM1CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMA_SM1CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMA_SM1CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMA_SM1CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMA_SM1CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMA_SM1CAPTCTRLB             (*((volatile word *)0x0000E64C))


  /*** PWMA_SM1CAPTCOMPB - Capture Compare B Register; 0x0000E64D ***/
  union {
    word Word;
  } PWMA_SM1CAPTCOMPB_STR;

  #define PWMA_SM1CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMA_SM1CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMA_SM1CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMA_SM1CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMA_SM1CAPTCOMPB             (*((volatile word *)0x0000E64D))


  /*** PWMA_SM1CAPTCTRLX - Capture Control X Register; 0x0000E64E ***/
  union {
    word Word;
  } PWMA_SM1CAPTCTRLX_STR;

  #define PWMA_SM1CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMA_SM1CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMA_SM1CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMA_SM1CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMA_SM1CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMA_SM1CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMA_SM1CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMA_SM1CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMA_SM1CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMA_SM1CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMA_SM1CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMA_SM1CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMA_SM1CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMA_SM1CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMA_SM1CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMA_SM1CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMA_SM1CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMA_SM1CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMA_SM1CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMA_SM1CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMA_SM1CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMA_SM1CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMA_SM1CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMA_SM1CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMA_SM1CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMA_SM1CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMA_SM1CAPTCTRLX             (*((volatile word *)0x0000E64E))


  /*** PWMA_SM1CAPTCOMPX - Capture Compare X Register; 0x0000E64F ***/
  union {
    word Word;
  } PWMA_SM1CAPTCOMPX_STR;

  #define PWMA_SM1CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMA_SM1CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMA_SM1CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMA_SM1CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMA_SM1CAPTCOMPX             (*((volatile word *)0x0000E64F))


  /*** PWMA_SM1CVAL0 - Capture Value 0 Register; 0x0000E650 ***/
  union {
    word Word;
  } PWMA_SM1CVAL0_STR;

  #define PWMA_SM1CVAL0                 (*((volatile word *)0x0000E650))


  /*** PWMA_SM1CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E651 ***/
  union {
    word Word;
  } PWMA_SM1CVAL0CYC_STR;

  #define PWMA_SM1CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMA_SM1CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMA_SM1CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMA_SM1CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMA_SM1CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMA_SM1CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL0CYC              (*((volatile word *)0x0000E651))


  /*** PWMA_SM1CVAL1 - Capture Value 1 Register; 0x0000E652 ***/
  union {
    word Word;
  } PWMA_SM1CVAL1_STR;

  #define PWMA_SM1CVAL1                 (*((volatile word *)0x0000E652))


  /*** PWMA_SM1CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E653 ***/
  union {
    word Word;
  } PWMA_SM1CVAL1CYC_STR;

  #define PWMA_SM1CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMA_SM1CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMA_SM1CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMA_SM1CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMA_SM1CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMA_SM1CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL1CYC              (*((volatile word *)0x0000E653))


  /*** PWMA_SM1CVAL2 - Capture Value 2 Register; 0x0000E654 ***/
  union {
    word Word;
  } PWMA_SM1CVAL2_STR;

  #define PWMA_SM1CVAL2                 (*((volatile word *)0x0000E654))


  /*** PWMA_SM1CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E655 ***/
  union {
    word Word;
  } PWMA_SM1CVAL2CYC_STR;

  #define PWMA_SM1CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMA_SM1CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMA_SM1CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMA_SM1CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMA_SM1CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMA_SM1CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL2CYC              (*((volatile word *)0x0000E655))


  /*** PWMA_SM1CVAL3 - Capture Value 3 Register; 0x0000E656 ***/
  union {
    word Word;
  } PWMA_SM1CVAL3_STR;

  #define PWMA_SM1CVAL3                 (*((volatile word *)0x0000E656))


  /*** PWMA_SM1CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E657 ***/
  union {
    word Word;
  } PWMA_SM1CVAL3CYC_STR;

  #define PWMA_SM1CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMA_SM1CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMA_SM1CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMA_SM1CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMA_SM1CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMA_SM1CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL3CYC              (*((volatile word *)0x0000E657))


  /*** PWMA_SM1CVAL4 - Capture Value 4 Register; 0x0000E658 ***/
  union {
    word Word;
  } PWMA_SM1CVAL4_STR;

  #define PWMA_SM1CVAL4                 (*((volatile word *)0x0000E658))


  /*** PWMA_SM1CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E659 ***/
  union {
    word Word;
  } PWMA_SM1CVAL4CYC_STR;

  #define PWMA_SM1CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMA_SM1CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMA_SM1CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMA_SM1CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMA_SM1CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMA_SM1CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL4CYC              (*((volatile word *)0x0000E659))


  /*** PWMA_SM1CVAL5 - Capture Value 5 Register; 0x0000E65A ***/
  union {
    word Word;
  } PWMA_SM1CVAL5_STR;

  #define PWMA_SM1CVAL5                 (*((volatile word *)0x0000E65A))


  /*** PWMA_SM1CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E65B ***/
  union {
    word Word;
  } PWMA_SM1CVAL5CYC_STR;

  #define PWMA_SM1CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMA_SM1CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMA_SM1CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMA_SM1CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMA_SM1CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMA_SM1CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMA_SM1CVAL5CYC              (*((volatile word *)0x0000E65B))


  word Reserved3[4];                   /* Reserved (unused) registers */

  /*** PWMA_SM2CNT - Counter Register; 0x0000E660 ***/
  union {
    word Word;
  } PWMA_SM2CNT_STR;

  #define PWMA_SM2CNT                   (*((volatile word *)0x0000E660))


  /*** PWMA_SM2INIT - Initial Count Register; 0x0000E661 ***/
  union {
    word Word;
  } PWMA_SM2INIT_STR;

  #define PWMA_SM2INIT                  (*((volatile word *)0x0000E661))


  /*** PWMA_SM2CTRL2 - Control 2 Register; 0x0000E662 ***/
  union {
    word Word;
  } PWMA_SM2CTRL2_STR;

  #define PWMA_SM2CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMA_SM2CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMA_SM2CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMA_SM2CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMA_SM2CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMA_SM2CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMA_SM2CTRL2_FORCE_MASK      0x40U
  #define PWMA_SM2CTRL2_FRCEN_MASK      0x80U
  #define PWMA_SM2CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMA_SM2CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMA_SM2CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMA_SM2CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMA_SM2CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMA_SM2CTRL2_INDEP_MASK      0x2000U
  #define PWMA_SM2CTRL2_WAITEN_MASK     0x4000U
  #define PWMA_SM2CTRL2_DBGEN_MASK      0x8000U
  #define PWMA_SM2CTRL2_CLK_SEL_MASK    0x03U
  #define PWMA_SM2CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMA_SM2CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMA_SM2CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMA_SM2CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMA_SM2CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMA_SM2CTRL2                 (*((volatile word *)0x0000E662))


  /*** PWMA_SM2CTRL - Control Register; 0x0000E663 ***/
  union {
    word Word;
  } PWMA_SM2CTRL_STR;

  #define PWMA_SM2CTRL_DBLEN_MASK       0x01U
  #define PWMA_SM2CTRL_DBLX_MASK        0x02U
  #define PWMA_SM2CTRL_LDMOD_MASK       0x04U
  #define PWMA_SM2CTRL_PRSC0_MASK       0x10U
  #define PWMA_SM2CTRL_PRSC1_MASK       0x20U
  #define PWMA_SM2CTRL_PRSC2_MASK       0x40U
  #define PWMA_SM2CTRL_DT0_MASK         0x0100U
  #define PWMA_SM2CTRL_DT1_MASK         0x0200U
  #define PWMA_SM2CTRL_FULL_MASK        0x0400U
  #define PWMA_SM2CTRL_HALF_MASK        0x0800U
  #define PWMA_SM2CTRL_LDFQ0_MASK       0x1000U
  #define PWMA_SM2CTRL_LDFQ1_MASK       0x2000U
  #define PWMA_SM2CTRL_LDFQ2_MASK       0x4000U
  #define PWMA_SM2CTRL_LDFQ3_MASK       0x8000U
  #define PWMA_SM2CTRL_PRSC_MASK        0x70U
  #define PWMA_SM2CTRL_PRSC_BITNUM      0x04U
  #define PWMA_SM2CTRL_DT_MASK          0x0300U
  #define PWMA_SM2CTRL_DT_BITNUM        0x08U
  #define PWMA_SM2CTRL_LDFQ_MASK        0xF000U
  #define PWMA_SM2CTRL_LDFQ_BITNUM      0x0CU
  #define PWMA_SM2CTRL                  (*((volatile word *)0x0000E663))


  word Reserved4[1];                   /* Reserved (unused) registers */

  /*** PWMA_SM2VAL0 - Value Register 0; 0x0000E665 ***/
  union {
    word Word;
  } PWMA_SM2VAL0_STR;

  #define PWMA_SM2VAL0                  (*((volatile word *)0x0000E665))


  /*** PWMA_SM2FRACVAL1 - Fractional Value Register 1; 0x0000E666 ***/
  union {
    word Word;
  } PWMA_SM2FRACVAL1_STR;

  #define PWMA_SM2FRACVAL1_FRACVAL10_MASK 0x0800U
  #define PWMA_SM2FRACVAL1_FRACVAL11_MASK 0x1000U
  #define PWMA_SM2FRACVAL1_FRACVAL12_MASK 0x2000U
  #define PWMA_SM2FRACVAL1_FRACVAL13_MASK 0x4000U
  #define PWMA_SM2FRACVAL1_FRACVAL14_MASK 0x8000U
  #define PWMA_SM2FRACVAL1_FRACVAL1_MASK 0xF800U
  #define PWMA_SM2FRACVAL1_FRACVAL1_BITNUM 0x0BU
  #define PWMA_SM2FRACVAL1              (*((volatile word *)0x0000E666))


  /*** PWMA_SM2VAL1 - Value Register 1; 0x0000E667 ***/
  union {
    word Word;
  } PWMA_SM2VAL1_STR;

  #define PWMA_SM2VAL1                  (*((volatile word *)0x0000E667))


  /*** PWMA_SM2FRACVAL2 - Fractional Value Register 2; 0x0000E668 ***/
  union {
    word Word;
  } PWMA_SM2FRACVAL2_STR;

  #define PWMA_SM2FRACVAL2_FRACVAL20_MASK 0x0800U
  #define PWMA_SM2FRACVAL2_FRACVAL21_MASK 0x1000U
  #define PWMA_SM2FRACVAL2_FRACVAL22_MASK 0x2000U
  #define PWMA_SM2FRACVAL2_FRACVAL23_MASK 0x4000U
  #define PWMA_SM2FRACVAL2_FRACVAL24_MASK 0x8000U
  #define PWMA_SM2FRACVAL2_FRACVAL2_MASK 0xF800U
  #define PWMA_SM2FRACVAL2_FRACVAL2_BITNUM 0x0BU
  #define PWMA_SM2FRACVAL2              (*((volatile word *)0x0000E668))


  /*** PWMA_SM2VAL2 - Value Register 2; 0x0000E669 ***/
  union {
    word Word;
  } PWMA_SM2VAL2_STR;

  #define PWMA_SM2VAL2                  (*((volatile word *)0x0000E669))


  /*** PWMA_SM2FRACVAL3 - Fractional Value Register 3; 0x0000E66A ***/
  union {
    word Word;
  } PWMA_SM2FRACVAL3_STR;

  #define PWMA_SM2FRACVAL3_FRACVAL30_MASK 0x0800U
  #define PWMA_SM2FRACVAL3_FRACVAL31_MASK 0x1000U
  #define PWMA_SM2FRACVAL3_FRACVAL32_MASK 0x2000U
  #define PWMA_SM2FRACVAL3_FRACVAL33_MASK 0x4000U
  #define PWMA_SM2FRACVAL3_FRACVAL34_MASK 0x8000U
  #define PWMA_SM2FRACVAL3_FRACVAL3_MASK 0xF800U
  #define PWMA_SM2FRACVAL3_FRACVAL3_BITNUM 0x0BU
  #define PWMA_SM2FRACVAL3              (*((volatile word *)0x0000E66A))


  /*** PWMA_SM2VAL3 - Value Register 3; 0x0000E66B ***/
  union {
    word Word;
  } PWMA_SM2VAL3_STR;

  #define PWMA_SM2VAL3                  (*((volatile word *)0x0000E66B))


  /*** PWMA_SM2FRACVAL4 - Fractional Value Register 4; 0x0000E66C ***/
  union {
    word Word;
  } PWMA_SM2FRACVAL4_STR;

  #define PWMA_SM2FRACVAL4_FRACVAL40_MASK 0x0800U
  #define PWMA_SM2FRACVAL4_FRACVAL41_MASK 0x1000U
  #define PWMA_SM2FRACVAL4_FRACVAL42_MASK 0x2000U
  #define PWMA_SM2FRACVAL4_FRACVAL43_MASK 0x4000U
  #define PWMA_SM2FRACVAL4_FRACVAL44_MASK 0x8000U
  #define PWMA_SM2FRACVAL4_FRACVAL4_MASK 0xF800U
  #define PWMA_SM2FRACVAL4_FRACVAL4_BITNUM 0x0BU
  #define PWMA_SM2FRACVAL4              (*((volatile word *)0x0000E66C))


  /*** PWMA_SM2VAL4 - Value Register 4; 0x0000E66D ***/
  union {
    word Word;
  } PWMA_SM2VAL4_STR;

  #define PWMA_SM2VAL4                  (*((volatile word *)0x0000E66D))


  /*** PWMA_SM2FRACVAL5 - Fractional Value Register 5; 0x0000E66E ***/
  union {
    word Word;
  } PWMA_SM2FRACVAL5_STR;

  #define PWMA_SM2FRACVAL5_FRACVAL50_MASK 0x0800U
  #define PWMA_SM2FRACVAL5_FRACVAL51_MASK 0x1000U
  #define PWMA_SM2FRACVAL5_FRACVAL52_MASK 0x2000U
  #define PWMA_SM2FRACVAL5_FRACVAL53_MASK 0x4000U
  #define PWMA_SM2FRACVAL5_FRACVAL54_MASK 0x8000U
  #define PWMA_SM2FRACVAL5_FRACVAL5_MASK 0xF800U
  #define PWMA_SM2FRACVAL5_FRACVAL5_BITNUM 0x0BU
  #define PWMA_SM2FRACVAL5              (*((volatile word *)0x0000E66E))


  /*** PWMA_SM2VAL5 - Value Register 5; 0x0000E66F ***/
  union {
    word Word;
  } PWMA_SM2VAL5_STR;

  #define PWMA_SM2VAL5                  (*((volatile word *)0x0000E66F))


  /*** PWMA_SM2FRCTRL - Fractional Control Register; 0x0000E670 ***/
  union {
    word Word;
  } PWMA_SM2FRCTRL_STR;

  #define PWMA_SM2FRCTRL_FRAC1_EN_MASK  0x02U
  #define PWMA_SM2FRCTRL_FRAC23_EN_MASK 0x04U
  #define PWMA_SM2FRCTRL_FRAC45_EN_MASK 0x10U
  #define PWMA_SM2FRCTRL_FRAC_PU_MASK   0x0100U
  #define PWMA_SM2FRCTRL_TEST_MASK      0x8000U
  #define PWMA_SM2FRCTRL                (*((volatile word *)0x0000E670))


  /*** PWMA_SM2OCTRL - Output Control Register; 0x0000E671 ***/
  union {
    word Word;
  } PWMA_SM2OCTRL_STR;

  #define PWMA_SM2OCTRL_PWMXFS0_MASK    0x01U
  #define PWMA_SM2OCTRL_PWMXFS1_MASK    0x02U
  #define PWMA_SM2OCTRL_PWMBFS0_MASK    0x04U
  #define PWMA_SM2OCTRL_PWMBFS1_MASK    0x08U
  #define PWMA_SM2OCTRL_PWMAFS0_MASK    0x10U
  #define PWMA_SM2OCTRL_PWMAFS1_MASK    0x20U
  #define PWMA_SM2OCTRL_POLX_MASK       0x0100U
  #define PWMA_SM2OCTRL_POLB_MASK       0x0200U
  #define PWMA_SM2OCTRL_POLA_MASK       0x0400U
  #define PWMA_SM2OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMA_SM2OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMA_SM2OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMA_SM2OCTRL_PWMXFS_MASK     0x03U
  #define PWMA_SM2OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMA_SM2OCTRL_PWMBFS_MASK     0x0CU
  #define PWMA_SM2OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMA_SM2OCTRL_PWMAFS_MASK     0x30U
  #define PWMA_SM2OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMA_SM2OCTRL                 (*((volatile word *)0x0000E671))


  /*** PWMA_SM2STS - Status Register; 0x0000E672 ***/
  union {
    word Word;
  } PWMA_SM2STS_STR;

  #define PWMA_SM2STS_CMPF0_MASK        0x01U
  #define PWMA_SM2STS_CMPF1_MASK        0x02U
  #define PWMA_SM2STS_CMPF2_MASK        0x04U
  #define PWMA_SM2STS_CMPF3_MASK        0x08U
  #define PWMA_SM2STS_CMPF4_MASK        0x10U
  #define PWMA_SM2STS_CMPF5_MASK        0x20U
  #define PWMA_SM2STS_CFX0_MASK         0x40U
  #define PWMA_SM2STS_CFX1_MASK         0x80U
  #define PWMA_SM2STS_CFB0_MASK         0x0100U
  #define PWMA_SM2STS_CFB1_MASK         0x0200U
  #define PWMA_SM2STS_CFA0_MASK         0x0400U
  #define PWMA_SM2STS_CFA1_MASK         0x0800U
  #define PWMA_SM2STS_RF_MASK           0x1000U
  #define PWMA_SM2STS_REF_MASK          0x2000U
  #define PWMA_SM2STS_RUF_MASK          0x4000U
  #define PWMA_SM2STS_CMPF_MASK         0x3FU
  #define PWMA_SM2STS_CMPF_BITNUM       0x00U
  #define PWMA_SM2STS                   (*((volatile word *)0x0000E672))


  /*** PWMA_SM2INTEN - Interrupt Enable Register; 0x0000E673 ***/
  union {
    word Word;
  } PWMA_SM2INTEN_STR;

  #define PWMA_SM2INTEN_CMPIE0_MASK     0x01U
  #define PWMA_SM2INTEN_CMPIE1_MASK     0x02U
  #define PWMA_SM2INTEN_CMPIE2_MASK     0x04U
  #define PWMA_SM2INTEN_CMPIE3_MASK     0x08U
  #define PWMA_SM2INTEN_CMPIE4_MASK     0x10U
  #define PWMA_SM2INTEN_CMPIE5_MASK     0x20U
  #define PWMA_SM2INTEN_CX0IE_MASK      0x40U
  #define PWMA_SM2INTEN_CX1IE_MASK      0x80U
  #define PWMA_SM2INTEN_CB0IE_MASK      0x0100U
  #define PWMA_SM2INTEN_CB1IE_MASK      0x0200U
  #define PWMA_SM2INTEN_CA0IE_MASK      0x0400U
  #define PWMA_SM2INTEN_CA1IE_MASK      0x0800U
  #define PWMA_SM2INTEN_RIE_MASK        0x1000U
  #define PWMA_SM2INTEN_REIE_MASK       0x2000U
  #define PWMA_SM2INTEN_CMPIE_MASK      0x3FU
  #define PWMA_SM2INTEN_CMPIE_BITNUM    0x00U
  #define PWMA_SM2INTEN                 (*((volatile word *)0x0000E673))


  /*** PWMA_SM2DMAEN - DMA Enable Register; 0x0000E674 ***/
  union {
    word Word;
  } PWMA_SM2DMAEN_STR;

  #define PWMA_SM2DMAEN_CX0DE_MASK      0x01U
  #define PWMA_SM2DMAEN_CX1DE_MASK      0x02U
  #define PWMA_SM2DMAEN_CB0DE_MASK      0x04U
  #define PWMA_SM2DMAEN_CB1DE_MASK      0x08U
  #define PWMA_SM2DMAEN_CA0DE_MASK      0x10U
  #define PWMA_SM2DMAEN_CA1DE_MASK      0x20U
  #define PWMA_SM2DMAEN_CAPTDE0_MASK    0x40U
  #define PWMA_SM2DMAEN_CAPTDE1_MASK    0x80U
  #define PWMA_SM2DMAEN_FAND_MASK       0x0100U
  #define PWMA_SM2DMAEN_VALDE_MASK      0x0200U
  #define PWMA_SM2DMAEN_CAPTDE_MASK     0xC0U
  #define PWMA_SM2DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMA_SM2DMAEN                 (*((volatile word *)0x0000E674))


  /*** PWMA_SM2TCTRL - Output Trigger Control Register; 0x0000E675 ***/
  union {
    word Word;
  } PWMA_SM2TCTRL_STR;

  #define PWMA_SM2TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMA_SM2TCTRL_PWBOT1_MASK     0x4000U
  #define PWMA_SM2TCTRL_PWAOT0_MASK     0x8000U
  #define PWMA_SM2TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMA_SM2TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMA_SM2TCTRL                 (*((volatile word *)0x0000E675))


  /*** PWMA_SM2DISMAP0 - Fault Disable Mapping Register 0; 0x0000E676 ***/
  union {
    word Word;
  } PWMA_SM2DISMAP0_STR;

  #define PWMA_SM2DISMAP0_DIS0A0_MASK   0x01U
  #define PWMA_SM2DISMAP0_DIS0A1_MASK   0x02U
  #define PWMA_SM2DISMAP0_DIS0A2_MASK   0x04U
  #define PWMA_SM2DISMAP0_DIS0A3_MASK   0x08U
  #define PWMA_SM2DISMAP0_DIS0B0_MASK   0x10U
  #define PWMA_SM2DISMAP0_DIS0B1_MASK   0x20U
  #define PWMA_SM2DISMAP0_DIS0B2_MASK   0x40U
  #define PWMA_SM2DISMAP0_DIS0B3_MASK   0x80U
  #define PWMA_SM2DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMA_SM2DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMA_SM2DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMA_SM2DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMA_SM2DISMAP0_DIS0A_MASK    0x0FU
  #define PWMA_SM2DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMA_SM2DISMAP0_DIS0B_MASK    0xF0U
  #define PWMA_SM2DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMA_SM2DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMA_SM2DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMA_SM2DISMAP0               (*((volatile word *)0x0000E676))


  /*** PWMA_SM2DISMAP1 - Fault Disable Mapping Register 1; 0x0000E677 ***/
  union {
    word Word;
  } PWMA_SM2DISMAP1_STR;

  #define PWMA_SM2DISMAP1_DIS1A0_MASK   0x01U
  #define PWMA_SM2DISMAP1_DIS1A1_MASK   0x02U
  #define PWMA_SM2DISMAP1_DIS1A2_MASK   0x04U
  #define PWMA_SM2DISMAP1_DIS1A3_MASK   0x08U
  #define PWMA_SM2DISMAP1_DIS1B0_MASK   0x10U
  #define PWMA_SM2DISMAP1_DIS1B1_MASK   0x20U
  #define PWMA_SM2DISMAP1_DIS1B2_MASK   0x40U
  #define PWMA_SM2DISMAP1_DIS1B3_MASK   0x80U
  #define PWMA_SM2DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMA_SM2DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMA_SM2DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMA_SM2DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMA_SM2DISMAP1_DIS1A_MASK    0x0FU
  #define PWMA_SM2DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMA_SM2DISMAP1_DIS1B_MASK    0xF0U
  #define PWMA_SM2DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMA_SM2DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMA_SM2DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMA_SM2DISMAP1               (*((volatile word *)0x0000E677))


  /*** PWMA_SM2DTCNT0 - Deadtime Count Register 0; 0x0000E678 ***/
  union {
    word Word;
  } PWMA_SM2DTCNT0_STR;

  #define PWMA_SM2DTCNT0_DTCNT00_MASK   0x01U
  #define PWMA_SM2DTCNT0_DTCNT01_MASK   0x02U
  #define PWMA_SM2DTCNT0_DTCNT02_MASK   0x04U
  #define PWMA_SM2DTCNT0_DTCNT03_MASK   0x08U
  #define PWMA_SM2DTCNT0_DTCNT04_MASK   0x10U
  #define PWMA_SM2DTCNT0_DTCNT05_MASK   0x20U
  #define PWMA_SM2DTCNT0_DTCNT06_MASK   0x40U
  #define PWMA_SM2DTCNT0_DTCNT07_MASK   0x80U
  #define PWMA_SM2DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMA_SM2DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMA_SM2DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMA_SM2DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMA_SM2DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMA_SM2DTCNT0                (*((volatile word *)0x0000E678))


  /*** PWMA_SM2DTCNT1 - Deadtime Count Register 1; 0x0000E679 ***/
  union {
    word Word;
  } PWMA_SM2DTCNT1_STR;

  #define PWMA_SM2DTCNT1_DTCNT10_MASK   0x01U
  #define PWMA_SM2DTCNT1_DTCNT11_MASK   0x02U
  #define PWMA_SM2DTCNT1_DTCNT12_MASK   0x04U
  #define PWMA_SM2DTCNT1_DTCNT13_MASK   0x08U
  #define PWMA_SM2DTCNT1_DTCNT14_MASK   0x10U
  #define PWMA_SM2DTCNT1_DTCNT15_MASK   0x20U
  #define PWMA_SM2DTCNT1_DTCNT16_MASK   0x40U
  #define PWMA_SM2DTCNT1_DTCNT17_MASK   0x80U
  #define PWMA_SM2DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMA_SM2DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMA_SM2DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMA_SM2DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMA_SM2DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMA_SM2DTCNT1                (*((volatile word *)0x0000E679))


  /*** PWMA_SM2CAPTCTRLA - Capture Control A Register; 0x0000E67A ***/
  union {
    word Word;
  } PWMA_SM2CAPTCTRLA_STR;

  #define PWMA_SM2CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMA_SM2CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMA_SM2CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMA_SM2CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMA_SM2CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMA_SM2CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMA_SM2CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMA_SM2CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMA_SM2CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMA_SM2CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMA_SM2CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMA_SM2CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMA_SM2CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMA_SM2CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMA_SM2CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMA_SM2CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMA_SM2CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMA_SM2CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMA_SM2CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMA_SM2CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMA_SM2CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMA_SM2CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMA_SM2CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMA_SM2CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMA_SM2CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMA_SM2CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMA_SM2CAPTCTRLA             (*((volatile word *)0x0000E67A))


  /*** PWMA_SM2CAPTCOMPA - Capture Compare A Register; 0x0000E67B ***/
  union {
    word Word;
  } PWMA_SM2CAPTCOMPA_STR;

  #define PWMA_SM2CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMA_SM2CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMA_SM2CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMA_SM2CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMA_SM2CAPTCOMPA             (*((volatile word *)0x0000E67B))


  /*** PWMA_SM2CAPTCTRLB - Capture Control B Register; 0x0000E67C ***/
  union {
    word Word;
  } PWMA_SM2CAPTCTRLB_STR;

  #define PWMA_SM2CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMA_SM2CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMA_SM2CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMA_SM2CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMA_SM2CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMA_SM2CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMA_SM2CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMA_SM2CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMA_SM2CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMA_SM2CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMA_SM2CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMA_SM2CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMA_SM2CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMA_SM2CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMA_SM2CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMA_SM2CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMA_SM2CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMA_SM2CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMA_SM2CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMA_SM2CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMA_SM2CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMA_SM2CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMA_SM2CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMA_SM2CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMA_SM2CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMA_SM2CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMA_SM2CAPTCTRLB             (*((volatile word *)0x0000E67C))


  /*** PWMA_SM2CAPTCOMPB - Capture Compare B Register; 0x0000E67D ***/
  union {
    word Word;
  } PWMA_SM2CAPTCOMPB_STR;

  #define PWMA_SM2CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMA_SM2CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMA_SM2CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMA_SM2CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMA_SM2CAPTCOMPB             (*((volatile word *)0x0000E67D))


  /*** PWMA_SM2CAPTCTRLX - Capture Control X Register; 0x0000E67E ***/
  union {
    word Word;
  } PWMA_SM2CAPTCTRLX_STR;

  #define PWMA_SM2CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMA_SM2CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMA_SM2CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMA_SM2CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMA_SM2CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMA_SM2CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMA_SM2CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMA_SM2CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMA_SM2CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMA_SM2CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMA_SM2CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMA_SM2CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMA_SM2CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMA_SM2CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMA_SM2CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMA_SM2CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMA_SM2CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMA_SM2CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMA_SM2CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMA_SM2CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMA_SM2CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMA_SM2CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMA_SM2CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMA_SM2CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMA_SM2CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMA_SM2CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMA_SM2CAPTCTRLX             (*((volatile word *)0x0000E67E))


  /*** PWMA_SM2CAPTCOMPX - Capture Compare X Register; 0x0000E67F ***/
  union {
    word Word;
  } PWMA_SM2CAPTCOMPX_STR;

  #define PWMA_SM2CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMA_SM2CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMA_SM2CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMA_SM2CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMA_SM2CAPTCOMPX             (*((volatile word *)0x0000E67F))


  /*** PWMA_SM2CVAL0 - Capture Value 0 Register; 0x0000E680 ***/
  union {
    word Word;
  } PWMA_SM2CVAL0_STR;

  #define PWMA_SM2CVAL0                 (*((volatile word *)0x0000E680))


  /*** PWMA_SM2CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E681 ***/
  union {
    word Word;
  } PWMA_SM2CVAL0CYC_STR;

  #define PWMA_SM2CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMA_SM2CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMA_SM2CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMA_SM2CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMA_SM2CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMA_SM2CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL0CYC              (*((volatile word *)0x0000E681))


  /*** PWMA_SM2CVAL1 - Capture Value 1 Register; 0x0000E682 ***/
  union {
    word Word;
  } PWMA_SM2CVAL1_STR;

  #define PWMA_SM2CVAL1                 (*((volatile word *)0x0000E682))


  /*** PWMA_SM2CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E683 ***/
  union {
    word Word;
  } PWMA_SM2CVAL1CYC_STR;

  #define PWMA_SM2CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMA_SM2CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMA_SM2CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMA_SM2CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMA_SM2CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMA_SM2CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL1CYC              (*((volatile word *)0x0000E683))


  /*** PWMA_SM2CVAL2 - Capture Value 2 Register; 0x0000E684 ***/
  union {
    word Word;
  } PWMA_SM2CVAL2_STR;

  #define PWMA_SM2CVAL2                 (*((volatile word *)0x0000E684))


  /*** PWMA_SM2CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E685 ***/
  union {
    word Word;
  } PWMA_SM2CVAL2CYC_STR;

  #define PWMA_SM2CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMA_SM2CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMA_SM2CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMA_SM2CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMA_SM2CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMA_SM2CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL2CYC              (*((volatile word *)0x0000E685))


  /*** PWMA_SM2CVAL3 - Capture Value 3 Register; 0x0000E686 ***/
  union {
    word Word;
  } PWMA_SM2CVAL3_STR;

  #define PWMA_SM2CVAL3                 (*((volatile word *)0x0000E686))


  /*** PWMA_SM2CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E687 ***/
  union {
    word Word;
  } PWMA_SM2CVAL3CYC_STR;

  #define PWMA_SM2CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMA_SM2CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMA_SM2CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMA_SM2CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMA_SM2CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMA_SM2CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL3CYC              (*((volatile word *)0x0000E687))


  /*** PWMA_SM2CVAL4 - Capture Value 4 Register; 0x0000E688 ***/
  union {
    word Word;
  } PWMA_SM2CVAL4_STR;

  #define PWMA_SM2CVAL4                 (*((volatile word *)0x0000E688))


  /*** PWMA_SM2CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E689 ***/
  union {
    word Word;
  } PWMA_SM2CVAL4CYC_STR;

  #define PWMA_SM2CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMA_SM2CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMA_SM2CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMA_SM2CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMA_SM2CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMA_SM2CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL4CYC              (*((volatile word *)0x0000E689))


  /*** PWMA_SM2CVAL5 - Capture Value 5 Register; 0x0000E68A ***/
  union {
    word Word;
  } PWMA_SM2CVAL5_STR;

  #define PWMA_SM2CVAL5                 (*((volatile word *)0x0000E68A))


  /*** PWMA_SM2CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E68B ***/
  union {
    word Word;
  } PWMA_SM2CVAL5CYC_STR;

  #define PWMA_SM2CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMA_SM2CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMA_SM2CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMA_SM2CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMA_SM2CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMA_SM2CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMA_SM2CVAL5CYC              (*((volatile word *)0x0000E68B))


  word Reserved5[4];                   /* Reserved (unused) registers */

  /*** PWMA_SM3CNT - Counter Register; 0x0000E690 ***/
  union {
    word Word;
  } PWMA_SM3CNT_STR;

  #define PWMA_SM3CNT                   (*((volatile word *)0x0000E690))


  /*** PWMA_SM3INIT - Initial Count Register; 0x0000E691 ***/
  union {
    word Word;
  } PWMA_SM3INIT_STR;

  #define PWMA_SM3INIT                  (*((volatile word *)0x0000E691))


  /*** PWMA_SM3CTRL2 - Control 2 Register; 0x0000E692 ***/
  union {
    word Word;
  } PWMA_SM3CTRL2_STR;

  #define PWMA_SM3CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMA_SM3CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMA_SM3CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMA_SM3CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMA_SM3CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMA_SM3CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMA_SM3CTRL2_FORCE_MASK      0x40U
  #define PWMA_SM3CTRL2_FRCEN_MASK      0x80U
  #define PWMA_SM3CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMA_SM3CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMA_SM3CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMA_SM3CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMA_SM3CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMA_SM3CTRL2_INDEP_MASK      0x2000U
  #define PWMA_SM3CTRL2_WAITEN_MASK     0x4000U
  #define PWMA_SM3CTRL2_DBGEN_MASK      0x8000U
  #define PWMA_SM3CTRL2_CLK_SEL_MASK    0x03U
  #define PWMA_SM3CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMA_SM3CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMA_SM3CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMA_SM3CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMA_SM3CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMA_SM3CTRL2                 (*((volatile word *)0x0000E692))


  /*** PWMA_SM3CTRL - Control Register; 0x0000E693 ***/
  union {
    word Word;
  } PWMA_SM3CTRL_STR;

  #define PWMA_SM3CTRL_DBLEN_MASK       0x01U
  #define PWMA_SM3CTRL_DBLX_MASK        0x02U
  #define PWMA_SM3CTRL_LDMOD_MASK       0x04U
  #define PWMA_SM3CTRL_PRSC0_MASK       0x10U
  #define PWMA_SM3CTRL_PRSC1_MASK       0x20U
  #define PWMA_SM3CTRL_PRSC2_MASK       0x40U
  #define PWMA_SM3CTRL_DT0_MASK         0x0100U
  #define PWMA_SM3CTRL_DT1_MASK         0x0200U
  #define PWMA_SM3CTRL_FULL_MASK        0x0400U
  #define PWMA_SM3CTRL_HALF_MASK        0x0800U
  #define PWMA_SM3CTRL_LDFQ0_MASK       0x1000U
  #define PWMA_SM3CTRL_LDFQ1_MASK       0x2000U
  #define PWMA_SM3CTRL_LDFQ2_MASK       0x4000U
  #define PWMA_SM3CTRL_LDFQ3_MASK       0x8000U
  #define PWMA_SM3CTRL_PRSC_MASK        0x70U
  #define PWMA_SM3CTRL_PRSC_BITNUM      0x04U
  #define PWMA_SM3CTRL_DT_MASK          0x0300U
  #define PWMA_SM3CTRL_DT_BITNUM        0x08U
  #define PWMA_SM3CTRL_LDFQ_MASK        0xF000U
  #define PWMA_SM3CTRL_LDFQ_BITNUM      0x0CU
  #define PWMA_SM3CTRL                  (*((volatile word *)0x0000E693))


  word Reserved6[1];                   /* Reserved (unused) registers */

  /*** PWMA_SM3VAL0 - Value Register 0; 0x0000E695 ***/
  union {
    word Word;
  } PWMA_SM3VAL0_STR;

  #define PWMA_SM3VAL0                  (*((volatile word *)0x0000E695))


  /*** PWMA_SM3FRACVAL1 - Fractional Value Register 1; 0x0000E696 ***/
  union {
    word Word;
  } PWMA_SM3FRACVAL1_STR;

  #define PWMA_SM3FRACVAL1_FRACVAL10_MASK 0x0800U
  #define PWMA_SM3FRACVAL1_FRACVAL11_MASK 0x1000U
  #define PWMA_SM3FRACVAL1_FRACVAL12_MASK 0x2000U
  #define PWMA_SM3FRACVAL1_FRACVAL13_MASK 0x4000U
  #define PWMA_SM3FRACVAL1_FRACVAL14_MASK 0x8000U
  #define PWMA_SM3FRACVAL1_FRACVAL1_MASK 0xF800U
  #define PWMA_SM3FRACVAL1_FRACVAL1_BITNUM 0x0BU
  #define PWMA_SM3FRACVAL1              (*((volatile word *)0x0000E696))


  /*** PWMA_SM3VAL1 - Value Register 1; 0x0000E697 ***/
  union {
    word Word;
  } PWMA_SM3VAL1_STR;

  #define PWMA_SM3VAL1                  (*((volatile word *)0x0000E697))


  /*** PWMA_SM3FRACVAL2 - Fractional Value Register 2; 0x0000E698 ***/
  union {
    word Word;
  } PWMA_SM3FRACVAL2_STR;

  #define PWMA_SM3FRACVAL2_FRACVAL20_MASK 0x0800U
  #define PWMA_SM3FRACVAL2_FRACVAL21_MASK 0x1000U
  #define PWMA_SM3FRACVAL2_FRACVAL22_MASK 0x2000U
  #define PWMA_SM3FRACVAL2_FRACVAL23_MASK 0x4000U
  #define PWMA_SM3FRACVAL2_FRACVAL24_MASK 0x8000U
  #define PWMA_SM3FRACVAL2_FRACVAL2_MASK 0xF800U
  #define PWMA_SM3FRACVAL2_FRACVAL2_BITNUM 0x0BU
  #define PWMA_SM3FRACVAL2              (*((volatile word *)0x0000E698))


  /*** PWMA_SM3VAL2 - Value Register 2; 0x0000E699 ***/
  union {
    word Word;
  } PWMA_SM3VAL2_STR;

  #define PWMA_SM3VAL2                  (*((volatile word *)0x0000E699))


  /*** PWMA_SM3FRACVAL3 - Fractional Value Register 3; 0x0000E69A ***/
  union {
    word Word;
  } PWMA_SM3FRACVAL3_STR;

  #define PWMA_SM3FRACVAL3_FRACVAL30_MASK 0x0800U
  #define PWMA_SM3FRACVAL3_FRACVAL31_MASK 0x1000U
  #define PWMA_SM3FRACVAL3_FRACVAL32_MASK 0x2000U
  #define PWMA_SM3FRACVAL3_FRACVAL33_MASK 0x4000U
  #define PWMA_SM3FRACVAL3_FRACVAL34_MASK 0x8000U
  #define PWMA_SM3FRACVAL3_FRACVAL3_MASK 0xF800U
  #define PWMA_SM3FRACVAL3_FRACVAL3_BITNUM 0x0BU
  #define PWMA_SM3FRACVAL3              (*((volatile word *)0x0000E69A))


  /*** PWMA_SM3VAL3 - Value Register 3; 0x0000E69B ***/
  union {
    word Word;
  } PWMA_SM3VAL3_STR;

  #define PWMA_SM3VAL3                  (*((volatile word *)0x0000E69B))


  /*** PWMA_SM3FRACVAL4 - Fractional Value Register 4; 0x0000E69C ***/
  union {
    word Word;
  } PWMA_SM3FRACVAL4_STR;

  #define PWMA_SM3FRACVAL4_FRACVAL40_MASK 0x0800U
  #define PWMA_SM3FRACVAL4_FRACVAL41_MASK 0x1000U
  #define PWMA_SM3FRACVAL4_FRACVAL42_MASK 0x2000U
  #define PWMA_SM3FRACVAL4_FRACVAL43_MASK 0x4000U
  #define PWMA_SM3FRACVAL4_FRACVAL44_MASK 0x8000U
  #define PWMA_SM3FRACVAL4_FRACVAL4_MASK 0xF800U
  #define PWMA_SM3FRACVAL4_FRACVAL4_BITNUM 0x0BU
  #define PWMA_SM3FRACVAL4              (*((volatile word *)0x0000E69C))


  /*** PWMA_SM3VAL4 - Value Register 4; 0x0000E69D ***/
  union {
    word Word;
  } PWMA_SM3VAL4_STR;

  #define PWMA_SM3VAL4                  (*((volatile word *)0x0000E69D))


  /*** PWMA_SM3FRACVAL5 - Fractional Value Register 5; 0x0000E69E ***/
  union {
    word Word;
  } PWMA_SM3FRACVAL5_STR;

  #define PWMA_SM3FRACVAL5_FRACVAL50_MASK 0x0800U
  #define PWMA_SM3FRACVAL5_FRACVAL51_MASK 0x1000U
  #define PWMA_SM3FRACVAL5_FRACVAL52_MASK 0x2000U
  #define PWMA_SM3FRACVAL5_FRACVAL53_MASK 0x4000U
  #define PWMA_SM3FRACVAL5_FRACVAL54_MASK 0x8000U
  #define PWMA_SM3FRACVAL5_FRACVAL5_MASK 0xF800U
  #define PWMA_SM3FRACVAL5_FRACVAL5_BITNUM 0x0BU
  #define PWMA_SM3FRACVAL5              (*((volatile word *)0x0000E69E))


  /*** PWMA_SM3VAL5 - Value Register 5; 0x0000E69F ***/
  union {
    word Word;
  } PWMA_SM3VAL5_STR;

  #define PWMA_SM3VAL5                  (*((volatile word *)0x0000E69F))


  /*** PWMA_SM3FRCTRL - Fractional Control Register; 0x0000E6A0 ***/
  union {
    word Word;
  } PWMA_SM3FRCTRL_STR;

  #define PWMA_SM3FRCTRL_FRAC1_EN_MASK  0x02U
  #define PWMA_SM3FRCTRL_FRAC23_EN_MASK 0x04U
  #define PWMA_SM3FRCTRL_FRAC45_EN_MASK 0x10U
  #define PWMA_SM3FRCTRL_FRAC_PU_MASK   0x0100U
  #define PWMA_SM3FRCTRL_TEST_MASK      0x8000U
  #define PWMA_SM3FRCTRL                (*((volatile word *)0x0000E6A0))


  /*** PWMA_SM3OCTRL - Output Control Register; 0x0000E6A1 ***/
  union {
    word Word;
  } PWMA_SM3OCTRL_STR;

  #define PWMA_SM3OCTRL_PWMXFS0_MASK    0x01U
  #define PWMA_SM3OCTRL_PWMXFS1_MASK    0x02U
  #define PWMA_SM3OCTRL_PWMBFS0_MASK    0x04U
  #define PWMA_SM3OCTRL_PWMBFS1_MASK    0x08U
  #define PWMA_SM3OCTRL_PWMAFS0_MASK    0x10U
  #define PWMA_SM3OCTRL_PWMAFS1_MASK    0x20U
  #define PWMA_SM3OCTRL_POLX_MASK       0x0100U
  #define PWMA_SM3OCTRL_POLB_MASK       0x0200U
  #define PWMA_SM3OCTRL_POLA_MASK       0x0400U
  #define PWMA_SM3OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMA_SM3OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMA_SM3OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMA_SM3OCTRL_PWMXFS_MASK     0x03U
  #define PWMA_SM3OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMA_SM3OCTRL_PWMBFS_MASK     0x0CU
  #define PWMA_SM3OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMA_SM3OCTRL_PWMAFS_MASK     0x30U
  #define PWMA_SM3OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMA_SM3OCTRL                 (*((volatile word *)0x0000E6A1))


  /*** PWMA_SM3STS - Status Register; 0x0000E6A2 ***/
  union {
    word Word;
  } PWMA_SM3STS_STR;

  #define PWMA_SM3STS_CMPF0_MASK        0x01U
  #define PWMA_SM3STS_CMPF1_MASK        0x02U
  #define PWMA_SM3STS_CMPF2_MASK        0x04U
  #define PWMA_SM3STS_CMPF3_MASK        0x08U
  #define PWMA_SM3STS_CMPF4_MASK        0x10U
  #define PWMA_SM3STS_CMPF5_MASK        0x20U
  #define PWMA_SM3STS_CFX0_MASK         0x40U
  #define PWMA_SM3STS_CFX1_MASK         0x80U
  #define PWMA_SM3STS_CFB0_MASK         0x0100U
  #define PWMA_SM3STS_CFB1_MASK         0x0200U
  #define PWMA_SM3STS_CFA0_MASK         0x0400U
  #define PWMA_SM3STS_CFA1_MASK         0x0800U
  #define PWMA_SM3STS_RF_MASK           0x1000U
  #define PWMA_SM3STS_REF_MASK          0x2000U
  #define PWMA_SM3STS_RUF_MASK          0x4000U
  #define PWMA_SM3STS_CMPF_MASK         0x3FU
  #define PWMA_SM3STS_CMPF_BITNUM       0x00U
  #define PWMA_SM3STS                   (*((volatile word *)0x0000E6A2))


  /*** PWMA_SM3INTEN - Interrupt Enable Register; 0x0000E6A3 ***/
  union {
    word Word;
  } PWMA_SM3INTEN_STR;

  #define PWMA_SM3INTEN_CMPIE0_MASK     0x01U
  #define PWMA_SM3INTEN_CMPIE1_MASK     0x02U
  #define PWMA_SM3INTEN_CMPIE2_MASK     0x04U
  #define PWMA_SM3INTEN_CMPIE3_MASK     0x08U
  #define PWMA_SM3INTEN_CMPIE4_MASK     0x10U
  #define PWMA_SM3INTEN_CMPIE5_MASK     0x20U
  #define PWMA_SM3INTEN_CX0IE_MASK      0x40U
  #define PWMA_SM3INTEN_CX1IE_MASK      0x80U
  #define PWMA_SM3INTEN_CB0IE_MASK      0x0100U
  #define PWMA_SM3INTEN_CB1IE_MASK      0x0200U
  #define PWMA_SM3INTEN_CA0IE_MASK      0x0400U
  #define PWMA_SM3INTEN_CA1IE_MASK      0x0800U
  #define PWMA_SM3INTEN_RIE_MASK        0x1000U
  #define PWMA_SM3INTEN_REIE_MASK       0x2000U
  #define PWMA_SM3INTEN_CMPIE_MASK      0x3FU
  #define PWMA_SM3INTEN_CMPIE_BITNUM    0x00U
  #define PWMA_SM3INTEN                 (*((volatile word *)0x0000E6A3))


  /*** PWMA_SM3DMAEN - DMA Enable Register; 0x0000E6A4 ***/
  union {
    word Word;
  } PWMA_SM3DMAEN_STR;

  #define PWMA_SM3DMAEN_CX0DE_MASK      0x01U
  #define PWMA_SM3DMAEN_CX1DE_MASK      0x02U
  #define PWMA_SM3DMAEN_CB0DE_MASK      0x04U
  #define PWMA_SM3DMAEN_CB1DE_MASK      0x08U
  #define PWMA_SM3DMAEN_CA0DE_MASK      0x10U
  #define PWMA_SM3DMAEN_CA1DE_MASK      0x20U
  #define PWMA_SM3DMAEN_CAPTDE0_MASK    0x40U
  #define PWMA_SM3DMAEN_CAPTDE1_MASK    0x80U
  #define PWMA_SM3DMAEN_FAND_MASK       0x0100U
  #define PWMA_SM3DMAEN_VALDE_MASK      0x0200U
  #define PWMA_SM3DMAEN_CAPTDE_MASK     0xC0U
  #define PWMA_SM3DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMA_SM3DMAEN                 (*((volatile word *)0x0000E6A4))


  /*** PWMA_SM3TCTRL - Output Trigger Control Register; 0x0000E6A5 ***/
  union {
    word Word;
  } PWMA_SM3TCTRL_STR;

  #define PWMA_SM3TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMA_SM3TCTRL_PWBOT1_MASK     0x4000U
  #define PWMA_SM3TCTRL_PWAOT0_MASK     0x8000U
  #define PWMA_SM3TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMA_SM3TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMA_SM3TCTRL                 (*((volatile word *)0x0000E6A5))


  /*** PWMA_SM3DISMAP0 - Fault Disable Mapping Register 0; 0x0000E6A6 ***/
  union {
    word Word;
  } PWMA_SM3DISMAP0_STR;

  #define PWMA_SM3DISMAP0_DIS0A0_MASK   0x01U
  #define PWMA_SM3DISMAP0_DIS0A1_MASK   0x02U
  #define PWMA_SM3DISMAP0_DIS0A2_MASK   0x04U
  #define PWMA_SM3DISMAP0_DIS0A3_MASK   0x08U
  #define PWMA_SM3DISMAP0_DIS0B0_MASK   0x10U
  #define PWMA_SM3DISMAP0_DIS0B1_MASK   0x20U
  #define PWMA_SM3DISMAP0_DIS0B2_MASK   0x40U
  #define PWMA_SM3DISMAP0_DIS0B3_MASK   0x80U
  #define PWMA_SM3DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMA_SM3DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMA_SM3DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMA_SM3DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMA_SM3DISMAP0_DIS0A_MASK    0x0FU
  #define PWMA_SM3DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMA_SM3DISMAP0_DIS0B_MASK    0xF0U
  #define PWMA_SM3DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMA_SM3DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMA_SM3DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMA_SM3DISMAP0               (*((volatile word *)0x0000E6A6))


  /*** PWMA_SM3DISMAP1 - Fault Disable Mapping Register 1; 0x0000E6A7 ***/
  union {
    word Word;
  } PWMA_SM3DISMAP1_STR;

  #define PWMA_SM3DISMAP1_DIS1A0_MASK   0x01U
  #define PWMA_SM3DISMAP1_DIS1A1_MASK   0x02U
  #define PWMA_SM3DISMAP1_DIS1A2_MASK   0x04U
  #define PWMA_SM3DISMAP1_DIS1A3_MASK   0x08U
  #define PWMA_SM3DISMAP1_DIS1B0_MASK   0x10U
  #define PWMA_SM3DISMAP1_DIS1B1_MASK   0x20U
  #define PWMA_SM3DISMAP1_DIS1B2_MASK   0x40U
  #define PWMA_SM3DISMAP1_DIS1B3_MASK   0x80U
  #define PWMA_SM3DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMA_SM3DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMA_SM3DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMA_SM3DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMA_SM3DISMAP1_DIS1A_MASK    0x0FU
  #define PWMA_SM3DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMA_SM3DISMAP1_DIS1B_MASK    0xF0U
  #define PWMA_SM3DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMA_SM3DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMA_SM3DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMA_SM3DISMAP1               (*((volatile word *)0x0000E6A7))


  /*** PWMA_SM3DTCNT0 - Deadtime Count Register 0; 0x0000E6A8 ***/
  union {
    word Word;
  } PWMA_SM3DTCNT0_STR;

  #define PWMA_SM3DTCNT0_DTCNT00_MASK   0x01U
  #define PWMA_SM3DTCNT0_DTCNT01_MASK   0x02U
  #define PWMA_SM3DTCNT0_DTCNT02_MASK   0x04U
  #define PWMA_SM3DTCNT0_DTCNT03_MASK   0x08U
  #define PWMA_SM3DTCNT0_DTCNT04_MASK   0x10U
  #define PWMA_SM3DTCNT0_DTCNT05_MASK   0x20U
  #define PWMA_SM3DTCNT0_DTCNT06_MASK   0x40U
  #define PWMA_SM3DTCNT0_DTCNT07_MASK   0x80U
  #define PWMA_SM3DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMA_SM3DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMA_SM3DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMA_SM3DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMA_SM3DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMA_SM3DTCNT0                (*((volatile word *)0x0000E6A8))


  /*** PWMA_SM3DTCNT1 - Deadtime Count Register 1; 0x0000E6A9 ***/
  union {
    word Word;
  } PWMA_SM3DTCNT1_STR;

  #define PWMA_SM3DTCNT1_DTCNT10_MASK   0x01U
  #define PWMA_SM3DTCNT1_DTCNT11_MASK   0x02U
  #define PWMA_SM3DTCNT1_DTCNT12_MASK   0x04U
  #define PWMA_SM3DTCNT1_DTCNT13_MASK   0x08U
  #define PWMA_SM3DTCNT1_DTCNT14_MASK   0x10U
  #define PWMA_SM3DTCNT1_DTCNT15_MASK   0x20U
  #define PWMA_SM3DTCNT1_DTCNT16_MASK   0x40U
  #define PWMA_SM3DTCNT1_DTCNT17_MASK   0x80U
  #define PWMA_SM3DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMA_SM3DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMA_SM3DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMA_SM3DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMA_SM3DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMA_SM3DTCNT1                (*((volatile word *)0x0000E6A9))


  /*** PWMA_SM3CAPTCTRLA - Capture Control A Register; 0x0000E6AA ***/
  union {
    word Word;
  } PWMA_SM3CAPTCTRLA_STR;

  #define PWMA_SM3CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMA_SM3CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMA_SM3CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMA_SM3CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMA_SM3CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMA_SM3CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMA_SM3CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMA_SM3CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMA_SM3CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMA_SM3CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMA_SM3CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMA_SM3CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMA_SM3CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMA_SM3CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMA_SM3CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMA_SM3CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMA_SM3CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMA_SM3CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMA_SM3CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMA_SM3CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMA_SM3CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMA_SM3CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMA_SM3CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMA_SM3CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMA_SM3CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMA_SM3CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMA_SM3CAPTCTRLA             (*((volatile word *)0x0000E6AA))


  /*** PWMA_SM3CAPTCOMPA - Capture Compare A Register; 0x0000E6AB ***/
  union {
    word Word;
  } PWMA_SM3CAPTCOMPA_STR;

  #define PWMA_SM3CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMA_SM3CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMA_SM3CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMA_SM3CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMA_SM3CAPTCOMPA             (*((volatile word *)0x0000E6AB))


  /*** PWMA_SM3CAPTCTRLB - Capture Control B Register; 0x0000E6AC ***/
  union {
    word Word;
  } PWMA_SM3CAPTCTRLB_STR;

  #define PWMA_SM3CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMA_SM3CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMA_SM3CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMA_SM3CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMA_SM3CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMA_SM3CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMA_SM3CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMA_SM3CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMA_SM3CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMA_SM3CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMA_SM3CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMA_SM3CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMA_SM3CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMA_SM3CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMA_SM3CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMA_SM3CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMA_SM3CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMA_SM3CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMA_SM3CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMA_SM3CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMA_SM3CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMA_SM3CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMA_SM3CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMA_SM3CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMA_SM3CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMA_SM3CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMA_SM3CAPTCTRLB             (*((volatile word *)0x0000E6AC))


  /*** PWMA_SM3CAPTCOMPB - Capture Compare B Register; 0x0000E6AD ***/
  union {
    word Word;
  } PWMA_SM3CAPTCOMPB_STR;

  #define PWMA_SM3CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMA_SM3CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMA_SM3CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMA_SM3CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMA_SM3CAPTCOMPB             (*((volatile word *)0x0000E6AD))


  /*** PWMA_SM3CAPTCTRLX - Capture Control X Register; 0x0000E6AE ***/
  union {
    word Word;
  } PWMA_SM3CAPTCTRLX_STR;

  #define PWMA_SM3CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMA_SM3CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMA_SM3CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMA_SM3CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMA_SM3CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMA_SM3CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMA_SM3CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMA_SM3CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMA_SM3CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMA_SM3CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMA_SM3CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMA_SM3CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMA_SM3CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMA_SM3CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMA_SM3CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMA_SM3CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMA_SM3CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMA_SM3CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMA_SM3CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMA_SM3CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMA_SM3CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMA_SM3CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMA_SM3CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMA_SM3CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMA_SM3CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMA_SM3CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMA_SM3CAPTCTRLX             (*((volatile word *)0x0000E6AE))


  /*** PWMA_SM3CAPTCOMPX - Capture Compare X Register; 0x0000E6AF ***/
  union {
    word Word;
  } PWMA_SM3CAPTCOMPX_STR;

  #define PWMA_SM3CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMA_SM3CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMA_SM3CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMA_SM3CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMA_SM3CAPTCOMPX             (*((volatile word *)0x0000E6AF))


  /*** PWMA_SM3CVAL0 - Capture Value 0 Register; 0x0000E6B0 ***/
  union {
    word Word;
  } PWMA_SM3CVAL0_STR;

  #define PWMA_SM3CVAL0                 (*((volatile word *)0x0000E6B0))


  /*** PWMA_SM3CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E6B1 ***/
  union {
    word Word;
  } PWMA_SM3CVAL0CYC_STR;

  #define PWMA_SM3CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMA_SM3CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMA_SM3CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMA_SM3CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMA_SM3CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMA_SM3CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL0CYC              (*((volatile word *)0x0000E6B1))


  /*** PWMA_SM3CVAL1 - Capture Value 1 Register; 0x0000E6B2 ***/
  union {
    word Word;
  } PWMA_SM3CVAL1_STR;

  #define PWMA_SM3CVAL1                 (*((volatile word *)0x0000E6B2))


  /*** PWMA_SM3CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E6B3 ***/
  union {
    word Word;
  } PWMA_SM3CVAL1CYC_STR;

  #define PWMA_SM3CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMA_SM3CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMA_SM3CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMA_SM3CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMA_SM3CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMA_SM3CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL1CYC              (*((volatile word *)0x0000E6B3))


  /*** PWMA_SM3CVAL2 - Capture Value 2 Register; 0x0000E6B4 ***/
  union {
    word Word;
  } PWMA_SM3CVAL2_STR;

  #define PWMA_SM3CVAL2                 (*((volatile word *)0x0000E6B4))


  /*** PWMA_SM3CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E6B5 ***/
  union {
    word Word;
  } PWMA_SM3CVAL2CYC_STR;

  #define PWMA_SM3CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMA_SM3CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMA_SM3CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMA_SM3CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMA_SM3CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMA_SM3CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL2CYC              (*((volatile word *)0x0000E6B5))


  /*** PWMA_SM3CVAL3 - Capture Value 3 Register; 0x0000E6B6 ***/
  union {
    word Word;
  } PWMA_SM3CVAL3_STR;

  #define PWMA_SM3CVAL3                 (*((volatile word *)0x0000E6B6))


  /*** PWMA_SM3CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E6B7 ***/
  union {
    word Word;
  } PWMA_SM3CVAL3CYC_STR;

  #define PWMA_SM3CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMA_SM3CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMA_SM3CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMA_SM3CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMA_SM3CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMA_SM3CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL3CYC              (*((volatile word *)0x0000E6B7))


  /*** PWMA_SM3CVAL4 - Capture Value 4 Register; 0x0000E6B8 ***/
  union {
    word Word;
  } PWMA_SM3CVAL4_STR;

  #define PWMA_SM3CVAL4                 (*((volatile word *)0x0000E6B8))


  /*** PWMA_SM3CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E6B9 ***/
  union {
    word Word;
  } PWMA_SM3CVAL4CYC_STR;

  #define PWMA_SM3CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMA_SM3CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMA_SM3CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMA_SM3CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMA_SM3CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMA_SM3CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL4CYC              (*((volatile word *)0x0000E6B9))


  /*** PWMA_SM3CVAL5 - Capture Value 5 Register; 0x0000E6BA ***/
  union {
    word Word;
  } PWMA_SM3CVAL5_STR;

  #define PWMA_SM3CVAL5                 (*((volatile word *)0x0000E6BA))


  /*** PWMA_SM3CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E6BB ***/
  union {
    word Word;
  } PWMA_SM3CVAL5CYC_STR;

  #define PWMA_SM3CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMA_SM3CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMA_SM3CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMA_SM3CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMA_SM3CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMA_SM3CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMA_SM3CVAL5CYC              (*((volatile word *)0x0000E6BB))


  word Reserved7[4];                   /* Reserved (unused) registers */

  /*** PWMA_OUTEN - Output Enable Register; 0x0000E6C0 ***/
  union {
    word Word;
  } PWMA_OUTEN_STR;

  #define PWMA_OUTEN_PWMX_EN0_MASK      0x01U
  #define PWMA_OUTEN_PWMX_EN1_MASK      0x02U
  #define PWMA_OUTEN_PWMX_EN2_MASK      0x04U
  #define PWMA_OUTEN_PWMX_EN3_MASK      0x08U
  #define PWMA_OUTEN_PWMB_EN0_MASK      0x10U
  #define PWMA_OUTEN_PWMB_EN1_MASK      0x20U
  #define PWMA_OUTEN_PWMB_EN2_MASK      0x40U
  #define PWMA_OUTEN_PWMB_EN3_MASK      0x80U
  #define PWMA_OUTEN_PWMA_EN0_MASK      0x0100U
  #define PWMA_OUTEN_PWMA_EN1_MASK      0x0200U
  #define PWMA_OUTEN_PWMA_EN2_MASK      0x0400U
  #define PWMA_OUTEN_PWMA_EN3_MASK      0x0800U
  #define PWMA_OUTEN_PWMX_EN_MASK       0x0FU
  #define PWMA_OUTEN_PWMX_EN_BITNUM     0x00U
  #define PWMA_OUTEN_PWMB_EN_MASK       0xF0U
  #define PWMA_OUTEN_PWMB_EN_BITNUM     0x04U
  #define PWMA_OUTEN_PWMA_EN_MASK       0x0F00U
  #define PWMA_OUTEN_PWMA_EN_BITNUM     0x08U
  #define PWMA_OUTEN                    (*((volatile word *)0x0000E6C0))


  /*** PWMA_MASK - Mask Register; 0x0000E6C1 ***/
  union {
    word Word;
  } PWMA_MASK_STR;

  #define PWMA_MASK_MASKX0_MASK         0x01U
  #define PWMA_MASK_MASKX1_MASK         0x02U
  #define PWMA_MASK_MASKX2_MASK         0x04U
  #define PWMA_MASK_MASKX3_MASK         0x08U
  #define PWMA_MASK_MASKB0_MASK         0x10U
  #define PWMA_MASK_MASKB1_MASK         0x20U
  #define PWMA_MASK_MASKB2_MASK         0x40U
  #define PWMA_MASK_MASKB3_MASK         0x80U
  #define PWMA_MASK_MASKA0_MASK         0x0100U
  #define PWMA_MASK_MASKA1_MASK         0x0200U
  #define PWMA_MASK_MASKA2_MASK         0x0400U
  #define PWMA_MASK_MASKA3_MASK         0x0800U
  #define PWMA_MASK_MASKX_MASK          0x0FU
  #define PWMA_MASK_MASKX_BITNUM        0x00U
  #define PWMA_MASK_MASKB_MASK          0xF0U
  #define PWMA_MASK_MASKB_BITNUM        0x04U
  #define PWMA_MASK_MASKA_MASK          0x0F00U
  #define PWMA_MASK_MASKA_BITNUM        0x08U
  #define PWMA_MASK                     (*((volatile word *)0x0000E6C1))


  /*** PWMA_SWCOUT - Software Controlled Output Register; 0x0000E6C2 ***/
  union {
    word Word;
  } PWMA_SWCOUT_STR;

  #define PWMA_SWCOUT_SM0OUT45_MASK     0x01U
  #define PWMA_SWCOUT_SM0OUT23_MASK     0x02U
  #define PWMA_SWCOUT_SM1OUT45_MASK     0x04U
  #define PWMA_SWCOUT_SM1OUT23_MASK     0x08U
  #define PWMA_SWCOUT_SM2OUT45_MASK     0x10U
  #define PWMA_SWCOUT_SM2OUT23_MASK     0x20U
  #define PWMA_SWCOUT_SM3OUT45_MASK     0x40U
  #define PWMA_SWCOUT_SM3OUT23_MASK     0x80U
  #define PWMA_SWCOUT                   (*((volatile word *)0x0000E6C2))


  /*** PWMA_DTSRCSEL - Deadtime Source Select Register; 0x0000E6C3 ***/
  union {
    word Word;
  } PWMA_DTSRCSEL_STR;

  #define PWMA_DTSRCSEL_SM0SEL450_MASK  0x01U
  #define PWMA_DTSRCSEL_SM0SEL451_MASK  0x02U
  #define PWMA_DTSRCSEL_SM0SEL230_MASK  0x04U
  #define PWMA_DTSRCSEL_SM0SEL231_MASK  0x08U
  #define PWMA_DTSRCSEL_SM1SEL450_MASK  0x10U
  #define PWMA_DTSRCSEL_SM1SEL451_MASK  0x20U
  #define PWMA_DTSRCSEL_SM1SEL230_MASK  0x40U
  #define PWMA_DTSRCSEL_SM1SEL231_MASK  0x80U
  #define PWMA_DTSRCSEL_SM2SEL450_MASK  0x0100U
  #define PWMA_DTSRCSEL_SM2SEL451_MASK  0x0200U
  #define PWMA_DTSRCSEL_SM2SEL230_MASK  0x0400U
  #define PWMA_DTSRCSEL_SM2SEL231_MASK  0x0800U
  #define PWMA_DTSRCSEL_SM3SEL450_MASK  0x1000U
  #define PWMA_DTSRCSEL_SM3SEL451_MASK  0x2000U
  #define PWMA_DTSRCSEL_SM3SEL230_MASK  0x4000U
  #define PWMA_DTSRCSEL_SM3SEL231_MASK  0x8000U
  #define PWMA_DTSRCSEL_SM0SEL45_MASK   0x03U
  #define PWMA_DTSRCSEL_SM0SEL45_BITNUM 0x00U
  #define PWMA_DTSRCSEL_SM0SEL23_MASK   0x0CU
  #define PWMA_DTSRCSEL_SM0SEL23_BITNUM 0x02U
  #define PWMA_DTSRCSEL_SM1SEL45_MASK   0x30U
  #define PWMA_DTSRCSEL_SM1SEL45_BITNUM 0x04U
  #define PWMA_DTSRCSEL_SM1SEL23_MASK   0xC0U
  #define PWMA_DTSRCSEL_SM1SEL23_BITNUM 0x06U
  #define PWMA_DTSRCSEL_SM2SEL45_MASK   0x0300U
  #define PWMA_DTSRCSEL_SM2SEL45_BITNUM 0x08U
  #define PWMA_DTSRCSEL_SM2SEL23_MASK   0x0C00U
  #define PWMA_DTSRCSEL_SM2SEL23_BITNUM 0x0AU
  #define PWMA_DTSRCSEL_SM3SEL45_MASK   0x3000U
  #define PWMA_DTSRCSEL_SM3SEL45_BITNUM 0x0CU
  #define PWMA_DTSRCSEL_SM3SEL23_MASK   0xC000U
  #define PWMA_DTSRCSEL_SM3SEL23_BITNUM 0x0EU
  #define PWMA_DTSRCSEL                 (*((volatile word *)0x0000E6C3))


  /*** PWMA_MCTRL - Master Control Register; 0x0000E6C4 ***/
  union {
    word Word;
  } PWMA_MCTRL_STR;

  #define PWMA_MCTRL_LDOK0_MASK         0x01U
  #define PWMA_MCTRL_LDOK1_MASK         0x02U
  #define PWMA_MCTRL_LDOK2_MASK         0x04U
  #define PWMA_MCTRL_LDOK3_MASK         0x08U
  #define PWMA_MCTRL_CLDOK0_MASK        0x10U
  #define PWMA_MCTRL_CLDOK1_MASK        0x20U
  #define PWMA_MCTRL_CLDOK2_MASK        0x40U
  #define PWMA_MCTRL_CLDOK3_MASK        0x80U
  #define PWMA_MCTRL_RUN0_MASK          0x0100U
  #define PWMA_MCTRL_RUN1_MASK          0x0200U
  #define PWMA_MCTRL_RUN2_MASK          0x0400U
  #define PWMA_MCTRL_RUN3_MASK          0x0800U
  #define PWMA_MCTRL_IPOL0_MASK         0x1000U
  #define PWMA_MCTRL_IPOL1_MASK         0x2000U
  #define PWMA_MCTRL_IPOL2_MASK         0x4000U
  #define PWMA_MCTRL_IPOL3_MASK         0x8000U
  #define PWMA_MCTRL_LDOK_MASK          0x0FU
  #define PWMA_MCTRL_LDOK_BITNUM        0x00U
  #define PWMA_MCTRL_CLDOK_MASK         0xF0U
  #define PWMA_MCTRL_CLDOK_BITNUM       0x04U
  #define PWMA_MCTRL_RUN_MASK           0x0F00U
  #define PWMA_MCTRL_RUN_BITNUM         0x08U
  #define PWMA_MCTRL_IPOL_MASK          0xF000U
  #define PWMA_MCTRL_IPOL_BITNUM        0x0CU
  #define PWMA_MCTRL                    (*((volatile word *)0x0000E6C4))


  /*** PWMA_MCTRL2 - Master Control 2 Register; 0x0000E6C5 ***/
  union {
    word Word;
  } PWMA_MCTRL2_STR;

  #define PWMA_MCTRL2_MONPLL0_MASK      0x01U
  #define PWMA_MCTRL2_MONPLL1_MASK      0x02U
  #define PWMA_MCTRL2_MONPLL_MASK       0x03U
  #define PWMA_MCTRL2_MONPLL_BITNUM     0x00U
  #define PWMA_MCTRL2                   (*((volatile word *)0x0000E6C5))


  /*** PWMA_FCTRL0 - Fault Control Register; 0x0000E6C6 ***/
  union {
    word Word;
  } PWMA_FCTRL0_STR;

  #define PWMA_FCTRL0_FIE0_MASK         0x01U
  #define PWMA_FCTRL0_FIE1_MASK         0x02U
  #define PWMA_FCTRL0_FIE2_MASK         0x04U
  #define PWMA_FCTRL0_FIE3_MASK         0x08U
  #define PWMA_FCTRL0_FSAFE0_MASK       0x10U
  #define PWMA_FCTRL0_FSAFE1_MASK       0x20U
  #define PWMA_FCTRL0_FSAFE2_MASK       0x40U
  #define PWMA_FCTRL0_FSAFE3_MASK       0x80U
  #define PWMA_FCTRL0_FAUTO0_MASK       0x0100U
  #define PWMA_FCTRL0_FAUTO1_MASK       0x0200U
  #define PWMA_FCTRL0_FAUTO2_MASK       0x0400U
  #define PWMA_FCTRL0_FAUTO3_MASK       0x0800U
  #define PWMA_FCTRL0_FLVL0_MASK        0x1000U
  #define PWMA_FCTRL0_FLVL1_MASK        0x2000U
  #define PWMA_FCTRL0_FLVL2_MASK        0x4000U
  #define PWMA_FCTRL0_FLVL3_MASK        0x8000U
  #define PWMA_FCTRL0_FIE_MASK          0x0FU
  #define PWMA_FCTRL0_FIE_BITNUM        0x00U
  #define PWMA_FCTRL0_FSAFE_MASK        0xF0U
  #define PWMA_FCTRL0_FSAFE_BITNUM      0x04U
  #define PWMA_FCTRL0_FAUTO_MASK        0x0F00U
  #define PWMA_FCTRL0_FAUTO_BITNUM      0x08U
  #define PWMA_FCTRL0_FLVL_MASK         0xF000U
  #define PWMA_FCTRL0_FLVL_BITNUM       0x0CU
  #define PWMA_FCTRL0                   (*((volatile word *)0x0000E6C6))


  /*** PWMA_FSTS0 - Fault Status Register; 0x0000E6C7 ***/
  union {
    word Word;
  } PWMA_FSTS0_STR;

  #define PWMA_FSTS0_FFLAG0_MASK        0x01U
  #define PWMA_FSTS0_FFLAG1_MASK        0x02U
  #define PWMA_FSTS0_FFLAG2_MASK        0x04U
  #define PWMA_FSTS0_FFLAG3_MASK        0x08U
  #define PWMA_FSTS0_FFULL0_MASK        0x10U
  #define PWMA_FSTS0_FFULL1_MASK        0x20U
  #define PWMA_FSTS0_FFULL2_MASK        0x40U
  #define PWMA_FSTS0_FFULL3_MASK        0x80U
  #define PWMA_FSTS0_FFPIN0_MASK        0x0100U
  #define PWMA_FSTS0_FFPIN1_MASK        0x0200U
  #define PWMA_FSTS0_FFPIN2_MASK        0x0400U
  #define PWMA_FSTS0_FFPIN3_MASK        0x0800U
  #define PWMA_FSTS0_FHALF0_MASK        0x1000U
  #define PWMA_FSTS0_FHALF1_MASK        0x2000U
  #define PWMA_FSTS0_FHALF2_MASK        0x4000U
  #define PWMA_FSTS0_FHALF3_MASK        0x8000U
  #define PWMA_FSTS0_FFLAG_MASK         0x0FU
  #define PWMA_FSTS0_FFLAG_BITNUM       0x00U
  #define PWMA_FSTS0_FFULL_MASK         0xF0U
  #define PWMA_FSTS0_FFULL_BITNUM       0x04U
  #define PWMA_FSTS0_FFPIN_MASK         0x0F00U
  #define PWMA_FSTS0_FFPIN_BITNUM       0x08U
  #define PWMA_FSTS0_FHALF_MASK         0xF000U
  #define PWMA_FSTS0_FHALF_BITNUM       0x0CU
  #define PWMA_FSTS0                    (*((volatile word *)0x0000E6C7))


  /*** PWMA_FFILT0 - Fault Filter Register; 0x0000E6C8 ***/
  union {
    word Word;
  } PWMA_FFILT0_STR;

  #define PWMA_FFILT0_FILT_PER0_MASK    0x01U
  #define PWMA_FFILT0_FILT_PER1_MASK    0x02U
  #define PWMA_FFILT0_FILT_PER2_MASK    0x04U
  #define PWMA_FFILT0_FILT_PER3_MASK    0x08U
  #define PWMA_FFILT0_FILT_PER4_MASK    0x10U
  #define PWMA_FFILT0_FILT_PER5_MASK    0x20U
  #define PWMA_FFILT0_FILT_PER6_MASK    0x40U
  #define PWMA_FFILT0_FILT_PER7_MASK    0x80U
  #define PWMA_FFILT0_FILT_CNT0_MASK    0x0100U
  #define PWMA_FFILT0_FILT_CNT1_MASK    0x0200U
  #define PWMA_FFILT0_FILT_CNT2_MASK    0x0400U
  #define PWMA_FFILT0_GSTR_MASK         0x8000U
  #define PWMA_FFILT0_FILT_PER_MASK     0xFFU
  #define PWMA_FFILT0_FILT_PER_BITNUM   0x00U
  #define PWMA_FFILT0_FILT_CNT_MASK     0x0700U
  #define PWMA_FFILT0_FILT_CNT_BITNUM   0x08U
  #define PWMA_FFILT0                   (*((volatile word *)0x0000E6C8))


  /*** PWMA_FTST0 - Fault Test Register; 0x0000E6C9 ***/
  union {
    word Word;
  } PWMA_FTST0_STR;

  #define PWMA_FTST0_FTEST_MASK         0x01U
  #define PWMA_FTST0                    (*((volatile word *)0x0000E6C9))


  /*** PWMA_FCTRL1 - Fault Control Register; 0x0000E6CA ***/
  union {
    word Word;
  } PWMA_FCTRL1_STR;

  #define PWMA_FCTRL1_FIE0_MASK         0x01U
  #define PWMA_FCTRL1_FIE1_MASK         0x02U
  #define PWMA_FCTRL1_FIE2_MASK         0x04U
  #define PWMA_FCTRL1_FIE3_MASK         0x08U
  #define PWMA_FCTRL1_FSAFE0_MASK       0x10U
  #define PWMA_FCTRL1_FSAFE1_MASK       0x20U
  #define PWMA_FCTRL1_FSAFE2_MASK       0x40U
  #define PWMA_FCTRL1_FSAFE3_MASK       0x80U
  #define PWMA_FCTRL1_FAUTO0_MASK       0x0100U
  #define PWMA_FCTRL1_FAUTO1_MASK       0x0200U
  #define PWMA_FCTRL1_FAUTO2_MASK       0x0400U
  #define PWMA_FCTRL1_FAUTO3_MASK       0x0800U
  #define PWMA_FCTRL1_FLVL0_MASK        0x1000U
  #define PWMA_FCTRL1_FLVL1_MASK        0x2000U
  #define PWMA_FCTRL1_FLVL2_MASK        0x4000U
  #define PWMA_FCTRL1_FLVL3_MASK        0x8000U
  #define PWMA_FCTRL1_FIE_MASK          0x0FU
  #define PWMA_FCTRL1_FIE_BITNUM        0x00U
  #define PWMA_FCTRL1_FSAFE_MASK        0xF0U
  #define PWMA_FCTRL1_FSAFE_BITNUM      0x04U
  #define PWMA_FCTRL1_FAUTO_MASK        0x0F00U
  #define PWMA_FCTRL1_FAUTO_BITNUM      0x08U
  #define PWMA_FCTRL1_FLVL_MASK         0xF000U
  #define PWMA_FCTRL1_FLVL_BITNUM       0x0CU
  #define PWMA_FCTRL1                   (*((volatile word *)0x0000E6CA))


  /*** PWMA_FSTS1 - Fault Status Register; 0x0000E6CB ***/
  union {
    word Word;
  } PWMA_FSTS1_STR;

  #define PWMA_FSTS1_FFLAG0_MASK        0x01U
  #define PWMA_FSTS1_FFLAG1_MASK        0x02U
  #define PWMA_FSTS1_FFLAG2_MASK        0x04U
  #define PWMA_FSTS1_FFLAG3_MASK        0x08U
  #define PWMA_FSTS1_FFULL0_MASK        0x10U
  #define PWMA_FSTS1_FFULL1_MASK        0x20U
  #define PWMA_FSTS1_FFULL2_MASK        0x40U
  #define PWMA_FSTS1_FFULL3_MASK        0x80U
  #define PWMA_FSTS1_FFPIN0_MASK        0x0100U
  #define PWMA_FSTS1_FFPIN1_MASK        0x0200U
  #define PWMA_FSTS1_FFPIN2_MASK        0x0400U
  #define PWMA_FSTS1_FFPIN3_MASK        0x0800U
  #define PWMA_FSTS1_FHALF0_MASK        0x1000U
  #define PWMA_FSTS1_FHALF1_MASK        0x2000U
  #define PWMA_FSTS1_FHALF2_MASK        0x4000U
  #define PWMA_FSTS1_FHALF3_MASK        0x8000U
  #define PWMA_FSTS1_FFLAG_MASK         0x0FU
  #define PWMA_FSTS1_FFLAG_BITNUM       0x00U
  #define PWMA_FSTS1_FFULL_MASK         0xF0U
  #define PWMA_FSTS1_FFULL_BITNUM       0x04U
  #define PWMA_FSTS1_FFPIN_MASK         0x0F00U
  #define PWMA_FSTS1_FFPIN_BITNUM       0x08U
  #define PWMA_FSTS1_FHALF_MASK         0xF000U
  #define PWMA_FSTS1_FHALF_BITNUM       0x0CU
  #define PWMA_FSTS1                    (*((volatile word *)0x0000E6CB))


  /*** PWMA_FFILT1 - Fault Filter Register; 0x0000E6CC ***/
  union {
    word Word;
  } PWMA_FFILT1_STR;

  #define PWMA_FFILT1_FILT_PER0_MASK    0x01U
  #define PWMA_FFILT1_FILT_PER1_MASK    0x02U
  #define PWMA_FFILT1_FILT_PER2_MASK    0x04U
  #define PWMA_FFILT1_FILT_PER3_MASK    0x08U
  #define PWMA_FFILT1_FILT_PER4_MASK    0x10U
  #define PWMA_FFILT1_FILT_PER5_MASK    0x20U
  #define PWMA_FFILT1_FILT_PER6_MASK    0x40U
  #define PWMA_FFILT1_FILT_PER7_MASK    0x80U
  #define PWMA_FFILT1_FILT_CNT0_MASK    0x0100U
  #define PWMA_FFILT1_FILT_CNT1_MASK    0x0200U
  #define PWMA_FFILT1_FILT_CNT2_MASK    0x0400U
  #define PWMA_FFILT1_GSTR_MASK         0x8000U
  #define PWMA_FFILT1_FILT_PER_MASK     0xFFU
  #define PWMA_FFILT1_FILT_PER_BITNUM   0x00U
  #define PWMA_FFILT1_FILT_CNT_MASK     0x0700U
  #define PWMA_FFILT1_FILT_CNT_BITNUM   0x08U
  #define PWMA_FFILT1                   (*((volatile word *)0x0000E6CC))


  /*** PWMA_FTST1 - Fault Test Register; 0x0000E6CD ***/
  union {
    word Word;
  } PWMA_FTST1_STR;

  #define PWMA_FTST1_FTEST_MASK         0x01U
  #define PWMA_FTST1                    (*((volatile word *)0x0000E6CD))


} PWMA_PRPH;
/******************************************
*** Peripheral PWMB
*******************************************/
typedef volatile struct {
  /*** PWMB_SM0CNT - Counter Register; 0x0000E700 ***/
  union {
    word Word;
  } PWMB_SM0CNT_STR;

  #define PWMB_SM0CNT                   (*((volatile word *)0x0000E700))


  /*** PWMB_SM0INIT - Initial Count Register; 0x0000E701 ***/
  union {
    word Word;
  } PWMB_SM0INIT_STR;

  #define PWMB_SM0INIT                  (*((volatile word *)0x0000E701))


  /*** PWMB_SM0CTRL2 - Control 2 Register; 0x0000E702 ***/
  union {
    word Word;
  } PWMB_SM0CTRL2_STR;

  #define PWMB_SM0CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMB_SM0CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMB_SM0CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMB_SM0CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMB_SM0CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMB_SM0CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMB_SM0CTRL2_FORCE_MASK      0x40U
  #define PWMB_SM0CTRL2_FRCEN_MASK      0x80U
  #define PWMB_SM0CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMB_SM0CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMB_SM0CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMB_SM0CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMB_SM0CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMB_SM0CTRL2_INDEP_MASK      0x2000U
  #define PWMB_SM0CTRL2_WAITEN_MASK     0x4000U
  #define PWMB_SM0CTRL2_DBGEN_MASK      0x8000U
  #define PWMB_SM0CTRL2_CLK_SEL_MASK    0x03U
  #define PWMB_SM0CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMB_SM0CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMB_SM0CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMB_SM0CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMB_SM0CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMB_SM0CTRL2                 (*((volatile word *)0x0000E702))


  /*** PWMB_SM0CTRL - Control Register; 0x0000E703 ***/
  union {
    word Word;
  } PWMB_SM0CTRL_STR;

  #define PWMB_SM0CTRL_DBLEN_MASK       0x01U
  #define PWMB_SM0CTRL_DBLX_MASK        0x02U
  #define PWMB_SM0CTRL_LDMOD_MASK       0x04U
  #define PWMB_SM0CTRL_PRSC0_MASK       0x10U
  #define PWMB_SM0CTRL_PRSC1_MASK       0x20U
  #define PWMB_SM0CTRL_PRSC2_MASK       0x40U
  #define PWMB_SM0CTRL_DT0_MASK         0x0100U
  #define PWMB_SM0CTRL_DT1_MASK         0x0200U
  #define PWMB_SM0CTRL_FULL_MASK        0x0400U
  #define PWMB_SM0CTRL_HALF_MASK        0x0800U
  #define PWMB_SM0CTRL_LDFQ0_MASK       0x1000U
  #define PWMB_SM0CTRL_LDFQ1_MASK       0x2000U
  #define PWMB_SM0CTRL_LDFQ2_MASK       0x4000U
  #define PWMB_SM0CTRL_LDFQ3_MASK       0x8000U
  #define PWMB_SM0CTRL_PRSC_MASK        0x70U
  #define PWMB_SM0CTRL_PRSC_BITNUM      0x04U
  #define PWMB_SM0CTRL_DT_MASK          0x0300U
  #define PWMB_SM0CTRL_DT_BITNUM        0x08U
  #define PWMB_SM0CTRL_LDFQ_MASK        0xF000U
  #define PWMB_SM0CTRL_LDFQ_BITNUM      0x0CU
  #define PWMB_SM0CTRL                  (*((volatile word *)0x0000E703))


  word Reserved0[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL0 - Value Register 0; 0x0000E705 ***/
  union {
    word Word;
  } PWMB_SM0VAL0_STR;

  #define PWMB_SM0VAL0                  (*((volatile word *)0x0000E705))


  word Reserved1[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL1 - Value Register 1; 0x0000E707 ***/
  union {
    word Word;
  } PWMB_SM0VAL1_STR;

  #define PWMB_SM0VAL1                  (*((volatile word *)0x0000E707))


  word Reserved2[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL2 - Value Register 2; 0x0000E709 ***/
  union {
    word Word;
  } PWMB_SM0VAL2_STR;

  #define PWMB_SM0VAL2                  (*((volatile word *)0x0000E709))


  word Reserved3[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL3 - Value Register 3; 0x0000E70B ***/
  union {
    word Word;
  } PWMB_SM0VAL3_STR;

  #define PWMB_SM0VAL3                  (*((volatile word *)0x0000E70B))


  word Reserved4[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL4 - Value Register 4; 0x0000E70D ***/
  union {
    word Word;
  } PWMB_SM0VAL4_STR;

  #define PWMB_SM0VAL4                  (*((volatile word *)0x0000E70D))


  word Reserved5[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0VAL5 - Value Register 5; 0x0000E70F ***/
  union {
    word Word;
  } PWMB_SM0VAL5_STR;

  #define PWMB_SM0VAL5                  (*((volatile word *)0x0000E70F))


  word Reserved6[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM0OCTRL - Output Control Register; 0x0000E711 ***/
  union {
    word Word;
  } PWMB_SM0OCTRL_STR;

  #define PWMB_SM0OCTRL_PWMXFS0_MASK    0x01U
  #define PWMB_SM0OCTRL_PWMXFS1_MASK    0x02U
  #define PWMB_SM0OCTRL_PWMBFS0_MASK    0x04U
  #define PWMB_SM0OCTRL_PWMBFS1_MASK    0x08U
  #define PWMB_SM0OCTRL_PWMAFS0_MASK    0x10U
  #define PWMB_SM0OCTRL_PWMAFS1_MASK    0x20U
  #define PWMB_SM0OCTRL_POLX_MASK       0x0100U
  #define PWMB_SM0OCTRL_POLB_MASK       0x0200U
  #define PWMB_SM0OCTRL_POLA_MASK       0x0400U
  #define PWMB_SM0OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMB_SM0OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMB_SM0OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMB_SM0OCTRL_PWMXFS_MASK     0x03U
  #define PWMB_SM0OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMB_SM0OCTRL_PWMBFS_MASK     0x0CU
  #define PWMB_SM0OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMB_SM0OCTRL_PWMAFS_MASK     0x30U
  #define PWMB_SM0OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMB_SM0OCTRL                 (*((volatile word *)0x0000E711))


  /*** PWMB_SM0STS - Status Register; 0x0000E712 ***/
  union {
    word Word;
  } PWMB_SM0STS_STR;

  #define PWMB_SM0STS_CMPF0_MASK        0x01U
  #define PWMB_SM0STS_CMPF1_MASK        0x02U
  #define PWMB_SM0STS_CMPF2_MASK        0x04U
  #define PWMB_SM0STS_CMPF3_MASK        0x08U
  #define PWMB_SM0STS_CMPF4_MASK        0x10U
  #define PWMB_SM0STS_CMPF5_MASK        0x20U
  #define PWMB_SM0STS_CFX0_MASK         0x40U
  #define PWMB_SM0STS_CFX1_MASK         0x80U
  #define PWMB_SM0STS_CFB0_MASK         0x0100U
  #define PWMB_SM0STS_CFB1_MASK         0x0200U
  #define PWMB_SM0STS_CFA0_MASK         0x0400U
  #define PWMB_SM0STS_CFA1_MASK         0x0800U
  #define PWMB_SM0STS_RF_MASK           0x1000U
  #define PWMB_SM0STS_REF_MASK          0x2000U
  #define PWMB_SM0STS_RUF_MASK          0x4000U
  #define PWMB_SM0STS_CMPF_MASK         0x3FU
  #define PWMB_SM0STS_CMPF_BITNUM       0x00U
  #define PWMB_SM0STS                   (*((volatile word *)0x0000E712))


  /*** PWMB_SM0INTEN - Interrupt Enable Register; 0x0000E713 ***/
  union {
    word Word;
  } PWMB_SM0INTEN_STR;

  #define PWMB_SM0INTEN_CMPIE0_MASK     0x01U
  #define PWMB_SM0INTEN_CMPIE1_MASK     0x02U
  #define PWMB_SM0INTEN_CMPIE2_MASK     0x04U
  #define PWMB_SM0INTEN_CMPIE3_MASK     0x08U
  #define PWMB_SM0INTEN_CMPIE4_MASK     0x10U
  #define PWMB_SM0INTEN_CMPIE5_MASK     0x20U
  #define PWMB_SM0INTEN_CX0IE_MASK      0x40U
  #define PWMB_SM0INTEN_CX1IE_MASK      0x80U
  #define PWMB_SM0INTEN_CB0IE_MASK      0x0100U
  #define PWMB_SM0INTEN_CB1IE_MASK      0x0200U
  #define PWMB_SM0INTEN_CA0IE_MASK      0x0400U
  #define PWMB_SM0INTEN_CA1IE_MASK      0x0800U
  #define PWMB_SM0INTEN_RIE_MASK        0x1000U
  #define PWMB_SM0INTEN_REIE_MASK       0x2000U
  #define PWMB_SM0INTEN_CMPIE_MASK      0x3FU
  #define PWMB_SM0INTEN_CMPIE_BITNUM    0x00U
  #define PWMB_SM0INTEN                 (*((volatile word *)0x0000E713))


  /*** PWMB_SM0DMAEN - DMA Enable Register; 0x0000E714 ***/
  union {
    word Word;
  } PWMB_SM0DMAEN_STR;

  #define PWMB_SM0DMAEN_CX0DE_MASK      0x01U
  #define PWMB_SM0DMAEN_CX1DE_MASK      0x02U
  #define PWMB_SM0DMAEN_CB0DE_MASK      0x04U
  #define PWMB_SM0DMAEN_CB1DE_MASK      0x08U
  #define PWMB_SM0DMAEN_CA0DE_MASK      0x10U
  #define PWMB_SM0DMAEN_CA1DE_MASK      0x20U
  #define PWMB_SM0DMAEN_CAPTDE0_MASK    0x40U
  #define PWMB_SM0DMAEN_CAPTDE1_MASK    0x80U
  #define PWMB_SM0DMAEN_FAND_MASK       0x0100U
  #define PWMB_SM0DMAEN_VALDE_MASK      0x0200U
  #define PWMB_SM0DMAEN_CAPTDE_MASK     0xC0U
  #define PWMB_SM0DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMB_SM0DMAEN                 (*((volatile word *)0x0000E714))


  /*** PWMB_SM0TCTRL - Output Trigger Control Register; 0x0000E715 ***/
  union {
    word Word;
  } PWMB_SM0TCTRL_STR;

  #define PWMB_SM0TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMB_SM0TCTRL_PWBOT1_MASK     0x4000U
  #define PWMB_SM0TCTRL_PWAOT0_MASK     0x8000U
  #define PWMB_SM0TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMB_SM0TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMB_SM0TCTRL                 (*((volatile word *)0x0000E715))


  /*** PWMB_SM0DISMAP0 - Fault Disable Mapping Register 0; 0x0000E716 ***/
  union {
    word Word;
  } PWMB_SM0DISMAP0_STR;

  #define PWMB_SM0DISMAP0_DIS0A0_MASK   0x01U
  #define PWMB_SM0DISMAP0_DIS0A1_MASK   0x02U
  #define PWMB_SM0DISMAP0_DIS0A2_MASK   0x04U
  #define PWMB_SM0DISMAP0_DIS0A3_MASK   0x08U
  #define PWMB_SM0DISMAP0_DIS0B0_MASK   0x10U
  #define PWMB_SM0DISMAP0_DIS0B1_MASK   0x20U
  #define PWMB_SM0DISMAP0_DIS0B2_MASK   0x40U
  #define PWMB_SM0DISMAP0_DIS0B3_MASK   0x80U
  #define PWMB_SM0DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMB_SM0DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMB_SM0DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMB_SM0DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMB_SM0DISMAP0_DIS0A_MASK    0x0FU
  #define PWMB_SM0DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMB_SM0DISMAP0_DIS0B_MASK    0xF0U
  #define PWMB_SM0DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMB_SM0DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMB_SM0DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMB_SM0DISMAP0               (*((volatile word *)0x0000E716))


  /*** PWMB_SM0DISMAP1 - Fault Disable Mapping Register 1; 0x0000E717 ***/
  union {
    word Word;
  } PWMB_SM0DISMAP1_STR;

  #define PWMB_SM0DISMAP1_DIS1A0_MASK   0x01U
  #define PWMB_SM0DISMAP1_DIS1A1_MASK   0x02U
  #define PWMB_SM0DISMAP1_DIS1A2_MASK   0x04U
  #define PWMB_SM0DISMAP1_DIS1A3_MASK   0x08U
  #define PWMB_SM0DISMAP1_DIS1B0_MASK   0x10U
  #define PWMB_SM0DISMAP1_DIS1B1_MASK   0x20U
  #define PWMB_SM0DISMAP1_DIS1B2_MASK   0x40U
  #define PWMB_SM0DISMAP1_DIS1B3_MASK   0x80U
  #define PWMB_SM0DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMB_SM0DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMB_SM0DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMB_SM0DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMB_SM0DISMAP1_DIS1A_MASK    0x0FU
  #define PWMB_SM0DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMB_SM0DISMAP1_DIS1B_MASK    0xF0U
  #define PWMB_SM0DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMB_SM0DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMB_SM0DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMB_SM0DISMAP1               (*((volatile word *)0x0000E717))


  /*** PWMB_SM0DTCNT0 - Deadtime Count Register 0; 0x0000E718 ***/
  union {
    word Word;
  } PWMB_SM0DTCNT0_STR;

  #define PWMB_SM0DTCNT0_DTCNT00_MASK   0x01U
  #define PWMB_SM0DTCNT0_DTCNT01_MASK   0x02U
  #define PWMB_SM0DTCNT0_DTCNT02_MASK   0x04U
  #define PWMB_SM0DTCNT0_DTCNT03_MASK   0x08U
  #define PWMB_SM0DTCNT0_DTCNT04_MASK   0x10U
  #define PWMB_SM0DTCNT0_DTCNT05_MASK   0x20U
  #define PWMB_SM0DTCNT0_DTCNT06_MASK   0x40U
  #define PWMB_SM0DTCNT0_DTCNT07_MASK   0x80U
  #define PWMB_SM0DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMB_SM0DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMB_SM0DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMB_SM0DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMB_SM0DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMB_SM0DTCNT0                (*((volatile word *)0x0000E718))


  /*** PWMB_SM0DTCNT1 - Deadtime Count Register 1; 0x0000E719 ***/
  union {
    word Word;
  } PWMB_SM0DTCNT1_STR;

  #define PWMB_SM0DTCNT1_DTCNT10_MASK   0x01U
  #define PWMB_SM0DTCNT1_DTCNT11_MASK   0x02U
  #define PWMB_SM0DTCNT1_DTCNT12_MASK   0x04U
  #define PWMB_SM0DTCNT1_DTCNT13_MASK   0x08U
  #define PWMB_SM0DTCNT1_DTCNT14_MASK   0x10U
  #define PWMB_SM0DTCNT1_DTCNT15_MASK   0x20U
  #define PWMB_SM0DTCNT1_DTCNT16_MASK   0x40U
  #define PWMB_SM0DTCNT1_DTCNT17_MASK   0x80U
  #define PWMB_SM0DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMB_SM0DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMB_SM0DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMB_SM0DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMB_SM0DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMB_SM0DTCNT1                (*((volatile word *)0x0000E719))


  /*** PWMB_SM0CAPTCTRLA - Capture Control A Register; 0x0000E71A ***/
  union {
    word Word;
  } PWMB_SM0CAPTCTRLA_STR;

  #define PWMB_SM0CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMB_SM0CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMB_SM0CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMB_SM0CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMB_SM0CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMB_SM0CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMB_SM0CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMB_SM0CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMB_SM0CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMB_SM0CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMB_SM0CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMB_SM0CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMB_SM0CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMB_SM0CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMB_SM0CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMB_SM0CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMB_SM0CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMB_SM0CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMB_SM0CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMB_SM0CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMB_SM0CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMB_SM0CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMB_SM0CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMB_SM0CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMB_SM0CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMB_SM0CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMB_SM0CAPTCTRLA             (*((volatile word *)0x0000E71A))


  /*** PWMB_SM0CAPTCOMPA - Capture Compare A Register; 0x0000E71B ***/
  union {
    word Word;
  } PWMB_SM0CAPTCOMPA_STR;

  #define PWMB_SM0CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMB_SM0CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMB_SM0CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMB_SM0CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMB_SM0CAPTCOMPA             (*((volatile word *)0x0000E71B))


  /*** PWMB_SM0CAPTCTRLB - Capture Control B Register; 0x0000E71C ***/
  union {
    word Word;
  } PWMB_SM0CAPTCTRLB_STR;

  #define PWMB_SM0CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMB_SM0CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMB_SM0CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMB_SM0CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMB_SM0CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMB_SM0CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMB_SM0CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMB_SM0CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMB_SM0CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMB_SM0CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMB_SM0CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMB_SM0CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMB_SM0CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMB_SM0CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMB_SM0CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMB_SM0CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMB_SM0CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMB_SM0CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMB_SM0CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMB_SM0CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMB_SM0CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMB_SM0CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMB_SM0CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMB_SM0CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMB_SM0CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMB_SM0CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMB_SM0CAPTCTRLB             (*((volatile word *)0x0000E71C))


  /*** PWMB_SM0CAPTCOMPB - Capture Compare B Register; 0x0000E71D ***/
  union {
    word Word;
  } PWMB_SM0CAPTCOMPB_STR;

  #define PWMB_SM0CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMB_SM0CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMB_SM0CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMB_SM0CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMB_SM0CAPTCOMPB             (*((volatile word *)0x0000E71D))


  /*** PWMB_SM0CAPTCTRLX - Capture Control X Register; 0x0000E71E ***/
  union {
    word Word;
  } PWMB_SM0CAPTCTRLX_STR;

  #define PWMB_SM0CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMB_SM0CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMB_SM0CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMB_SM0CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMB_SM0CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMB_SM0CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMB_SM0CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMB_SM0CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMB_SM0CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMB_SM0CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMB_SM0CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMB_SM0CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMB_SM0CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMB_SM0CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMB_SM0CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMB_SM0CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMB_SM0CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMB_SM0CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMB_SM0CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMB_SM0CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMB_SM0CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMB_SM0CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMB_SM0CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMB_SM0CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMB_SM0CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMB_SM0CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMB_SM0CAPTCTRLX             (*((volatile word *)0x0000E71E))


  /*** PWMB_SM0CAPTCOMPX - Capture Compare X Register; 0x0000E71F ***/
  union {
    word Word;
  } PWMB_SM0CAPTCOMPX_STR;

  #define PWMB_SM0CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMB_SM0CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMB_SM0CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMB_SM0CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMB_SM0CAPTCOMPX             (*((volatile word *)0x0000E71F))


  /*** PWMB_SM0CVAL0 - Capture Value 0 Register; 0x0000E720 ***/
  union {
    word Word;
  } PWMB_SM0CVAL0_STR;

  #define PWMB_SM0CVAL0                 (*((volatile word *)0x0000E720))


  /*** PWMB_SM0CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E721 ***/
  union {
    word Word;
  } PWMB_SM0CVAL0CYC_STR;

  #define PWMB_SM0CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMB_SM0CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMB_SM0CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMB_SM0CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMB_SM0CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMB_SM0CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL0CYC              (*((volatile word *)0x0000E721))


  /*** PWMB_SM0CVAL1 - Capture Value 1 Register; 0x0000E722 ***/
  union {
    word Word;
  } PWMB_SM0CVAL1_STR;

  #define PWMB_SM0CVAL1                 (*((volatile word *)0x0000E722))


  /*** PWMB_SM0CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E723 ***/
  union {
    word Word;
  } PWMB_SM0CVAL1CYC_STR;

  #define PWMB_SM0CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMB_SM0CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMB_SM0CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMB_SM0CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMB_SM0CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMB_SM0CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL1CYC              (*((volatile word *)0x0000E723))


  /*** PWMB_SM0CVAL2 - Capture Value 2 Register; 0x0000E724 ***/
  union {
    word Word;
  } PWMB_SM0CVAL2_STR;

  #define PWMB_SM0CVAL2                 (*((volatile word *)0x0000E724))


  /*** PWMB_SM0CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E725 ***/
  union {
    word Word;
  } PWMB_SM0CVAL2CYC_STR;

  #define PWMB_SM0CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMB_SM0CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMB_SM0CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMB_SM0CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMB_SM0CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMB_SM0CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL2CYC              (*((volatile word *)0x0000E725))


  /*** PWMB_SM0CVAL3 - Capture Value 3 Register; 0x0000E726 ***/
  union {
    word Word;
  } PWMB_SM0CVAL3_STR;

  #define PWMB_SM0CVAL3                 (*((volatile word *)0x0000E726))


  /*** PWMB_SM0CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E727 ***/
  union {
    word Word;
  } PWMB_SM0CVAL3CYC_STR;

  #define PWMB_SM0CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMB_SM0CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMB_SM0CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMB_SM0CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMB_SM0CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMB_SM0CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL3CYC              (*((volatile word *)0x0000E727))


  /*** PWMB_SM0CVAL4 - Capture Value 4 Register; 0x0000E728 ***/
  union {
    word Word;
  } PWMB_SM0CVAL4_STR;

  #define PWMB_SM0CVAL4                 (*((volatile word *)0x0000E728))


  /*** PWMB_SM0CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E729 ***/
  union {
    word Word;
  } PWMB_SM0CVAL4CYC_STR;

  #define PWMB_SM0CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMB_SM0CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMB_SM0CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMB_SM0CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMB_SM0CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMB_SM0CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL4CYC              (*((volatile word *)0x0000E729))


  /*** PWMB_SM0CVAL5 - Capture Value 5 Register; 0x0000E72A ***/
  union {
    word Word;
  } PWMB_SM0CVAL5_STR;

  #define PWMB_SM0CVAL5                 (*((volatile word *)0x0000E72A))


  /*** PWMB_SM0CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E72B ***/
  union {
    word Word;
  } PWMB_SM0CVAL5CYC_STR;

  #define PWMB_SM0CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMB_SM0CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMB_SM0CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMB_SM0CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMB_SM0CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMB_SM0CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMB_SM0CVAL5CYC              (*((volatile word *)0x0000E72B))


  word Reserved7[4];                   /* Reserved (unused) registers */

  /*** PWMB_SM1CNT - Counter Register; 0x0000E730 ***/
  union {
    word Word;
  } PWMB_SM1CNT_STR;

  #define PWMB_SM1CNT                   (*((volatile word *)0x0000E730))


  /*** PWMB_SM1INIT - Initial Count Register; 0x0000E731 ***/
  union {
    word Word;
  } PWMB_SM1INIT_STR;

  #define PWMB_SM1INIT                  (*((volatile word *)0x0000E731))


  /*** PWMB_SM1CTRL2 - Control 2 Register; 0x0000E732 ***/
  union {
    word Word;
  } PWMB_SM1CTRL2_STR;

  #define PWMB_SM1CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMB_SM1CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMB_SM1CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMB_SM1CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMB_SM1CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMB_SM1CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMB_SM1CTRL2_FORCE_MASK      0x40U
  #define PWMB_SM1CTRL2_FRCEN_MASK      0x80U
  #define PWMB_SM1CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMB_SM1CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMB_SM1CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMB_SM1CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMB_SM1CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMB_SM1CTRL2_INDEP_MASK      0x2000U
  #define PWMB_SM1CTRL2_WAITEN_MASK     0x4000U
  #define PWMB_SM1CTRL2_DBGEN_MASK      0x8000U
  #define PWMB_SM1CTRL2_CLK_SEL_MASK    0x03U
  #define PWMB_SM1CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMB_SM1CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMB_SM1CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMB_SM1CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMB_SM1CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMB_SM1CTRL2                 (*((volatile word *)0x0000E732))


  /*** PWMB_SM1CTRL - Control Register; 0x0000E733 ***/
  union {
    word Word;
  } PWMB_SM1CTRL_STR;

  #define PWMB_SM1CTRL_DBLEN_MASK       0x01U
  #define PWMB_SM1CTRL_DBLX_MASK        0x02U
  #define PWMB_SM1CTRL_LDMOD_MASK       0x04U
  #define PWMB_SM1CTRL_PRSC0_MASK       0x10U
  #define PWMB_SM1CTRL_PRSC1_MASK       0x20U
  #define PWMB_SM1CTRL_PRSC2_MASK       0x40U
  #define PWMB_SM1CTRL_DT0_MASK         0x0100U
  #define PWMB_SM1CTRL_DT1_MASK         0x0200U
  #define PWMB_SM1CTRL_FULL_MASK        0x0400U
  #define PWMB_SM1CTRL_HALF_MASK        0x0800U
  #define PWMB_SM1CTRL_LDFQ0_MASK       0x1000U
  #define PWMB_SM1CTRL_LDFQ1_MASK       0x2000U
  #define PWMB_SM1CTRL_LDFQ2_MASK       0x4000U
  #define PWMB_SM1CTRL_LDFQ3_MASK       0x8000U
  #define PWMB_SM1CTRL_PRSC_MASK        0x70U
  #define PWMB_SM1CTRL_PRSC_BITNUM      0x04U
  #define PWMB_SM1CTRL_DT_MASK          0x0300U
  #define PWMB_SM1CTRL_DT_BITNUM        0x08U
  #define PWMB_SM1CTRL_LDFQ_MASK        0xF000U
  #define PWMB_SM1CTRL_LDFQ_BITNUM      0x0CU
  #define PWMB_SM1CTRL                  (*((volatile word *)0x0000E733))


  word Reserved8[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM1VAL0 - Value Register 0; 0x0000E735 ***/
  union {
    word Word;
  } PWMB_SM1VAL0_STR;

  #define PWMB_SM1VAL0                  (*((volatile word *)0x0000E735))


  word Reserved9[1];                   /* Reserved (unused) registers */

  /*** PWMB_SM1VAL1 - Value Register 1; 0x0000E737 ***/
  union {
    word Word;
  } PWMB_SM1VAL1_STR;

  #define PWMB_SM1VAL1                  (*((volatile word *)0x0000E737))


  word Reserved10[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM1VAL2 - Value Register 2; 0x0000E739 ***/
  union {
    word Word;
  } PWMB_SM1VAL2_STR;

  #define PWMB_SM1VAL2                  (*((volatile word *)0x0000E739))


  word Reserved11[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM1VAL3 - Value Register 3; 0x0000E73B ***/
  union {
    word Word;
  } PWMB_SM1VAL3_STR;

  #define PWMB_SM1VAL3                  (*((volatile word *)0x0000E73B))


  word Reserved12[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM1VAL4 - Value Register 4; 0x0000E73D ***/
  union {
    word Word;
  } PWMB_SM1VAL4_STR;

  #define PWMB_SM1VAL4                  (*((volatile word *)0x0000E73D))


  word Reserved13[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM1VAL5 - Value Register 5; 0x0000E73F ***/
  union {
    word Word;
  } PWMB_SM1VAL5_STR;

  #define PWMB_SM1VAL5                  (*((volatile word *)0x0000E73F))


  word Reserved14[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM1OCTRL - Output Control Register; 0x0000E741 ***/
  union {
    word Word;
  } PWMB_SM1OCTRL_STR;

  #define PWMB_SM1OCTRL_PWMXFS0_MASK    0x01U
  #define PWMB_SM1OCTRL_PWMXFS1_MASK    0x02U
  #define PWMB_SM1OCTRL_PWMBFS0_MASK    0x04U
  #define PWMB_SM1OCTRL_PWMBFS1_MASK    0x08U
  #define PWMB_SM1OCTRL_PWMAFS0_MASK    0x10U
  #define PWMB_SM1OCTRL_PWMAFS1_MASK    0x20U
  #define PWMB_SM1OCTRL_POLX_MASK       0x0100U
  #define PWMB_SM1OCTRL_POLB_MASK       0x0200U
  #define PWMB_SM1OCTRL_POLA_MASK       0x0400U
  #define PWMB_SM1OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMB_SM1OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMB_SM1OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMB_SM1OCTRL_PWMXFS_MASK     0x03U
  #define PWMB_SM1OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMB_SM1OCTRL_PWMBFS_MASK     0x0CU
  #define PWMB_SM1OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMB_SM1OCTRL_PWMAFS_MASK     0x30U
  #define PWMB_SM1OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMB_SM1OCTRL                 (*((volatile word *)0x0000E741))


  /*** PWMB_SM1STS - Status Register; 0x0000E742 ***/
  union {
    word Word;
  } PWMB_SM1STS_STR;

  #define PWMB_SM1STS_CMPF0_MASK        0x01U
  #define PWMB_SM1STS_CMPF1_MASK        0x02U
  #define PWMB_SM1STS_CMPF2_MASK        0x04U
  #define PWMB_SM1STS_CMPF3_MASK        0x08U
  #define PWMB_SM1STS_CMPF4_MASK        0x10U
  #define PWMB_SM1STS_CMPF5_MASK        0x20U
  #define PWMB_SM1STS_CFX0_MASK         0x40U
  #define PWMB_SM1STS_CFX1_MASK         0x80U
  #define PWMB_SM1STS_CFB0_MASK         0x0100U
  #define PWMB_SM1STS_CFB1_MASK         0x0200U
  #define PWMB_SM1STS_CFA0_MASK         0x0400U
  #define PWMB_SM1STS_CFA1_MASK         0x0800U
  #define PWMB_SM1STS_RF_MASK           0x1000U
  #define PWMB_SM1STS_REF_MASK          0x2000U
  #define PWMB_SM1STS_RUF_MASK          0x4000U
  #define PWMB_SM1STS_CMPF_MASK         0x3FU
  #define PWMB_SM1STS_CMPF_BITNUM       0x00U
  #define PWMB_SM1STS                   (*((volatile word *)0x0000E742))


  /*** PWMB_SM1INTEN - Interrupt Enable Register; 0x0000E743 ***/
  union {
    word Word;
  } PWMB_SM1INTEN_STR;

  #define PWMB_SM1INTEN_CMPIE0_MASK     0x01U
  #define PWMB_SM1INTEN_CMPIE1_MASK     0x02U
  #define PWMB_SM1INTEN_CMPIE2_MASK     0x04U
  #define PWMB_SM1INTEN_CMPIE3_MASK     0x08U
  #define PWMB_SM1INTEN_CMPIE4_MASK     0x10U
  #define PWMB_SM1INTEN_CMPIE5_MASK     0x20U
  #define PWMB_SM1INTEN_CX0IE_MASK      0x40U
  #define PWMB_SM1INTEN_CX1IE_MASK      0x80U
  #define PWMB_SM1INTEN_CB0IE_MASK      0x0100U
  #define PWMB_SM1INTEN_CB1IE_MASK      0x0200U
  #define PWMB_SM1INTEN_CA0IE_MASK      0x0400U
  #define PWMB_SM1INTEN_CA1IE_MASK      0x0800U
  #define PWMB_SM1INTEN_RIE_MASK        0x1000U
  #define PWMB_SM1INTEN_REIE_MASK       0x2000U
  #define PWMB_SM1INTEN_CMPIE_MASK      0x3FU
  #define PWMB_SM1INTEN_CMPIE_BITNUM    0x00U
  #define PWMB_SM1INTEN                 (*((volatile word *)0x0000E743))


  /*** PWMB_SM1DMAEN - DMA Enable Register; 0x0000E744 ***/
  union {
    word Word;
  } PWMB_SM1DMAEN_STR;

  #define PWMB_SM1DMAEN_CX0DE_MASK      0x01U
  #define PWMB_SM1DMAEN_CX1DE_MASK      0x02U
  #define PWMB_SM1DMAEN_CB0DE_MASK      0x04U
  #define PWMB_SM1DMAEN_CB1DE_MASK      0x08U
  #define PWMB_SM1DMAEN_CA0DE_MASK      0x10U
  #define PWMB_SM1DMAEN_CA1DE_MASK      0x20U
  #define PWMB_SM1DMAEN_CAPTDE0_MASK    0x40U
  #define PWMB_SM1DMAEN_CAPTDE1_MASK    0x80U
  #define PWMB_SM1DMAEN_FAND_MASK       0x0100U
  #define PWMB_SM1DMAEN_VALDE_MASK      0x0200U
  #define PWMB_SM1DMAEN_CAPTDE_MASK     0xC0U
  #define PWMB_SM1DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMB_SM1DMAEN                 (*((volatile word *)0x0000E744))


  /*** PWMB_SM1TCTRL - Output Trigger Control Register; 0x0000E745 ***/
  union {
    word Word;
  } PWMB_SM1TCTRL_STR;

  #define PWMB_SM1TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMB_SM1TCTRL_PWBOT1_MASK     0x4000U
  #define PWMB_SM1TCTRL_PWAOT0_MASK     0x8000U
  #define PWMB_SM1TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMB_SM1TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMB_SM1TCTRL                 (*((volatile word *)0x0000E745))


  /*** PWMB_SM1DISMAP0 - Fault Disable Mapping Register 0; 0x0000E746 ***/
  union {
    word Word;
  } PWMB_SM1DISMAP0_STR;

  #define PWMB_SM1DISMAP0_DIS0A0_MASK   0x01U
  #define PWMB_SM1DISMAP0_DIS0A1_MASK   0x02U
  #define PWMB_SM1DISMAP0_DIS0A2_MASK   0x04U
  #define PWMB_SM1DISMAP0_DIS0A3_MASK   0x08U
  #define PWMB_SM1DISMAP0_DIS0B0_MASK   0x10U
  #define PWMB_SM1DISMAP0_DIS0B1_MASK   0x20U
  #define PWMB_SM1DISMAP0_DIS0B2_MASK   0x40U
  #define PWMB_SM1DISMAP0_DIS0B3_MASK   0x80U
  #define PWMB_SM1DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMB_SM1DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMB_SM1DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMB_SM1DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMB_SM1DISMAP0_DIS0A_MASK    0x0FU
  #define PWMB_SM1DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMB_SM1DISMAP0_DIS0B_MASK    0xF0U
  #define PWMB_SM1DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMB_SM1DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMB_SM1DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMB_SM1DISMAP0               (*((volatile word *)0x0000E746))


  /*** PWMB_SM1DISMAP1 - Fault Disable Mapping Register 1; 0x0000E747 ***/
  union {
    word Word;
  } PWMB_SM1DISMAP1_STR;

  #define PWMB_SM1DISMAP1_DIS1A0_MASK   0x01U
  #define PWMB_SM1DISMAP1_DIS1A1_MASK   0x02U
  #define PWMB_SM1DISMAP1_DIS1A2_MASK   0x04U
  #define PWMB_SM1DISMAP1_DIS1A3_MASK   0x08U
  #define PWMB_SM1DISMAP1_DIS1B0_MASK   0x10U
  #define PWMB_SM1DISMAP1_DIS1B1_MASK   0x20U
  #define PWMB_SM1DISMAP1_DIS1B2_MASK   0x40U
  #define PWMB_SM1DISMAP1_DIS1B3_MASK   0x80U
  #define PWMB_SM1DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMB_SM1DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMB_SM1DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMB_SM1DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMB_SM1DISMAP1_DIS1A_MASK    0x0FU
  #define PWMB_SM1DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMB_SM1DISMAP1_DIS1B_MASK    0xF0U
  #define PWMB_SM1DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMB_SM1DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMB_SM1DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMB_SM1DISMAP1               (*((volatile word *)0x0000E747))


  /*** PWMB_SM1DTCNT0 - Deadtime Count Register 0; 0x0000E748 ***/
  union {
    word Word;
  } PWMB_SM1DTCNT0_STR;

  #define PWMB_SM1DTCNT0_DTCNT00_MASK   0x01U
  #define PWMB_SM1DTCNT0_DTCNT01_MASK   0x02U
  #define PWMB_SM1DTCNT0_DTCNT02_MASK   0x04U
  #define PWMB_SM1DTCNT0_DTCNT03_MASK   0x08U
  #define PWMB_SM1DTCNT0_DTCNT04_MASK   0x10U
  #define PWMB_SM1DTCNT0_DTCNT05_MASK   0x20U
  #define PWMB_SM1DTCNT0_DTCNT06_MASK   0x40U
  #define PWMB_SM1DTCNT0_DTCNT07_MASK   0x80U
  #define PWMB_SM1DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMB_SM1DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMB_SM1DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMB_SM1DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMB_SM1DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMB_SM1DTCNT0                (*((volatile word *)0x0000E748))


  /*** PWMB_SM1DTCNT1 - Deadtime Count Register 1; 0x0000E749 ***/
  union {
    word Word;
  } PWMB_SM1DTCNT1_STR;

  #define PWMB_SM1DTCNT1_DTCNT10_MASK   0x01U
  #define PWMB_SM1DTCNT1_DTCNT11_MASK   0x02U
  #define PWMB_SM1DTCNT1_DTCNT12_MASK   0x04U
  #define PWMB_SM1DTCNT1_DTCNT13_MASK   0x08U
  #define PWMB_SM1DTCNT1_DTCNT14_MASK   0x10U
  #define PWMB_SM1DTCNT1_DTCNT15_MASK   0x20U
  #define PWMB_SM1DTCNT1_DTCNT16_MASK   0x40U
  #define PWMB_SM1DTCNT1_DTCNT17_MASK   0x80U
  #define PWMB_SM1DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMB_SM1DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMB_SM1DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMB_SM1DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMB_SM1DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMB_SM1DTCNT1                (*((volatile word *)0x0000E749))


  /*** PWMB_SM1CAPTCTRLA - Capture Control A Register; 0x0000E74A ***/
  union {
    word Word;
  } PWMB_SM1CAPTCTRLA_STR;

  #define PWMB_SM1CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMB_SM1CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMB_SM1CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMB_SM1CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMB_SM1CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMB_SM1CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMB_SM1CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMB_SM1CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMB_SM1CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMB_SM1CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMB_SM1CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMB_SM1CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMB_SM1CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMB_SM1CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMB_SM1CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMB_SM1CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMB_SM1CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMB_SM1CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMB_SM1CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMB_SM1CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMB_SM1CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMB_SM1CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMB_SM1CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMB_SM1CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMB_SM1CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMB_SM1CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMB_SM1CAPTCTRLA             (*((volatile word *)0x0000E74A))


  /*** PWMB_SM1CAPTCOMPA - Capture Compare A Register; 0x0000E74B ***/
  union {
    word Word;
  } PWMB_SM1CAPTCOMPA_STR;

  #define PWMB_SM1CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMB_SM1CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMB_SM1CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMB_SM1CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMB_SM1CAPTCOMPA             (*((volatile word *)0x0000E74B))


  /*** PWMB_SM1CAPTCTRLB - Capture Control B Register; 0x0000E74C ***/
  union {
    word Word;
  } PWMB_SM1CAPTCTRLB_STR;

  #define PWMB_SM1CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMB_SM1CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMB_SM1CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMB_SM1CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMB_SM1CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMB_SM1CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMB_SM1CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMB_SM1CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMB_SM1CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMB_SM1CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMB_SM1CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMB_SM1CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMB_SM1CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMB_SM1CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMB_SM1CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMB_SM1CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMB_SM1CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMB_SM1CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMB_SM1CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMB_SM1CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMB_SM1CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMB_SM1CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMB_SM1CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMB_SM1CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMB_SM1CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMB_SM1CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMB_SM1CAPTCTRLB             (*((volatile word *)0x0000E74C))


  /*** PWMB_SM1CAPTCOMPB - Capture Compare B Register; 0x0000E74D ***/
  union {
    word Word;
  } PWMB_SM1CAPTCOMPB_STR;

  #define PWMB_SM1CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMB_SM1CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMB_SM1CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMB_SM1CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMB_SM1CAPTCOMPB             (*((volatile word *)0x0000E74D))


  /*** PWMB_SM1CAPTCTRLX - Capture Control X Register; 0x0000E74E ***/
  union {
    word Word;
  } PWMB_SM1CAPTCTRLX_STR;

  #define PWMB_SM1CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMB_SM1CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMB_SM1CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMB_SM1CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMB_SM1CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMB_SM1CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMB_SM1CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMB_SM1CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMB_SM1CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMB_SM1CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMB_SM1CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMB_SM1CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMB_SM1CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMB_SM1CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMB_SM1CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMB_SM1CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMB_SM1CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMB_SM1CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMB_SM1CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMB_SM1CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMB_SM1CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMB_SM1CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMB_SM1CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMB_SM1CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMB_SM1CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMB_SM1CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMB_SM1CAPTCTRLX             (*((volatile word *)0x0000E74E))


  /*** PWMB_SM1CAPTCOMPX - Capture Compare X Register; 0x0000E74F ***/
  union {
    word Word;
  } PWMB_SM1CAPTCOMPX_STR;

  #define PWMB_SM1CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMB_SM1CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMB_SM1CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMB_SM1CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMB_SM1CAPTCOMPX             (*((volatile word *)0x0000E74F))


  /*** PWMB_SM1CVAL0 - Capture Value 0 Register; 0x0000E750 ***/
  union {
    word Word;
  } PWMB_SM1CVAL0_STR;

  #define PWMB_SM1CVAL0                 (*((volatile word *)0x0000E750))


  /*** PWMB_SM1CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E751 ***/
  union {
    word Word;
  } PWMB_SM1CVAL0CYC_STR;

  #define PWMB_SM1CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMB_SM1CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMB_SM1CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMB_SM1CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMB_SM1CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMB_SM1CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL0CYC              (*((volatile word *)0x0000E751))


  /*** PWMB_SM1CVAL1 - Capture Value 1 Register; 0x0000E752 ***/
  union {
    word Word;
  } PWMB_SM1CVAL1_STR;

  #define PWMB_SM1CVAL1                 (*((volatile word *)0x0000E752))


  /*** PWMB_SM1CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E753 ***/
  union {
    word Word;
  } PWMB_SM1CVAL1CYC_STR;

  #define PWMB_SM1CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMB_SM1CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMB_SM1CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMB_SM1CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMB_SM1CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMB_SM1CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL1CYC              (*((volatile word *)0x0000E753))


  /*** PWMB_SM1CVAL2 - Capture Value 2 Register; 0x0000E754 ***/
  union {
    word Word;
  } PWMB_SM1CVAL2_STR;

  #define PWMB_SM1CVAL2                 (*((volatile word *)0x0000E754))


  /*** PWMB_SM1CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E755 ***/
  union {
    word Word;
  } PWMB_SM1CVAL2CYC_STR;

  #define PWMB_SM1CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMB_SM1CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMB_SM1CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMB_SM1CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMB_SM1CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMB_SM1CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL2CYC              (*((volatile word *)0x0000E755))


  /*** PWMB_SM1CVAL3 - Capture Value 3 Register; 0x0000E756 ***/
  union {
    word Word;
  } PWMB_SM1CVAL3_STR;

  #define PWMB_SM1CVAL3                 (*((volatile word *)0x0000E756))


  /*** PWMB_SM1CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E757 ***/
  union {
    word Word;
  } PWMB_SM1CVAL3CYC_STR;

  #define PWMB_SM1CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMB_SM1CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMB_SM1CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMB_SM1CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMB_SM1CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMB_SM1CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL3CYC              (*((volatile word *)0x0000E757))


  /*** PWMB_SM1CVAL4 - Capture Value 4 Register; 0x0000E758 ***/
  union {
    word Word;
  } PWMB_SM1CVAL4_STR;

  #define PWMB_SM1CVAL4                 (*((volatile word *)0x0000E758))


  /*** PWMB_SM1CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E759 ***/
  union {
    word Word;
  } PWMB_SM1CVAL4CYC_STR;

  #define PWMB_SM1CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMB_SM1CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMB_SM1CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMB_SM1CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMB_SM1CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMB_SM1CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL4CYC              (*((volatile word *)0x0000E759))


  /*** PWMB_SM1CVAL5 - Capture Value 5 Register; 0x0000E75A ***/
  union {
    word Word;
  } PWMB_SM1CVAL5_STR;

  #define PWMB_SM1CVAL5                 (*((volatile word *)0x0000E75A))


  /*** PWMB_SM1CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E75B ***/
  union {
    word Word;
  } PWMB_SM1CVAL5CYC_STR;

  #define PWMB_SM1CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMB_SM1CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMB_SM1CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMB_SM1CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMB_SM1CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMB_SM1CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMB_SM1CVAL5CYC              (*((volatile word *)0x0000E75B))


  word Reserved15[4];                  /* Reserved (unused) registers */

  /*** PWMB_SM2CNT - Counter Register; 0x0000E760 ***/
  union {
    word Word;
  } PWMB_SM2CNT_STR;

  #define PWMB_SM2CNT                   (*((volatile word *)0x0000E760))


  /*** PWMB_SM2INIT - Initial Count Register; 0x0000E761 ***/
  union {
    word Word;
  } PWMB_SM2INIT_STR;

  #define PWMB_SM2INIT                  (*((volatile word *)0x0000E761))


  /*** PWMB_SM2CTRL2 - Control 2 Register; 0x0000E762 ***/
  union {
    word Word;
  } PWMB_SM2CTRL2_STR;

  #define PWMB_SM2CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMB_SM2CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMB_SM2CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMB_SM2CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMB_SM2CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMB_SM2CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMB_SM2CTRL2_FORCE_MASK      0x40U
  #define PWMB_SM2CTRL2_FRCEN_MASK      0x80U
  #define PWMB_SM2CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMB_SM2CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMB_SM2CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMB_SM2CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMB_SM2CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMB_SM2CTRL2_INDEP_MASK      0x2000U
  #define PWMB_SM2CTRL2_WAITEN_MASK     0x4000U
  #define PWMB_SM2CTRL2_DBGEN_MASK      0x8000U
  #define PWMB_SM2CTRL2_CLK_SEL_MASK    0x03U
  #define PWMB_SM2CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMB_SM2CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMB_SM2CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMB_SM2CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMB_SM2CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMB_SM2CTRL2                 (*((volatile word *)0x0000E762))


  /*** PWMB_SM2CTRL - Control Register; 0x0000E763 ***/
  union {
    word Word;
  } PWMB_SM2CTRL_STR;

  #define PWMB_SM2CTRL_DBLEN_MASK       0x01U
  #define PWMB_SM2CTRL_DBLX_MASK        0x02U
  #define PWMB_SM2CTRL_LDMOD_MASK       0x04U
  #define PWMB_SM2CTRL_PRSC0_MASK       0x10U
  #define PWMB_SM2CTRL_PRSC1_MASK       0x20U
  #define PWMB_SM2CTRL_PRSC2_MASK       0x40U
  #define PWMB_SM2CTRL_DT0_MASK         0x0100U
  #define PWMB_SM2CTRL_DT1_MASK         0x0200U
  #define PWMB_SM2CTRL_FULL_MASK        0x0400U
  #define PWMB_SM2CTRL_HALF_MASK        0x0800U
  #define PWMB_SM2CTRL_LDFQ0_MASK       0x1000U
  #define PWMB_SM2CTRL_LDFQ1_MASK       0x2000U
  #define PWMB_SM2CTRL_LDFQ2_MASK       0x4000U
  #define PWMB_SM2CTRL_LDFQ3_MASK       0x8000U
  #define PWMB_SM2CTRL_PRSC_MASK        0x70U
  #define PWMB_SM2CTRL_PRSC_BITNUM      0x04U
  #define PWMB_SM2CTRL_DT_MASK          0x0300U
  #define PWMB_SM2CTRL_DT_BITNUM        0x08U
  #define PWMB_SM2CTRL_LDFQ_MASK        0xF000U
  #define PWMB_SM2CTRL_LDFQ_BITNUM      0x0CU
  #define PWMB_SM2CTRL                  (*((volatile word *)0x0000E763))


  word Reserved16[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL0 - Value Register 0; 0x0000E765 ***/
  union {
    word Word;
  } PWMB_SM2VAL0_STR;

  #define PWMB_SM2VAL0                  (*((volatile word *)0x0000E765))


  word Reserved17[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL1 - Value Register 1; 0x0000E767 ***/
  union {
    word Word;
  } PWMB_SM2VAL1_STR;

  #define PWMB_SM2VAL1                  (*((volatile word *)0x0000E767))


  word Reserved18[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL2 - Value Register 2; 0x0000E769 ***/
  union {
    word Word;
  } PWMB_SM2VAL2_STR;

  #define PWMB_SM2VAL2                  (*((volatile word *)0x0000E769))


  word Reserved19[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL3 - Value Register 3; 0x0000E76B ***/
  union {
    word Word;
  } PWMB_SM2VAL3_STR;

  #define PWMB_SM2VAL3                  (*((volatile word *)0x0000E76B))


  word Reserved20[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL4 - Value Register 4; 0x0000E76D ***/
  union {
    word Word;
  } PWMB_SM2VAL4_STR;

  #define PWMB_SM2VAL4                  (*((volatile word *)0x0000E76D))


  word Reserved21[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2VAL5 - Value Register 5; 0x0000E76F ***/
  union {
    word Word;
  } PWMB_SM2VAL5_STR;

  #define PWMB_SM2VAL5                  (*((volatile word *)0x0000E76F))


  word Reserved22[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM2OCTRL - Output Control Register; 0x0000E771 ***/
  union {
    word Word;
  } PWMB_SM2OCTRL_STR;

  #define PWMB_SM2OCTRL_PWMXFS0_MASK    0x01U
  #define PWMB_SM2OCTRL_PWMXFS1_MASK    0x02U
  #define PWMB_SM2OCTRL_PWMBFS0_MASK    0x04U
  #define PWMB_SM2OCTRL_PWMBFS1_MASK    0x08U
  #define PWMB_SM2OCTRL_PWMAFS0_MASK    0x10U
  #define PWMB_SM2OCTRL_PWMAFS1_MASK    0x20U
  #define PWMB_SM2OCTRL_POLX_MASK       0x0100U
  #define PWMB_SM2OCTRL_POLB_MASK       0x0200U
  #define PWMB_SM2OCTRL_POLA_MASK       0x0400U
  #define PWMB_SM2OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMB_SM2OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMB_SM2OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMB_SM2OCTRL_PWMXFS_MASK     0x03U
  #define PWMB_SM2OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMB_SM2OCTRL_PWMBFS_MASK     0x0CU
  #define PWMB_SM2OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMB_SM2OCTRL_PWMAFS_MASK     0x30U
  #define PWMB_SM2OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMB_SM2OCTRL                 (*((volatile word *)0x0000E771))


  /*** PWMB_SM2STS - Status Register; 0x0000E772 ***/
  union {
    word Word;
  } PWMB_SM2STS_STR;

  #define PWMB_SM2STS_CMPF0_MASK        0x01U
  #define PWMB_SM2STS_CMPF1_MASK        0x02U
  #define PWMB_SM2STS_CMPF2_MASK        0x04U
  #define PWMB_SM2STS_CMPF3_MASK        0x08U
  #define PWMB_SM2STS_CMPF4_MASK        0x10U
  #define PWMB_SM2STS_CMPF5_MASK        0x20U
  #define PWMB_SM2STS_CFX0_MASK         0x40U
  #define PWMB_SM2STS_CFX1_MASK         0x80U
  #define PWMB_SM2STS_CFB0_MASK         0x0100U
  #define PWMB_SM2STS_CFB1_MASK         0x0200U
  #define PWMB_SM2STS_CFA0_MASK         0x0400U
  #define PWMB_SM2STS_CFA1_MASK         0x0800U
  #define PWMB_SM2STS_RF_MASK           0x1000U
  #define PWMB_SM2STS_REF_MASK          0x2000U
  #define PWMB_SM2STS_RUF_MASK          0x4000U
  #define PWMB_SM2STS_CMPF_MASK         0x3FU
  #define PWMB_SM2STS_CMPF_BITNUM       0x00U
  #define PWMB_SM2STS                   (*((volatile word *)0x0000E772))


  /*** PWMB_SM2INTEN - Interrupt Enable Register; 0x0000E773 ***/
  union {
    word Word;
  } PWMB_SM2INTEN_STR;

  #define PWMB_SM2INTEN_CMPIE0_MASK     0x01U
  #define PWMB_SM2INTEN_CMPIE1_MASK     0x02U
  #define PWMB_SM2INTEN_CMPIE2_MASK     0x04U
  #define PWMB_SM2INTEN_CMPIE3_MASK     0x08U
  #define PWMB_SM2INTEN_CMPIE4_MASK     0x10U
  #define PWMB_SM2INTEN_CMPIE5_MASK     0x20U
  #define PWMB_SM2INTEN_CX0IE_MASK      0x40U
  #define PWMB_SM2INTEN_CX1IE_MASK      0x80U
  #define PWMB_SM2INTEN_CB0IE_MASK      0x0100U
  #define PWMB_SM2INTEN_CB1IE_MASK      0x0200U
  #define PWMB_SM2INTEN_CA0IE_MASK      0x0400U
  #define PWMB_SM2INTEN_CA1IE_MASK      0x0800U
  #define PWMB_SM2INTEN_RIE_MASK        0x1000U
  #define PWMB_SM2INTEN_REIE_MASK       0x2000U
  #define PWMB_SM2INTEN_CMPIE_MASK      0x3FU
  #define PWMB_SM2INTEN_CMPIE_BITNUM    0x00U
  #define PWMB_SM2INTEN                 (*((volatile word *)0x0000E773))


  /*** PWMB_SM2DMAEN - DMA Enable Register; 0x0000E774 ***/
  union {
    word Word;
  } PWMB_SM2DMAEN_STR;

  #define PWMB_SM2DMAEN_CX0DE_MASK      0x01U
  #define PWMB_SM2DMAEN_CX1DE_MASK      0x02U
  #define PWMB_SM2DMAEN_CB0DE_MASK      0x04U
  #define PWMB_SM2DMAEN_CB1DE_MASK      0x08U
  #define PWMB_SM2DMAEN_CA0DE_MASK      0x10U
  #define PWMB_SM2DMAEN_CA1DE_MASK      0x20U
  #define PWMB_SM2DMAEN_CAPTDE0_MASK    0x40U
  #define PWMB_SM2DMAEN_CAPTDE1_MASK    0x80U
  #define PWMB_SM2DMAEN_FAND_MASK       0x0100U
  #define PWMB_SM2DMAEN_VALDE_MASK      0x0200U
  #define PWMB_SM2DMAEN_CAPTDE_MASK     0xC0U
  #define PWMB_SM2DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMB_SM2DMAEN                 (*((volatile word *)0x0000E774))


  /*** PWMB_SM2TCTRL - Output Trigger Control Register; 0x0000E775 ***/
  union {
    word Word;
  } PWMB_SM2TCTRL_STR;

  #define PWMB_SM2TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMB_SM2TCTRL_PWBOT1_MASK     0x4000U
  #define PWMB_SM2TCTRL_PWAOT0_MASK     0x8000U
  #define PWMB_SM2TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMB_SM2TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMB_SM2TCTRL                 (*((volatile word *)0x0000E775))


  /*** PWMB_SM2DISMAP0 - Fault Disable Mapping Register 0; 0x0000E776 ***/
  union {
    word Word;
  } PWMB_SM2DISMAP0_STR;

  #define PWMB_SM2DISMAP0_DIS0A0_MASK   0x01U
  #define PWMB_SM2DISMAP0_DIS0A1_MASK   0x02U
  #define PWMB_SM2DISMAP0_DIS0A2_MASK   0x04U
  #define PWMB_SM2DISMAP0_DIS0A3_MASK   0x08U
  #define PWMB_SM2DISMAP0_DIS0B0_MASK   0x10U
  #define PWMB_SM2DISMAP0_DIS0B1_MASK   0x20U
  #define PWMB_SM2DISMAP0_DIS0B2_MASK   0x40U
  #define PWMB_SM2DISMAP0_DIS0B3_MASK   0x80U
  #define PWMB_SM2DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMB_SM2DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMB_SM2DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMB_SM2DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMB_SM2DISMAP0_DIS0A_MASK    0x0FU
  #define PWMB_SM2DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMB_SM2DISMAP0_DIS0B_MASK    0xF0U
  #define PWMB_SM2DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMB_SM2DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMB_SM2DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMB_SM2DISMAP0               (*((volatile word *)0x0000E776))


  /*** PWMB_SM2DISMAP1 - Fault Disable Mapping Register 1; 0x0000E777 ***/
  union {
    word Word;
  } PWMB_SM2DISMAP1_STR;

  #define PWMB_SM2DISMAP1_DIS1A0_MASK   0x01U
  #define PWMB_SM2DISMAP1_DIS1A1_MASK   0x02U
  #define PWMB_SM2DISMAP1_DIS1A2_MASK   0x04U
  #define PWMB_SM2DISMAP1_DIS1A3_MASK   0x08U
  #define PWMB_SM2DISMAP1_DIS1B0_MASK   0x10U
  #define PWMB_SM2DISMAP1_DIS1B1_MASK   0x20U
  #define PWMB_SM2DISMAP1_DIS1B2_MASK   0x40U
  #define PWMB_SM2DISMAP1_DIS1B3_MASK   0x80U
  #define PWMB_SM2DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMB_SM2DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMB_SM2DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMB_SM2DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMB_SM2DISMAP1_DIS1A_MASK    0x0FU
  #define PWMB_SM2DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMB_SM2DISMAP1_DIS1B_MASK    0xF0U
  #define PWMB_SM2DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMB_SM2DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMB_SM2DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMB_SM2DISMAP1               (*((volatile word *)0x0000E777))


  /*** PWMB_SM2DTCNT0 - Deadtime Count Register 0; 0x0000E778 ***/
  union {
    word Word;
  } PWMB_SM2DTCNT0_STR;

  #define PWMB_SM2DTCNT0_DTCNT00_MASK   0x01U
  #define PWMB_SM2DTCNT0_DTCNT01_MASK   0x02U
  #define PWMB_SM2DTCNT0_DTCNT02_MASK   0x04U
  #define PWMB_SM2DTCNT0_DTCNT03_MASK   0x08U
  #define PWMB_SM2DTCNT0_DTCNT04_MASK   0x10U
  #define PWMB_SM2DTCNT0_DTCNT05_MASK   0x20U
  #define PWMB_SM2DTCNT0_DTCNT06_MASK   0x40U
  #define PWMB_SM2DTCNT0_DTCNT07_MASK   0x80U
  #define PWMB_SM2DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMB_SM2DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMB_SM2DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMB_SM2DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMB_SM2DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMB_SM2DTCNT0                (*((volatile word *)0x0000E778))


  /*** PWMB_SM2DTCNT1 - Deadtime Count Register 1; 0x0000E779 ***/
  union {
    word Word;
  } PWMB_SM2DTCNT1_STR;

  #define PWMB_SM2DTCNT1_DTCNT10_MASK   0x01U
  #define PWMB_SM2DTCNT1_DTCNT11_MASK   0x02U
  #define PWMB_SM2DTCNT1_DTCNT12_MASK   0x04U
  #define PWMB_SM2DTCNT1_DTCNT13_MASK   0x08U
  #define PWMB_SM2DTCNT1_DTCNT14_MASK   0x10U
  #define PWMB_SM2DTCNT1_DTCNT15_MASK   0x20U
  #define PWMB_SM2DTCNT1_DTCNT16_MASK   0x40U
  #define PWMB_SM2DTCNT1_DTCNT17_MASK   0x80U
  #define PWMB_SM2DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMB_SM2DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMB_SM2DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMB_SM2DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMB_SM2DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMB_SM2DTCNT1                (*((volatile word *)0x0000E779))


  /*** PWMB_SM2CAPTCTRLA - Capture Control A Register; 0x0000E77A ***/
  union {
    word Word;
  } PWMB_SM2CAPTCTRLA_STR;

  #define PWMB_SM2CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMB_SM2CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMB_SM2CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMB_SM2CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMB_SM2CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMB_SM2CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMB_SM2CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMB_SM2CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMB_SM2CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMB_SM2CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMB_SM2CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMB_SM2CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMB_SM2CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMB_SM2CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMB_SM2CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMB_SM2CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMB_SM2CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMB_SM2CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMB_SM2CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMB_SM2CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMB_SM2CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMB_SM2CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMB_SM2CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMB_SM2CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMB_SM2CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMB_SM2CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMB_SM2CAPTCTRLA             (*((volatile word *)0x0000E77A))


  /*** PWMB_SM2CAPTCOMPA - Capture Compare A Register; 0x0000E77B ***/
  union {
    word Word;
  } PWMB_SM2CAPTCOMPA_STR;

  #define PWMB_SM2CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMB_SM2CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMB_SM2CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMB_SM2CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMB_SM2CAPTCOMPA             (*((volatile word *)0x0000E77B))


  /*** PWMB_SM2CAPTCTRLB - Capture Control B Register; 0x0000E77C ***/
  union {
    word Word;
  } PWMB_SM2CAPTCTRLB_STR;

  #define PWMB_SM2CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMB_SM2CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMB_SM2CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMB_SM2CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMB_SM2CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMB_SM2CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMB_SM2CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMB_SM2CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMB_SM2CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMB_SM2CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMB_SM2CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMB_SM2CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMB_SM2CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMB_SM2CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMB_SM2CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMB_SM2CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMB_SM2CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMB_SM2CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMB_SM2CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMB_SM2CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMB_SM2CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMB_SM2CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMB_SM2CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMB_SM2CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMB_SM2CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMB_SM2CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMB_SM2CAPTCTRLB             (*((volatile word *)0x0000E77C))


  /*** PWMB_SM2CAPTCOMPB - Capture Compare B Register; 0x0000E77D ***/
  union {
    word Word;
  } PWMB_SM2CAPTCOMPB_STR;

  #define PWMB_SM2CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMB_SM2CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMB_SM2CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMB_SM2CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMB_SM2CAPTCOMPB             (*((volatile word *)0x0000E77D))


  /*** PWMB_SM2CAPTCTRLX - Capture Control X Register; 0x0000E77E ***/
  union {
    word Word;
  } PWMB_SM2CAPTCTRLX_STR;

  #define PWMB_SM2CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMB_SM2CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMB_SM2CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMB_SM2CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMB_SM2CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMB_SM2CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMB_SM2CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMB_SM2CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMB_SM2CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMB_SM2CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMB_SM2CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMB_SM2CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMB_SM2CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMB_SM2CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMB_SM2CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMB_SM2CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMB_SM2CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMB_SM2CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMB_SM2CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMB_SM2CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMB_SM2CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMB_SM2CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMB_SM2CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMB_SM2CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMB_SM2CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMB_SM2CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMB_SM2CAPTCTRLX             (*((volatile word *)0x0000E77E))


  /*** PWMB_SM2CAPTCOMPX - Capture Compare X Register; 0x0000E77F ***/
  union {
    word Word;
  } PWMB_SM2CAPTCOMPX_STR;

  #define PWMB_SM2CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMB_SM2CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMB_SM2CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMB_SM2CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMB_SM2CAPTCOMPX             (*((volatile word *)0x0000E77F))


  /*** PWMB_SM2CVAL0 - Capture Value 0 Register; 0x0000E780 ***/
  union {
    word Word;
  } PWMB_SM2CVAL0_STR;

  #define PWMB_SM2CVAL0                 (*((volatile word *)0x0000E780))


  /*** PWMB_SM2CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E781 ***/
  union {
    word Word;
  } PWMB_SM2CVAL0CYC_STR;

  #define PWMB_SM2CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMB_SM2CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMB_SM2CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMB_SM2CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMB_SM2CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMB_SM2CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL0CYC              (*((volatile word *)0x0000E781))


  /*** PWMB_SM2CVAL1 - Capture Value 1 Register; 0x0000E782 ***/
  union {
    word Word;
  } PWMB_SM2CVAL1_STR;

  #define PWMB_SM2CVAL1                 (*((volatile word *)0x0000E782))


  /*** PWMB_SM2CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E783 ***/
  union {
    word Word;
  } PWMB_SM2CVAL1CYC_STR;

  #define PWMB_SM2CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMB_SM2CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMB_SM2CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMB_SM2CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMB_SM2CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMB_SM2CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL1CYC              (*((volatile word *)0x0000E783))


  /*** PWMB_SM2CVAL2 - Capture Value 2 Register; 0x0000E784 ***/
  union {
    word Word;
  } PWMB_SM2CVAL2_STR;

  #define PWMB_SM2CVAL2                 (*((volatile word *)0x0000E784))


  /*** PWMB_SM2CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E785 ***/
  union {
    word Word;
  } PWMB_SM2CVAL2CYC_STR;

  #define PWMB_SM2CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMB_SM2CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMB_SM2CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMB_SM2CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMB_SM2CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMB_SM2CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL2CYC              (*((volatile word *)0x0000E785))


  /*** PWMB_SM2CVAL3 - Capture Value 3 Register; 0x0000E786 ***/
  union {
    word Word;
  } PWMB_SM2CVAL3_STR;

  #define PWMB_SM2CVAL3                 (*((volatile word *)0x0000E786))


  /*** PWMB_SM2CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E787 ***/
  union {
    word Word;
  } PWMB_SM2CVAL3CYC_STR;

  #define PWMB_SM2CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMB_SM2CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMB_SM2CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMB_SM2CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMB_SM2CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMB_SM2CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL3CYC              (*((volatile word *)0x0000E787))


  /*** PWMB_SM2CVAL4 - Capture Value 4 Register; 0x0000E788 ***/
  union {
    word Word;
  } PWMB_SM2CVAL4_STR;

  #define PWMB_SM2CVAL4                 (*((volatile word *)0x0000E788))


  /*** PWMB_SM2CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E789 ***/
  union {
    word Word;
  } PWMB_SM2CVAL4CYC_STR;

  #define PWMB_SM2CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMB_SM2CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMB_SM2CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMB_SM2CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMB_SM2CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMB_SM2CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL4CYC              (*((volatile word *)0x0000E789))


  /*** PWMB_SM2CVAL5 - Capture Value 5 Register; 0x0000E78A ***/
  union {
    word Word;
  } PWMB_SM2CVAL5_STR;

  #define PWMB_SM2CVAL5                 (*((volatile word *)0x0000E78A))


  /*** PWMB_SM2CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E78B ***/
  union {
    word Word;
  } PWMB_SM2CVAL5CYC_STR;

  #define PWMB_SM2CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMB_SM2CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMB_SM2CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMB_SM2CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMB_SM2CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMB_SM2CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMB_SM2CVAL5CYC              (*((volatile word *)0x0000E78B))


  word Reserved23[4];                  /* Reserved (unused) registers */

  /*** PWMB_SM3CNT - Counter Register; 0x0000E790 ***/
  union {
    word Word;
  } PWMB_SM3CNT_STR;

  #define PWMB_SM3CNT                   (*((volatile word *)0x0000E790))


  /*** PWMB_SM3INIT - Initial Count Register; 0x0000E791 ***/
  union {
    word Word;
  } PWMB_SM3INIT_STR;

  #define PWMB_SM3INIT                  (*((volatile word *)0x0000E791))


  /*** PWMB_SM3CTRL2 - Control 2 Register; 0x0000E792 ***/
  union {
    word Word;
  } PWMB_SM3CTRL2_STR;

  #define PWMB_SM3CTRL2_CLK_SEL0_MASK   0x01U
  #define PWMB_SM3CTRL2_CLK_SEL1_MASK   0x02U
  #define PWMB_SM3CTRL2_RELOAD_SEL_MASK 0x04U
  #define PWMB_SM3CTRL2_FORCE_SEL0_MASK 0x08U
  #define PWMB_SM3CTRL2_FORCE_SEL1_MASK 0x10U
  #define PWMB_SM3CTRL2_FORCE_SEL2_MASK 0x20U
  #define PWMB_SM3CTRL2_FORCE_MASK      0x40U
  #define PWMB_SM3CTRL2_FRCEN_MASK      0x80U
  #define PWMB_SM3CTRL2_INIT_SEL0_MASK  0x0100U
  #define PWMB_SM3CTRL2_INIT_SEL1_MASK  0x0200U
  #define PWMB_SM3CTRL2_PWMX_INIT_MASK  0x0400U
  #define PWMB_SM3CTRL2_PWM45_INIT_MASK 0x0800U
  #define PWMB_SM3CTRL2_PWM23_INIT_MASK 0x1000U
  #define PWMB_SM3CTRL2_INDEP_MASK      0x2000U
  #define PWMB_SM3CTRL2_WAITEN_MASK     0x4000U
  #define PWMB_SM3CTRL2_DBGEN_MASK      0x8000U
  #define PWMB_SM3CTRL2_CLK_SEL_MASK    0x03U
  #define PWMB_SM3CTRL2_CLK_SEL_BITNUM  0x00U
  #define PWMB_SM3CTRL2_FORCE_SEL_MASK  0x38U
  #define PWMB_SM3CTRL2_FORCE_SEL_BITNUM 0x03U
  #define PWMB_SM3CTRL2_INIT_SEL_MASK   0x0300U
  #define PWMB_SM3CTRL2_INIT_SEL_BITNUM 0x08U
  #define PWMB_SM3CTRL2                 (*((volatile word *)0x0000E792))


  /*** PWMB_SM3CTRL - Control Register; 0x0000E793 ***/
  union {
    word Word;
  } PWMB_SM3CTRL_STR;

  #define PWMB_SM3CTRL_DBLEN_MASK       0x01U
  #define PWMB_SM3CTRL_DBLX_MASK        0x02U
  #define PWMB_SM3CTRL_LDMOD_MASK       0x04U
  #define PWMB_SM3CTRL_PRSC0_MASK       0x10U
  #define PWMB_SM3CTRL_PRSC1_MASK       0x20U
  #define PWMB_SM3CTRL_PRSC2_MASK       0x40U
  #define PWMB_SM3CTRL_DT0_MASK         0x0100U
  #define PWMB_SM3CTRL_DT1_MASK         0x0200U
  #define PWMB_SM3CTRL_FULL_MASK        0x0400U
  #define PWMB_SM3CTRL_HALF_MASK        0x0800U
  #define PWMB_SM3CTRL_LDFQ0_MASK       0x1000U
  #define PWMB_SM3CTRL_LDFQ1_MASK       0x2000U
  #define PWMB_SM3CTRL_LDFQ2_MASK       0x4000U
  #define PWMB_SM3CTRL_LDFQ3_MASK       0x8000U
  #define PWMB_SM3CTRL_PRSC_MASK        0x70U
  #define PWMB_SM3CTRL_PRSC_BITNUM      0x04U
  #define PWMB_SM3CTRL_DT_MASK          0x0300U
  #define PWMB_SM3CTRL_DT_BITNUM        0x08U
  #define PWMB_SM3CTRL_LDFQ_MASK        0xF000U
  #define PWMB_SM3CTRL_LDFQ_BITNUM      0x0CU
  #define PWMB_SM3CTRL                  (*((volatile word *)0x0000E793))


  word Reserved24[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL0 - Value Register 0; 0x0000E795 ***/
  union {
    word Word;
  } PWMB_SM3VAL0_STR;

  #define PWMB_SM3VAL0                  (*((volatile word *)0x0000E795))


  word Reserved25[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL1 - Value Register 1; 0x0000E797 ***/
  union {
    word Word;
  } PWMB_SM3VAL1_STR;

  #define PWMB_SM3VAL1                  (*((volatile word *)0x0000E797))


  word Reserved26[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL2 - Value Register 2; 0x0000E799 ***/
  union {
    word Word;
  } PWMB_SM3VAL2_STR;

  #define PWMB_SM3VAL2                  (*((volatile word *)0x0000E799))


  word Reserved27[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL3 - Value Register 3; 0x0000E79B ***/
  union {
    word Word;
  } PWMB_SM3VAL3_STR;

  #define PWMB_SM3VAL3                  (*((volatile word *)0x0000E79B))


  word Reserved28[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL4 - Value Register 4; 0x0000E79D ***/
  union {
    word Word;
  } PWMB_SM3VAL4_STR;

  #define PWMB_SM3VAL4                  (*((volatile word *)0x0000E79D))


  word Reserved29[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3VAL5 - Value Register 5; 0x0000E79F ***/
  union {
    word Word;
  } PWMB_SM3VAL5_STR;

  #define PWMB_SM3VAL5                  (*((volatile word *)0x0000E79F))


  word Reserved30[1];                  /* Reserved (unused) registers */

  /*** PWMB_SM3OCTRL - Output Control Register; 0x0000E7A1 ***/
  union {
    word Word;
  } PWMB_SM3OCTRL_STR;

  #define PWMB_SM3OCTRL_PWMXFS0_MASK    0x01U
  #define PWMB_SM3OCTRL_PWMXFS1_MASK    0x02U
  #define PWMB_SM3OCTRL_PWMBFS0_MASK    0x04U
  #define PWMB_SM3OCTRL_PWMBFS1_MASK    0x08U
  #define PWMB_SM3OCTRL_PWMAFS0_MASK    0x10U
  #define PWMB_SM3OCTRL_PWMAFS1_MASK    0x20U
  #define PWMB_SM3OCTRL_POLX_MASK       0x0100U
  #define PWMB_SM3OCTRL_POLB_MASK       0x0200U
  #define PWMB_SM3OCTRL_POLA_MASK       0x0400U
  #define PWMB_SM3OCTRL_PWMX_IN_MASK    0x2000U
  #define PWMB_SM3OCTRL_PWMB_IN_MASK    0x4000U
  #define PWMB_SM3OCTRL_PWMA_IN_MASK    0x8000U
  #define PWMB_SM3OCTRL_PWMXFS_MASK     0x03U
  #define PWMB_SM3OCTRL_PWMXFS_BITNUM   0x00U
  #define PWMB_SM3OCTRL_PWMBFS_MASK     0x0CU
  #define PWMB_SM3OCTRL_PWMBFS_BITNUM   0x02U
  #define PWMB_SM3OCTRL_PWMAFS_MASK     0x30U
  #define PWMB_SM3OCTRL_PWMAFS_BITNUM   0x04U
  #define PWMB_SM3OCTRL                 (*((volatile word *)0x0000E7A1))


  /*** PWMB_SM3STS - Status Register; 0x0000E7A2 ***/
  union {
    word Word;
  } PWMB_SM3STS_STR;

  #define PWMB_SM3STS_CMPF0_MASK        0x01U
  #define PWMB_SM3STS_CMPF1_MASK        0x02U
  #define PWMB_SM3STS_CMPF2_MASK        0x04U
  #define PWMB_SM3STS_CMPF3_MASK        0x08U
  #define PWMB_SM3STS_CMPF4_MASK        0x10U
  #define PWMB_SM3STS_CMPF5_MASK        0x20U
  #define PWMB_SM3STS_CFX0_MASK         0x40U
  #define PWMB_SM3STS_CFX1_MASK         0x80U
  #define PWMB_SM3STS_CFB0_MASK         0x0100U
  #define PWMB_SM3STS_CFB1_MASK         0x0200U
  #define PWMB_SM3STS_CFA0_MASK         0x0400U
  #define PWMB_SM3STS_CFA1_MASK         0x0800U
  #define PWMB_SM3STS_RF_MASK           0x1000U
  #define PWMB_SM3STS_REF_MASK          0x2000U
  #define PWMB_SM3STS_RUF_MASK          0x4000U
  #define PWMB_SM3STS_CMPF_MASK         0x3FU
  #define PWMB_SM3STS_CMPF_BITNUM       0x00U
  #define PWMB_SM3STS                   (*((volatile word *)0x0000E7A2))


  /*** PWMB_SM3INTEN - Interrupt Enable Register; 0x0000E7A3 ***/
  union {
    word Word;
  } PWMB_SM3INTEN_STR;

  #define PWMB_SM3INTEN_CMPIE0_MASK     0x01U
  #define PWMB_SM3INTEN_CMPIE1_MASK     0x02U
  #define PWMB_SM3INTEN_CMPIE2_MASK     0x04U
  #define PWMB_SM3INTEN_CMPIE3_MASK     0x08U
  #define PWMB_SM3INTEN_CMPIE4_MASK     0x10U
  #define PWMB_SM3INTEN_CMPIE5_MASK     0x20U
  #define PWMB_SM3INTEN_CX0IE_MASK      0x40U
  #define PWMB_SM3INTEN_CX1IE_MASK      0x80U
  #define PWMB_SM3INTEN_CB0IE_MASK      0x0100U
  #define PWMB_SM3INTEN_CB1IE_MASK      0x0200U
  #define PWMB_SM3INTEN_CA0IE_MASK      0x0400U
  #define PWMB_SM3INTEN_CA1IE_MASK      0x0800U
  #define PWMB_SM3INTEN_RIE_MASK        0x1000U
  #define PWMB_SM3INTEN_REIE_MASK       0x2000U
  #define PWMB_SM3INTEN_CMPIE_MASK      0x3FU
  #define PWMB_SM3INTEN_CMPIE_BITNUM    0x00U
  #define PWMB_SM3INTEN                 (*((volatile word *)0x0000E7A3))


  /*** PWMB_SM3DMAEN - DMA Enable Register; 0x0000E7A4 ***/
  union {
    word Word;
  } PWMB_SM3DMAEN_STR;

  #define PWMB_SM3DMAEN_CX0DE_MASK      0x01U
  #define PWMB_SM3DMAEN_CX1DE_MASK      0x02U
  #define PWMB_SM3DMAEN_CB0DE_MASK      0x04U
  #define PWMB_SM3DMAEN_CB1DE_MASK      0x08U
  #define PWMB_SM3DMAEN_CA0DE_MASK      0x10U
  #define PWMB_SM3DMAEN_CA1DE_MASK      0x20U
  #define PWMB_SM3DMAEN_CAPTDE0_MASK    0x40U
  #define PWMB_SM3DMAEN_CAPTDE1_MASK    0x80U
  #define PWMB_SM3DMAEN_FAND_MASK       0x0100U
  #define PWMB_SM3DMAEN_VALDE_MASK      0x0200U
  #define PWMB_SM3DMAEN_CAPTDE_MASK     0xC0U
  #define PWMB_SM3DMAEN_CAPTDE_BITNUM   0x06U
  #define PWMB_SM3DMAEN                 (*((volatile word *)0x0000E7A4))


  /*** PWMB_SM3TCTRL - Output Trigger Control Register; 0x0000E7A5 ***/
  union {
    word Word;
  } PWMB_SM3TCTRL_STR;

  #define PWMB_SM3TCTRL_OUT_TRIG_EN0_MASK 0x01U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN1_MASK 0x02U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN2_MASK 0x04U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN3_MASK 0x08U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN4_MASK 0x10U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN5_MASK 0x20U
  #define PWMB_SM3TCTRL_PWBOT1_MASK     0x4000U
  #define PWMB_SM3TCTRL_PWAOT0_MASK     0x8000U
  #define PWMB_SM3TCTRL_OUT_TRIG_EN_MASK 0x3FU
  #define PWMB_SM3TCTRL_OUT_TRIG_EN_BITNUM 0x00U
  #define PWMB_SM3TCTRL                 (*((volatile word *)0x0000E7A5))


  /*** PWMB_SM3DISMAP0 - Fault Disable Mapping Register 0; 0x0000E7A6 ***/
  union {
    word Word;
  } PWMB_SM3DISMAP0_STR;

  #define PWMB_SM3DISMAP0_DIS0A0_MASK   0x01U
  #define PWMB_SM3DISMAP0_DIS0A1_MASK   0x02U
  #define PWMB_SM3DISMAP0_DIS0A2_MASK   0x04U
  #define PWMB_SM3DISMAP0_DIS0A3_MASK   0x08U
  #define PWMB_SM3DISMAP0_DIS0B0_MASK   0x10U
  #define PWMB_SM3DISMAP0_DIS0B1_MASK   0x20U
  #define PWMB_SM3DISMAP0_DIS0B2_MASK   0x40U
  #define PWMB_SM3DISMAP0_DIS0B3_MASK   0x80U
  #define PWMB_SM3DISMAP0_DIS0X0_MASK   0x0100U
  #define PWMB_SM3DISMAP0_DIS0X1_MASK   0x0200U
  #define PWMB_SM3DISMAP0_DIS0X2_MASK   0x0400U
  #define PWMB_SM3DISMAP0_DIS0X3_MASK   0x0800U
  #define PWMB_SM3DISMAP0_DIS0A_MASK    0x0FU
  #define PWMB_SM3DISMAP0_DIS0A_BITNUM  0x00U
  #define PWMB_SM3DISMAP0_DIS0B_MASK    0xF0U
  #define PWMB_SM3DISMAP0_DIS0B_BITNUM  0x04U
  #define PWMB_SM3DISMAP0_DIS0X_MASK    0x0F00U
  #define PWMB_SM3DISMAP0_DIS0X_BITNUM  0x08U
  #define PWMB_SM3DISMAP0               (*((volatile word *)0x0000E7A6))


  /*** PWMB_SM3DISMAP1 - Fault Disable Mapping Register 1; 0x0000E7A7 ***/
  union {
    word Word;
  } PWMB_SM3DISMAP1_STR;

  #define PWMB_SM3DISMAP1_DIS1A0_MASK   0x01U
  #define PWMB_SM3DISMAP1_DIS1A1_MASK   0x02U
  #define PWMB_SM3DISMAP1_DIS1A2_MASK   0x04U
  #define PWMB_SM3DISMAP1_DIS1A3_MASK   0x08U
  #define PWMB_SM3DISMAP1_DIS1B0_MASK   0x10U
  #define PWMB_SM3DISMAP1_DIS1B1_MASK   0x20U
  #define PWMB_SM3DISMAP1_DIS1B2_MASK   0x40U
  #define PWMB_SM3DISMAP1_DIS1B3_MASK   0x80U
  #define PWMB_SM3DISMAP1_DIS1X0_MASK   0x0100U
  #define PWMB_SM3DISMAP1_DIS1X1_MASK   0x0200U
  #define PWMB_SM3DISMAP1_DIS1X2_MASK   0x0400U
  #define PWMB_SM3DISMAP1_DIS1X3_MASK   0x0800U
  #define PWMB_SM3DISMAP1_DIS1A_MASK    0x0FU
  #define PWMB_SM3DISMAP1_DIS1A_BITNUM  0x00U
  #define PWMB_SM3DISMAP1_DIS1B_MASK    0xF0U
  #define PWMB_SM3DISMAP1_DIS1B_BITNUM  0x04U
  #define PWMB_SM3DISMAP1_DIS1X_MASK    0x0F00U
  #define PWMB_SM3DISMAP1_DIS1X_BITNUM  0x08U
  #define PWMB_SM3DISMAP1               (*((volatile word *)0x0000E7A7))


  /*** PWMB_SM3DTCNT0 - Deadtime Count Register 0; 0x0000E7A8 ***/
  union {
    word Word;
  } PWMB_SM3DTCNT0_STR;

  #define PWMB_SM3DTCNT0_DTCNT00_MASK   0x01U
  #define PWMB_SM3DTCNT0_DTCNT01_MASK   0x02U
  #define PWMB_SM3DTCNT0_DTCNT02_MASK   0x04U
  #define PWMB_SM3DTCNT0_DTCNT03_MASK   0x08U
  #define PWMB_SM3DTCNT0_DTCNT04_MASK   0x10U
  #define PWMB_SM3DTCNT0_DTCNT05_MASK   0x20U
  #define PWMB_SM3DTCNT0_DTCNT06_MASK   0x40U
  #define PWMB_SM3DTCNT0_DTCNT07_MASK   0x80U
  #define PWMB_SM3DTCNT0_DTCNT08_MASK   0x0100U
  #define PWMB_SM3DTCNT0_DTCNT09_MASK   0x0200U
  #define PWMB_SM3DTCNT0_DTCNT010_MASK  0x0400U
  #define PWMB_SM3DTCNT0_DTCNT0_MASK    0x07FFU
  #define PWMB_SM3DTCNT0_DTCNT0_BITNUM  0x00U
  #define PWMB_SM3DTCNT0                (*((volatile word *)0x0000E7A8))


  /*** PWMB_SM3DTCNT1 - Deadtime Count Register 1; 0x0000E7A9 ***/
  union {
    word Word;
  } PWMB_SM3DTCNT1_STR;

  #define PWMB_SM3DTCNT1_DTCNT10_MASK   0x01U
  #define PWMB_SM3DTCNT1_DTCNT11_MASK   0x02U
  #define PWMB_SM3DTCNT1_DTCNT12_MASK   0x04U
  #define PWMB_SM3DTCNT1_DTCNT13_MASK   0x08U
  #define PWMB_SM3DTCNT1_DTCNT14_MASK   0x10U
  #define PWMB_SM3DTCNT1_DTCNT15_MASK   0x20U
  #define PWMB_SM3DTCNT1_DTCNT16_MASK   0x40U
  #define PWMB_SM3DTCNT1_DTCNT17_MASK   0x80U
  #define PWMB_SM3DTCNT1_DTCNT18_MASK   0x0100U
  #define PWMB_SM3DTCNT1_DTCNT19_MASK   0x0200U
  #define PWMB_SM3DTCNT1_DTCNT110_MASK  0x0400U
  #define PWMB_SM3DTCNT1_DTCNT1_MASK    0x07FFU
  #define PWMB_SM3DTCNT1_DTCNT1_BITNUM  0x00U
  #define PWMB_SM3DTCNT1                (*((volatile word *)0x0000E7A9))


  /*** PWMB_SM3CAPTCTRLA - Capture Control A Register; 0x0000E7AA ***/
  union {
    word Word;
  } PWMB_SM3CAPTCTRLA_STR;

  #define PWMB_SM3CAPTCTRLA_ARMA_MASK   0x01U
  #define PWMB_SM3CAPTCTRLA_ONESHOTA_MASK 0x02U
  #define PWMB_SM3CAPTCTRLA_EDGA00_MASK 0x04U
  #define PWMB_SM3CAPTCTRLA_EDGA01_MASK 0x08U
  #define PWMB_SM3CAPTCTRLA_EDGA10_MASK 0x10U
  #define PWMB_SM3CAPTCTRLA_EDGA11_MASK 0x20U
  #define PWMB_SM3CAPTCTRLA_INP_SELA_MASK 0x40U
  #define PWMB_SM3CAPTCTRLA_EDGCNTA_EN_MASK 0x80U
  #define PWMB_SM3CAPTCTRLA_CFAWM0_MASK 0x0100U
  #define PWMB_SM3CAPTCTRLA_CFAWM1_MASK 0x0200U
  #define PWMB_SM3CAPTCTRLA_CA0CNT0_MASK 0x0400U
  #define PWMB_SM3CAPTCTRLA_CA0CNT1_MASK 0x0800U
  #define PWMB_SM3CAPTCTRLA_CA0CNT2_MASK 0x1000U
  #define PWMB_SM3CAPTCTRLA_CA1CNT0_MASK 0x2000U
  #define PWMB_SM3CAPTCTRLA_CA1CNT1_MASK 0x4000U
  #define PWMB_SM3CAPTCTRLA_CA1CNT2_MASK 0x8000U
  #define PWMB_SM3CAPTCTRLA_EDGA0_MASK  0x0CU
  #define PWMB_SM3CAPTCTRLA_EDGA0_BITNUM 0x02U
  #define PWMB_SM3CAPTCTRLA_EDGA1_MASK  0x30U
  #define PWMB_SM3CAPTCTRLA_EDGA1_BITNUM 0x04U
  #define PWMB_SM3CAPTCTRLA_CFAWM_MASK  0x0300U
  #define PWMB_SM3CAPTCTRLA_CFAWM_BITNUM 0x08U
  #define PWMB_SM3CAPTCTRLA_CA0CNT_MASK 0x1C00U
  #define PWMB_SM3CAPTCTRLA_CA0CNT_BITNUM 0x0AU
  #define PWMB_SM3CAPTCTRLA_CA1CNT_MASK 0xE000U
  #define PWMB_SM3CAPTCTRLA_CA1CNT_BITNUM 0x0DU
  #define PWMB_SM3CAPTCTRLA             (*((volatile word *)0x0000E7AA))


  /*** PWMB_SM3CAPTCOMPA - Capture Compare A Register; 0x0000E7AB ***/
  union {
    word Word;
  } PWMB_SM3CAPTCOMPA_STR;

  #define PWMB_SM3CAPTCOMPA_EDGCMPA0_MASK 0x01U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA1_MASK 0x02U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA2_MASK 0x04U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA3_MASK 0x08U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA4_MASK 0x10U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA5_MASK 0x20U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA6_MASK 0x40U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA7_MASK 0x80U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA0_MASK 0x0100U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA1_MASK 0x0200U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA2_MASK 0x0400U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA3_MASK 0x0800U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA4_MASK 0x1000U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA5_MASK 0x2000U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA6_MASK 0x4000U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA7_MASK 0x8000U
  #define PWMB_SM3CAPTCOMPA_EDGCMPA_MASK 0xFFU
  #define PWMB_SM3CAPTCOMPA_EDGCMPA_BITNUM 0x00U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA_MASK 0xFF00U
  #define PWMB_SM3CAPTCOMPA_EDGCNTA_BITNUM 0x08U
  #define PWMB_SM3CAPTCOMPA             (*((volatile word *)0x0000E7AB))


  /*** PWMB_SM3CAPTCTRLB - Capture Control B Register; 0x0000E7AC ***/
  union {
    word Word;
  } PWMB_SM3CAPTCTRLB_STR;

  #define PWMB_SM3CAPTCTRLB_ARMB_MASK   0x01U
  #define PWMB_SM3CAPTCTRLB_ONESHOTB_MASK 0x02U
  #define PWMB_SM3CAPTCTRLB_EDGB00_MASK 0x04U
  #define PWMB_SM3CAPTCTRLB_EDGB01_MASK 0x08U
  #define PWMB_SM3CAPTCTRLB_EDGB10_MASK 0x10U
  #define PWMB_SM3CAPTCTRLB_EDGB11_MASK 0x20U
  #define PWMB_SM3CAPTCTRLB_INP_SELB_MASK 0x40U
  #define PWMB_SM3CAPTCTRLB_EDGCNTB_EN_MASK 0x80U
  #define PWMB_SM3CAPTCTRLB_CFBWM0_MASK 0x0100U
  #define PWMB_SM3CAPTCTRLB_CFBWM1_MASK 0x0200U
  #define PWMB_SM3CAPTCTRLB_CB0CNT0_MASK 0x0400U
  #define PWMB_SM3CAPTCTRLB_CB0CNT1_MASK 0x0800U
  #define PWMB_SM3CAPTCTRLB_CB0CNT2_MASK 0x1000U
  #define PWMB_SM3CAPTCTRLB_CB1CNT0_MASK 0x2000U
  #define PWMB_SM3CAPTCTRLB_CB1CNT1_MASK 0x4000U
  #define PWMB_SM3CAPTCTRLB_CB1CNT2_MASK 0x8000U
  #define PWMB_SM3CAPTCTRLB_EDGB0_MASK  0x0CU
  #define PWMB_SM3CAPTCTRLB_EDGB0_BITNUM 0x02U
  #define PWMB_SM3CAPTCTRLB_EDGB1_MASK  0x30U
  #define PWMB_SM3CAPTCTRLB_EDGB1_BITNUM 0x04U
  #define PWMB_SM3CAPTCTRLB_CFBWM_MASK  0x0300U
  #define PWMB_SM3CAPTCTRLB_CFBWM_BITNUM 0x08U
  #define PWMB_SM3CAPTCTRLB_CB0CNT_MASK 0x1C00U
  #define PWMB_SM3CAPTCTRLB_CB0CNT_BITNUM 0x0AU
  #define PWMB_SM3CAPTCTRLB_CB1CNT_MASK 0xE000U
  #define PWMB_SM3CAPTCTRLB_CB1CNT_BITNUM 0x0DU
  #define PWMB_SM3CAPTCTRLB             (*((volatile word *)0x0000E7AC))


  /*** PWMB_SM3CAPTCOMPB - Capture Compare B Register; 0x0000E7AD ***/
  union {
    word Word;
  } PWMB_SM3CAPTCOMPB_STR;

  #define PWMB_SM3CAPTCOMPB_EDGCMPB0_MASK 0x01U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB1_MASK 0x02U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB2_MASK 0x04U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB3_MASK 0x08U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB4_MASK 0x10U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB5_MASK 0x20U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB6_MASK 0x40U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB7_MASK 0x80U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB0_MASK 0x0100U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB1_MASK 0x0200U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB2_MASK 0x0400U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB3_MASK 0x0800U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB4_MASK 0x1000U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB5_MASK 0x2000U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB6_MASK 0x4000U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB7_MASK 0x8000U
  #define PWMB_SM3CAPTCOMPB_EDGCMPB_MASK 0xFFU
  #define PWMB_SM3CAPTCOMPB_EDGCMPB_BITNUM 0x00U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB_MASK 0xFF00U
  #define PWMB_SM3CAPTCOMPB_EDGCNTB_BITNUM 0x08U
  #define PWMB_SM3CAPTCOMPB             (*((volatile word *)0x0000E7AD))


  /*** PWMB_SM3CAPTCTRLX - Capture Control X Register; 0x0000E7AE ***/
  union {
    word Word;
  } PWMB_SM3CAPTCTRLX_STR;

  #define PWMB_SM3CAPTCTRLX_ARMX_MASK   0x01U
  #define PWMB_SM3CAPTCTRLX_ONESHOTX_MASK 0x02U
  #define PWMB_SM3CAPTCTRLX_EDGX00_MASK 0x04U
  #define PWMB_SM3CAPTCTRLX_EDGX01_MASK 0x08U
  #define PWMB_SM3CAPTCTRLX_EDGX10_MASK 0x10U
  #define PWMB_SM3CAPTCTRLX_EDGX11_MASK 0x20U
  #define PWMB_SM3CAPTCTRLX_INP_SELX_MASK 0x40U
  #define PWMB_SM3CAPTCTRLX_EDGCNTX_EN_MASK 0x80U
  #define PWMB_SM3CAPTCTRLX_CFXWM0_MASK 0x0100U
  #define PWMB_SM3CAPTCTRLX_CFXWM1_MASK 0x0200U
  #define PWMB_SM3CAPTCTRLX_CX0CNT0_MASK 0x0400U
  #define PWMB_SM3CAPTCTRLX_CX0CNT1_MASK 0x0800U
  #define PWMB_SM3CAPTCTRLX_CX0CNT2_MASK 0x1000U
  #define PWMB_SM3CAPTCTRLX_CX1CNT0_MASK 0x2000U
  #define PWMB_SM3CAPTCTRLX_CX1CNT1_MASK 0x4000U
  #define PWMB_SM3CAPTCTRLX_CX1CNT2_MASK 0x8000U
  #define PWMB_SM3CAPTCTRLX_EDGX0_MASK  0x0CU
  #define PWMB_SM3CAPTCTRLX_EDGX0_BITNUM 0x02U
  #define PWMB_SM3CAPTCTRLX_EDGX1_MASK  0x30U
  #define PWMB_SM3CAPTCTRLX_EDGX1_BITNUM 0x04U
  #define PWMB_SM3CAPTCTRLX_CFXWM_MASK  0x0300U
  #define PWMB_SM3CAPTCTRLX_CFXWM_BITNUM 0x08U
  #define PWMB_SM3CAPTCTRLX_CX0CNT_MASK 0x1C00U
  #define PWMB_SM3CAPTCTRLX_CX0CNT_BITNUM 0x0AU
  #define PWMB_SM3CAPTCTRLX_CX1CNT_MASK 0xE000U
  #define PWMB_SM3CAPTCTRLX_CX1CNT_BITNUM 0x0DU
  #define PWMB_SM3CAPTCTRLX             (*((volatile word *)0x0000E7AE))


  /*** PWMB_SM3CAPTCOMPX - Capture Compare X Register; 0x0000E7AF ***/
  union {
    word Word;
  } PWMB_SM3CAPTCOMPX_STR;

  #define PWMB_SM3CAPTCOMPX_EDGCMPX0_MASK 0x01U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX1_MASK 0x02U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX2_MASK 0x04U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX3_MASK 0x08U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX4_MASK 0x10U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX5_MASK 0x20U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX6_MASK 0x40U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX7_MASK 0x80U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX0_MASK 0x0100U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX1_MASK 0x0200U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX2_MASK 0x0400U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX3_MASK 0x0800U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX4_MASK 0x1000U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX5_MASK 0x2000U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX6_MASK 0x4000U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX7_MASK 0x8000U
  #define PWMB_SM3CAPTCOMPX_EDGCMPX_MASK 0xFFU
  #define PWMB_SM3CAPTCOMPX_EDGCMPX_BITNUM 0x00U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX_MASK 0xFF00U
  #define PWMB_SM3CAPTCOMPX_EDGCNTX_BITNUM 0x08U
  #define PWMB_SM3CAPTCOMPX             (*((volatile word *)0x0000E7AF))


  /*** PWMB_SM3CVAL0 - Capture Value 0 Register; 0x0000E7B0 ***/
  union {
    word Word;
  } PWMB_SM3CVAL0_STR;

  #define PWMB_SM3CVAL0                 (*((volatile word *)0x0000E7B0))


  /*** PWMB_SM3CVAL0CYC - Capture Value 0 Cycle Register; 0x0000E7B1 ***/
  union {
    word Word;
  } PWMB_SM3CVAL0CYC_STR;

  #define PWMB_SM3CVAL0CYC_CVAL0CYC0_MASK 0x01U
  #define PWMB_SM3CVAL0CYC_CVAL0CYC1_MASK 0x02U
  #define PWMB_SM3CVAL0CYC_CVAL0CYC2_MASK 0x04U
  #define PWMB_SM3CVAL0CYC_CVAL0CYC3_MASK 0x08U
  #define PWMB_SM3CVAL0CYC_CVAL0CYC_MASK 0x0FU
  #define PWMB_SM3CVAL0CYC_CVAL0CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL0CYC              (*((volatile word *)0x0000E7B1))


  /*** PWMB_SM3CVAL1 - Capture Value 1 Register; 0x0000E7B2 ***/
  union {
    word Word;
  } PWMB_SM3CVAL1_STR;

  #define PWMB_SM3CVAL1                 (*((volatile word *)0x0000E7B2))


  /*** PWMB_SM3CVAL1CYC - Capture Value 1 Cycle Register; 0x0000E7B3 ***/
  union {
    word Word;
  } PWMB_SM3CVAL1CYC_STR;

  #define PWMB_SM3CVAL1CYC_CVAL1CYC0_MASK 0x01U
  #define PWMB_SM3CVAL1CYC_CVAL1CYC1_MASK 0x02U
  #define PWMB_SM3CVAL1CYC_CVAL1CYC2_MASK 0x04U
  #define PWMB_SM3CVAL1CYC_CVAL1CYC3_MASK 0x08U
  #define PWMB_SM3CVAL1CYC_CVAL1CYC_MASK 0x0FU
  #define PWMB_SM3CVAL1CYC_CVAL1CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL1CYC              (*((volatile word *)0x0000E7B3))


  /*** PWMB_SM3CVAL2 - Capture Value 2 Register; 0x0000E7B4 ***/
  union {
    word Word;
  } PWMB_SM3CVAL2_STR;

  #define PWMB_SM3CVAL2                 (*((volatile word *)0x0000E7B4))


  /*** PWMB_SM3CVAL2CYC - Capture Value 2 Cycle Register; 0x0000E7B5 ***/
  union {
    word Word;
  } PWMB_SM3CVAL2CYC_STR;

  #define PWMB_SM3CVAL2CYC_CVAL2CYC0_MASK 0x01U
  #define PWMB_SM3CVAL2CYC_CVAL2CYC1_MASK 0x02U
  #define PWMB_SM3CVAL2CYC_CVAL2CYC2_MASK 0x04U
  #define PWMB_SM3CVAL2CYC_CVAL2CYC3_MASK 0x08U
  #define PWMB_SM3CVAL2CYC_CVAL2CYC_MASK 0x0FU
  #define PWMB_SM3CVAL2CYC_CVAL2CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL2CYC              (*((volatile word *)0x0000E7B5))


  /*** PWMB_SM3CVAL3 - Capture Value 3 Register; 0x0000E7B6 ***/
  union {
    word Word;
  } PWMB_SM3CVAL3_STR;

  #define PWMB_SM3CVAL3                 (*((volatile word *)0x0000E7B6))


  /*** PWMB_SM3CVAL3CYC - Capture Value 3 Cycle Register; 0x0000E7B7 ***/
  union {
    word Word;
  } PWMB_SM3CVAL3CYC_STR;

  #define PWMB_SM3CVAL3CYC_CVAL3CYC0_MASK 0x01U
  #define PWMB_SM3CVAL3CYC_CVAL3CYC1_MASK 0x02U
  #define PWMB_SM3CVAL3CYC_CVAL3CYC2_MASK 0x04U
  #define PWMB_SM3CVAL3CYC_CVAL3CYC3_MASK 0x08U
  #define PWMB_SM3CVAL3CYC_CVAL3CYC_MASK 0x0FU
  #define PWMB_SM3CVAL3CYC_CVAL3CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL3CYC              (*((volatile word *)0x0000E7B7))


  /*** PWMB_SM3CVAL4 - Capture Value 4 Register; 0x0000E7B8 ***/
  union {
    word Word;
  } PWMB_SM3CVAL4_STR;

  #define PWMB_SM3CVAL4                 (*((volatile word *)0x0000E7B8))


  /*** PWMB_SM3CVAL4CYC - Capture Value 4 Cycle Register; 0x0000E7B9 ***/
  union {
    word Word;
  } PWMB_SM3CVAL4CYC_STR;

  #define PWMB_SM3CVAL4CYC_CVAL4CYC0_MASK 0x01U
  #define PWMB_SM3CVAL4CYC_CVAL4CYC1_MASK 0x02U
  #define PWMB_SM3CVAL4CYC_CVAL4CYC2_MASK 0x04U
  #define PWMB_SM3CVAL4CYC_CVAL4CYC3_MASK 0x08U
  #define PWMB_SM3CVAL4CYC_CVAL4CYC_MASK 0x0FU
  #define PWMB_SM3CVAL4CYC_CVAL4CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL4CYC              (*((volatile word *)0x0000E7B9))


  /*** PWMB_SM3CVAL5 - Capture Value 5 Register; 0x0000E7BA ***/
  union {
    word Word;
  } PWMB_SM3CVAL5_STR;

  #define PWMB_SM3CVAL5                 (*((volatile word *)0x0000E7BA))


  /*** PWMB_SM3CVAL5CYC - Capture Value 5 Cycle Register; 0x0000E7BB ***/
  union {
    word Word;
  } PWMB_SM3CVAL5CYC_STR;

  #define PWMB_SM3CVAL5CYC_CVAL5CYC0_MASK 0x01U
  #define PWMB_SM3CVAL5CYC_CVAL5CYC1_MASK 0x02U
  #define PWMB_SM3CVAL5CYC_CVAL5CYC2_MASK 0x04U
  #define PWMB_SM3CVAL5CYC_CVAL5CYC3_MASK 0x08U
  #define PWMB_SM3CVAL5CYC_CVAL5CYC_MASK 0x0FU
  #define PWMB_SM3CVAL5CYC_CVAL5CYC_BITNUM 0x00U
  #define PWMB_SM3CVAL5CYC              (*((volatile word *)0x0000E7BB))


  word Reserved31[4];                  /* Reserved (unused) registers */

  /*** PWMB_OUTEN - Output Enable Register; 0x0000E7C0 ***/
  union {
    word Word;
  } PWMB_OUTEN_STR;

  #define PWMB_OUTEN_PWMX_EN0_MASK      0x01U
  #define PWMB_OUTEN_PWMX_EN1_MASK      0x02U
  #define PWMB_OUTEN_PWMX_EN2_MASK      0x04U
  #define PWMB_OUTEN_PWMX_EN3_MASK      0x08U
  #define PWMB_OUTEN_PWMB_EN0_MASK      0x10U
  #define PWMB_OUTEN_PWMB_EN1_MASK      0x20U
  #define PWMB_OUTEN_PWMB_EN2_MASK      0x40U
  #define PWMB_OUTEN_PWMB_EN3_MASK      0x80U
  #define PWMB_OUTEN_PWMA_EN0_MASK      0x0100U
  #define PWMB_OUTEN_PWMA_EN1_MASK      0x0200U
  #define PWMB_OUTEN_PWMA_EN2_MASK      0x0400U
  #define PWMB_OUTEN_PWMA_EN3_MASK      0x0800U
  #define PWMB_OUTEN_PWMX_EN_MASK       0x0FU
  #define PWMB_OUTEN_PWMX_EN_BITNUM     0x00U
  #define PWMB_OUTEN_PWMB_EN_MASK       0xF0U
  #define PWMB_OUTEN_PWMB_EN_BITNUM     0x04U
  #define PWMB_OUTEN_PWMA_EN_MASK       0x0F00U
  #define PWMB_OUTEN_PWMA_EN_BITNUM     0x08U
  #define PWMB_OUTEN                    (*((volatile word *)0x0000E7C0))


  /*** PWMB_MASK - Mask Register; 0x0000E7C1 ***/
  union {
    word Word;
  } PWMB_MASK_STR;

  #define PWMB_MASK_MASKX0_MASK         0x01U
  #define PWMB_MASK_MASKX1_MASK         0x02U
  #define PWMB_MASK_MASKX2_MASK         0x04U
  #define PWMB_MASK_MASKX3_MASK         0x08U
  #define PWMB_MASK_MASKB0_MASK         0x10U
  #define PWMB_MASK_MASKB1_MASK         0x20U
  #define PWMB_MASK_MASKB2_MASK         0x40U
  #define PWMB_MASK_MASKB3_MASK         0x80U
  #define PWMB_MASK_MASKA0_MASK         0x0100U
  #define PWMB_MASK_MASKA1_MASK         0x0200U
  #define PWMB_MASK_MASKA2_MASK         0x0400U
  #define PWMB_MASK_MASKA3_MASK         0x0800U
  #define PWMB_MASK_MASKX_MASK          0x0FU
  #define PWMB_MASK_MASKX_BITNUM        0x00U
  #define PWMB_MASK_MASKB_MASK          0xF0U
  #define PWMB_MASK_MASKB_BITNUM        0x04U
  #define PWMB_MASK_MASKA_MASK          0x0F00U
  #define PWMB_MASK_MASKA_BITNUM        0x08U
  #define PWMB_MASK                     (*((volatile word *)0x0000E7C1))


  /*** PWMB_SWCOUT - Software Controlled Output Register; 0x0000E7C2 ***/
  union {
    word Word;
  } PWMB_SWCOUT_STR;

  #define PWMB_SWCOUT_SM0OUT45_MASK     0x01U
  #define PWMB_SWCOUT_SM0OUT23_MASK     0x02U
  #define PWMB_SWCOUT_SM1OUT45_MASK     0x04U
  #define PWMB_SWCOUT_SM1OUT23_MASK     0x08U
  #define PWMB_SWCOUT_SM2OUT45_MASK     0x10U
  #define PWMB_SWCOUT_SM2OUT23_MASK     0x20U
  #define PWMB_SWCOUT_SM3OUT45_MASK     0x40U
  #define PWMB_SWCOUT_SM3OUT23_MASK     0x80U
  #define PWMB_SWCOUT                   (*((volatile word *)0x0000E7C2))


  /*** PWMB_DTSRCSEL - Deadtime Source Select Register; 0x0000E7C3 ***/
  union {
    word Word;
  } PWMB_DTSRCSEL_STR;

  #define PWMB_DTSRCSEL_SM0SEL450_MASK  0x01U
  #define PWMB_DTSRCSEL_SM0SEL451_MASK  0x02U
  #define PWMB_DTSRCSEL_SM0SEL230_MASK  0x04U
  #define PWMB_DTSRCSEL_SM0SEL231_MASK  0x08U
  #define PWMB_DTSRCSEL_SM1SEL450_MASK  0x10U
  #define PWMB_DTSRCSEL_SM1SEL451_MASK  0x20U
  #define PWMB_DTSRCSEL_SM1SEL230_MASK  0x40U
  #define PWMB_DTSRCSEL_SM1SEL231_MASK  0x80U
  #define PWMB_DTSRCSEL_SM2SEL450_MASK  0x0100U
  #define PWMB_DTSRCSEL_SM2SEL451_MASK  0x0200U
  #define PWMB_DTSRCSEL_SM2SEL230_MASK  0x0400U
  #define PWMB_DTSRCSEL_SM2SEL231_MASK  0x0800U
  #define PWMB_DTSRCSEL_SM3SEL450_MASK  0x1000U
  #define PWMB_DTSRCSEL_SM3SEL451_MASK  0x2000U
  #define PWMB_DTSRCSEL_SM3SEL230_MASK  0x4000U
  #define PWMB_DTSRCSEL_SM3SEL231_MASK  0x8000U
  #define PWMB_DTSRCSEL_SM0SEL45_MASK   0x03U
  #define PWMB_DTSRCSEL_SM0SEL45_BITNUM 0x00U
  #define PWMB_DTSRCSEL_SM0SEL23_MASK   0x0CU
  #define PWMB_DTSRCSEL_SM0SEL23_BITNUM 0x02U
  #define PWMB_DTSRCSEL_SM1SEL45_MASK   0x30U
  #define PWMB_DTSRCSEL_SM1SEL45_BITNUM 0x04U
  #define PWMB_DTSRCSEL_SM1SEL23_MASK   0xC0U
  #define PWMB_DTSRCSEL_SM1SEL23_BITNUM 0x06U
  #define PWMB_DTSRCSEL_SM2SEL45_MASK   0x0300U
  #define PWMB_DTSRCSEL_SM2SEL45_BITNUM 0x08U
  #define PWMB_DTSRCSEL_SM2SEL23_MASK   0x0C00U
  #define PWMB_DTSRCSEL_SM2SEL23_BITNUM 0x0AU
  #define PWMB_DTSRCSEL_SM3SEL45_MASK   0x3000U
  #define PWMB_DTSRCSEL_SM3SEL45_BITNUM 0x0CU
  #define PWMB_DTSRCSEL_SM3SEL23_MASK   0xC000U
  #define PWMB_DTSRCSEL_SM3SEL23_BITNUM 0x0EU
  #define PWMB_DTSRCSEL                 (*((volatile word *)0x0000E7C3))


  /*** PWMB_MCTRL - Master Control Register; 0x0000E7C4 ***/
  union {
    word Word;
  } PWMB_MCTRL_STR;

  #define PWMB_MCTRL_LDOK0_MASK         0x01U
  #define PWMB_MCTRL_LDOK1_MASK         0x02U
  #define PWMB_MCTRL_LDOK2_MASK         0x04U
  #define PWMB_MCTRL_LDOK3_MASK         0x08U
  #define PWMB_MCTRL_CLDOK0_MASK        0x10U
  #define PWMB_MCTRL_CLDOK1_MASK        0x20U
  #define PWMB_MCTRL_CLDOK2_MASK        0x40U
  #define PWMB_MCTRL_CLDOK3_MASK        0x80U
  #define PWMB_MCTRL_RUN0_MASK          0x0100U
  #define PWMB_MCTRL_RUN1_MASK          0x0200U
  #define PWMB_MCTRL_RUN2_MASK          0x0400U
  #define PWMB_MCTRL_RUN3_MASK          0x0800U
  #define PWMB_MCTRL_IPOL0_MASK         0x1000U
  #define PWMB_MCTRL_IPOL1_MASK         0x2000U
  #define PWMB_MCTRL_IPOL2_MASK         0x4000U
  #define PWMB_MCTRL_IPOL3_MASK         0x8000U
  #define PWMB_MCTRL_LDOK_MASK          0x0FU
  #define PWMB_MCTRL_LDOK_BITNUM        0x00U
  #define PWMB_MCTRL_CLDOK_MASK         0xF0U
  #define PWMB_MCTRL_CLDOK_BITNUM       0x04U
  #define PWMB_MCTRL_RUN_MASK           0x0F00U
  #define PWMB_MCTRL_RUN_BITNUM         0x08U
  #define PWMB_MCTRL_IPOL_MASK          0xF000U
  #define PWMB_MCTRL_IPOL_BITNUM        0x0CU
  #define PWMB_MCTRL                    (*((volatile word *)0x0000E7C4))


  word Reserved32[1];                  /* Reserved (unused) registers */

  /*** PWMB_FCTRL0 - Fault Control Register; 0x0000E7C6 ***/
  union {
    word Word;
  } PWMB_FCTRL0_STR;

  #define PWMB_FCTRL0_FIE0_MASK         0x01U
  #define PWMB_FCTRL0_FIE1_MASK         0x02U
  #define PWMB_FCTRL0_FIE2_MASK         0x04U
  #define PWMB_FCTRL0_FIE3_MASK         0x08U
  #define PWMB_FCTRL0_FSAFE0_MASK       0x10U
  #define PWMB_FCTRL0_FSAFE1_MASK       0x20U
  #define PWMB_FCTRL0_FSAFE2_MASK       0x40U
  #define PWMB_FCTRL0_FSAFE3_MASK       0x80U
  #define PWMB_FCTRL0_FAUTO0_MASK       0x0100U
  #define PWMB_FCTRL0_FAUTO1_MASK       0x0200U
  #define PWMB_FCTRL0_FAUTO2_MASK       0x0400U
  #define PWMB_FCTRL0_FAUTO3_MASK       0x0800U
  #define PWMB_FCTRL0_FLVL0_MASK        0x1000U
  #define PWMB_FCTRL0_FLVL1_MASK        0x2000U
  #define PWMB_FCTRL0_FLVL2_MASK        0x4000U
  #define PWMB_FCTRL0_FLVL3_MASK        0x8000U
  #define PWMB_FCTRL0_FIE_MASK          0x0FU
  #define PWMB_FCTRL0_FIE_BITNUM        0x00U
  #define PWMB_FCTRL0_FSAFE_MASK        0xF0U
  #define PWMB_FCTRL0_FSAFE_BITNUM      0x04U
  #define PWMB_FCTRL0_FAUTO_MASK        0x0F00U
  #define PWMB_FCTRL0_FAUTO_BITNUM      0x08U
  #define PWMB_FCTRL0_FLVL_MASK         0xF000U
  #define PWMB_FCTRL0_FLVL_BITNUM       0x0CU
  #define PWMB_FCTRL0                   (*((volatile word *)0x0000E7C6))


  /*** PWMB_FSTS0 - Fault Status Register; 0x0000E7C7 ***/
  union {
    word Word;
  } PWMB_FSTS0_STR;

  #define PWMB_FSTS0_FFLAG0_MASK        0x01U
  #define PWMB_FSTS0_FFLAG1_MASK        0x02U
  #define PWMB_FSTS0_FFLAG2_MASK        0x04U
  #define PWMB_FSTS0_FFLAG3_MASK        0x08U
  #define PWMB_FSTS0_FFULL0_MASK        0x10U
  #define PWMB_FSTS0_FFULL1_MASK        0x20U
  #define PWMB_FSTS0_FFULL2_MASK        0x40U
  #define PWMB_FSTS0_FFULL3_MASK        0x80U
  #define PWMB_FSTS0_FFPIN0_MASK        0x0100U
  #define PWMB_FSTS0_FFPIN1_MASK        0x0200U
  #define PWMB_FSTS0_FFPIN2_MASK        0x0400U
  #define PWMB_FSTS0_FFPIN3_MASK        0x0800U
  #define PWMB_FSTS0_FHALF0_MASK        0x1000U
  #define PWMB_FSTS0_FHALF1_MASK        0x2000U
  #define PWMB_FSTS0_FHALF2_MASK        0x4000U
  #define PWMB_FSTS0_FHALF3_MASK        0x8000U
  #define PWMB_FSTS0_FFLAG_MASK         0x0FU
  #define PWMB_FSTS0_FFLAG_BITNUM       0x00U
  #define PWMB_FSTS0_FFULL_MASK         0xF0U
  #define PWMB_FSTS0_FFULL_BITNUM       0x04U
  #define PWMB_FSTS0_FFPIN_MASK         0x0F00U
  #define PWMB_FSTS0_FFPIN_BITNUM       0x08U
  #define PWMB_FSTS0_FHALF_MASK         0xF000U
  #define PWMB_FSTS0_FHALF_BITNUM       0x0CU
  #define PWMB_FSTS0                    (*((volatile word *)0x0000E7C7))


  /*** PWMB_FFILT0 - Fault Filter Register; 0x0000E7C8 ***/
  union {
    word Word;
  } PWMB_FFILT0_STR;

  #define PWMB_FFILT0_FILT_PER0_MASK    0x01U
  #define PWMB_FFILT0_FILT_PER1_MASK    0x02U
  #define PWMB_FFILT0_FILT_PER2_MASK    0x04U
  #define PWMB_FFILT0_FILT_PER3_MASK    0x08U
  #define PWMB_FFILT0_FILT_PER4_MASK    0x10U
  #define PWMB_FFILT0_FILT_PER5_MASK    0x20U
  #define PWMB_FFILT0_FILT_PER6_MASK    0x40U
  #define PWMB_FFILT0_FILT_PER7_MASK    0x80U
  #define PWMB_FFILT0_FILT_CNT0_MASK    0x0100U
  #define PWMB_FFILT0_FILT_CNT1_MASK    0x0200U
  #define PWMB_FFILT0_FILT_CNT2_MASK    0x0400U
  #define PWMB_FFILT0_GSTR_MASK         0x8000U
  #define PWMB_FFILT0_FILT_PER_MASK     0xFFU
  #define PWMB_FFILT0_FILT_PER_BITNUM   0x00U
  #define PWMB_FFILT0_FILT_CNT_MASK     0x0700U
  #define PWMB_FFILT0_FILT_CNT_BITNUM   0x08U
  #define PWMB_FFILT0                   (*((volatile word *)0x0000E7C8))


  /*** PWMB_FTST0 - Fault Test Register; 0x0000E7C9 ***/
  union {
    word Word;
  } PWMB_FTST0_STR;

  #define PWMB_FTST0_FTEST_MASK         0x01U
  #define PWMB_FTST0                    (*((volatile word *)0x0000E7C9))


  /*** PWMB_FCTRL1 - Fault Control Register; 0x0000E7CA ***/
  union {
    word Word;
  } PWMB_FCTRL1_STR;

  #define PWMB_FCTRL1_FIE0_MASK         0x01U
  #define PWMB_FCTRL1_FIE1_MASK         0x02U
  #define PWMB_FCTRL1_FIE2_MASK         0x04U
  #define PWMB_FCTRL1_FIE3_MASK         0x08U
  #define PWMB_FCTRL1_FSAFE0_MASK       0x10U
  #define PWMB_FCTRL1_FSAFE1_MASK       0x20U
  #define PWMB_FCTRL1_FSAFE2_MASK       0x40U
  #define PWMB_FCTRL1_FSAFE3_MASK       0x80U
  #define PWMB_FCTRL1_FAUTO0_MASK       0x0100U
  #define PWMB_FCTRL1_FAUTO1_MASK       0x0200U
  #define PWMB_FCTRL1_FAUTO2_MASK       0x0400U
  #define PWMB_FCTRL1_FAUTO3_MASK       0x0800U
  #define PWMB_FCTRL1_FLVL0_MASK        0x1000U
  #define PWMB_FCTRL1_FLVL1_MASK        0x2000U
  #define PWMB_FCTRL1_FLVL2_MASK        0x4000U
  #define PWMB_FCTRL1_FLVL3_MASK        0x8000U
  #define PWMB_FCTRL1_FIE_MASK          0x0FU
  #define PWMB_FCTRL1_FIE_BITNUM        0x00U
  #define PWMB_FCTRL1_FSAFE_MASK        0xF0U
  #define PWMB_FCTRL1_FSAFE_BITNUM      0x04U
  #define PWMB_FCTRL1_FAUTO_MASK        0x0F00U
  #define PWMB_FCTRL1_FAUTO_BITNUM      0x08U
  #define PWMB_FCTRL1_FLVL_MASK         0xF000U
  #define PWMB_FCTRL1_FLVL_BITNUM       0x0CU
  #define PWMB_FCTRL1                   (*((volatile word *)0x0000E7CA))


  /*** PWMB_FSTS1 - Fault Status Register; 0x0000E7CB ***/
  union {
    word Word;
  } PWMB_FSTS1_STR;

  #define PWMB_FSTS1_FFLAG0_MASK        0x01U
  #define PWMB_FSTS1_FFLAG1_MASK        0x02U
  #define PWMB_FSTS1_FFLAG2_MASK        0x04U
  #define PWMB_FSTS1_FFLAG3_MASK        0x08U
  #define PWMB_FSTS1_FFULL0_MASK        0x10U
  #define PWMB_FSTS1_FFULL1_MASK        0x20U
  #define PWMB_FSTS1_FFULL2_MASK        0x40U
  #define PWMB_FSTS1_FFULL3_MASK        0x80U
  #define PWMB_FSTS1_FFPIN0_MASK        0x0100U
  #define PWMB_FSTS1_FFPIN1_MASK        0x0200U
  #define PWMB_FSTS1_FFPIN2_MASK        0x0400U
  #define PWMB_FSTS1_FFPIN3_MASK        0x0800U
  #define PWMB_FSTS1_FHALF0_MASK        0x1000U
  #define PWMB_FSTS1_FHALF1_MASK        0x2000U
  #define PWMB_FSTS1_FHALF2_MASK        0x4000U
  #define PWMB_FSTS1_FHALF3_MASK        0x8000U
  #define PWMB_FSTS1_FFLAG_MASK         0x0FU
  #define PWMB_FSTS1_FFLAG_BITNUM       0x00U
  #define PWMB_FSTS1_FFULL_MASK         0xF0U
  #define PWMB_FSTS1_FFULL_BITNUM       0x04U
  #define PWMB_FSTS1_FFPIN_MASK         0x0F00U
  #define PWMB_FSTS1_FFPIN_BITNUM       0x08U
  #define PWMB_FSTS1_FHALF_MASK         0xF000U
  #define PWMB_FSTS1_FHALF_BITNUM       0x0CU
  #define PWMB_FSTS1                    (*((volatile word *)0x0000E7CB))


  /*** PWMB_FFILT1 - Fault Filter Register; 0x0000E7CC ***/
  union {
    word Word;
  } PWMB_FFILT1_STR;

  #define PWMB_FFILT1_FILT_PER0_MASK    0x01U
  #define PWMB_FFILT1_FILT_PER1_MASK    0x02U
  #define PWMB_FFILT1_FILT_PER2_MASK    0x04U
  #define PWMB_FFILT1_FILT_PER3_MASK    0x08U
  #define PWMB_FFILT1_FILT_PER4_MASK    0x10U
  #define PWMB_FFILT1_FILT_PER5_MASK    0x20U
  #define PWMB_FFILT1_FILT_PER6_MASK    0x40U
  #define PWMB_FFILT1_FILT_PER7_MASK    0x80U
  #define PWMB_FFILT1_FILT_CNT0_MASK    0x0100U
  #define PWMB_FFILT1_FILT_CNT1_MASK    0x0200U
  #define PWMB_FFILT1_FILT_CNT2_MASK    0x0400U
  #define PWMB_FFILT1_GSTR_MASK         0x8000U
  #define PWMB_FFILT1_FILT_PER_MASK     0xFFU
  #define PWMB_FFILT1_FILT_PER_BITNUM   0x00U
  #define PWMB_FFILT1_FILT_CNT_MASK     0x0700U
  #define PWMB_FFILT1_FILT_CNT_BITNUM   0x08U
  #define PWMB_FFILT1                   (*((volatile word *)0x0000E7CC))


  /*** PWMB_FTST1 - Fault Test Register; 0x0000E7CD ***/
  union {
    word Word;
  } PWMB_FTST1_STR;

  #define PWMB_FTST1_FTEST_MASK         0x01U
  #define PWMB_FTST1                    (*((volatile word *)0x0000E7CD))


} PWMB_PRPH;
/******************************************
*** Peripheral CAN
*******************************************/
typedef volatile struct {
  /*** CAN_MCR - Module Configuration Register; 0x0000E800 ***/
  union {
    dword Dword;
  } CAN_MCR_STR;

  #define CAN_MCR_MAXMB0_MASK           0x01UL
  #define CAN_MCR_MAXMB1_MASK           0x02UL
  #define CAN_MCR_MAXMB2_MASK           0x04UL
  #define CAN_MCR_MAXMB3_MASK           0x08UL
  #define CAN_MCR_MAXMB4_MASK           0x10UL
  #define CAN_MCR_MAXMB5_MASK           0x20UL
  #define CAN_MCR_MAXMB6_MASK           0x40UL
  #define CAN_MCR_IDAM0_MASK            0x0100UL
  #define CAN_MCR_IDAM1_MASK            0x0200UL
  #define CAN_MCR_AEN_MASK              0x1000UL
  #define CAN_MCR_LPRIOEN_MASK          0x2000UL
  #define CAN_MCR_IRMQ_MASK             0x00010000UL
  #define CAN_MCR_SRXDIS_MASK           0x00020000UL
  #define CAN_MCR_DOZE_MASK             0x00040000UL
  #define CAN_MCR_WAKSRC_MASK           0x00080000UL
  #define CAN_MCR_LPMACK_MASK           0x00100000UL
  #define CAN_MCR_WRNEN_MASK            0x00200000UL
  #define CAN_MCR_SLFWAK_MASK           0x00400000UL
  #define CAN_MCR_SUPV_MASK             0x00800000UL
  #define CAN_MCR_FRZACK_MASK           0x01000000UL
  #define CAN_MCR_SOFTRST_MASK          0x02000000UL
  #define CAN_MCR_WAKMSK_MASK           0x04000000UL
  #define CAN_MCR_NOTRDY_MASK           0x08000000UL
  #define CAN_MCR_HALT_MASK             0x10000000UL
  #define CAN_MCR_RFEN_MASK             0x20000000UL
  #define CAN_MCR_FRZ_MASK              0x40000000UL
  #define CAN_MCR_MDIS_MASK             0x80000000UL
  #define CAN_MCR_MAXMB_MASK            0x7FUL
  #define CAN_MCR_MAXMB_BITNUM          0x00U
  #define CAN_MCR_IDAM_MASK             0x0300UL
  #define CAN_MCR_IDAM_BITNUM           0x08U
  #define CAN_MCR                       (*((volatile dword *)0x0000E800))


  /*** CAN_CTRL1 - Control 1 Register; 0x0000E802 ***/
  union {
    dword Dword;
  } CAN_CTRL1_STR;

  #define CAN_CTRL1_PROPSEG0_MASK       0x01UL
  #define CAN_CTRL1_PROPSEG1_MASK       0x02UL
  #define CAN_CTRL1_PROPSEG2_MASK       0x04UL
  #define CAN_CTRL1_LOM_MASK            0x08UL
  #define CAN_CTRL1_LBUF_MASK           0x10UL
  #define CAN_CTRL1_TSYN_MASK           0x20UL
  #define CAN_CTRL1_BOFFREC_MASK        0x40UL
  #define CAN_CTRL1_SMP_MASK            0x80UL
  #define CAN_CTRL1_RWRNMSK_MASK        0x0400UL
  #define CAN_CTRL1_TWRNMSK_MASK        0x0800UL
  #define CAN_CTRL1_LPB_MASK            0x1000UL
  #define CAN_CTRL1_CLKSRC_MASK         0x2000UL
  #define CAN_CTRL1_ERRMSK_MASK         0x4000UL
  #define CAN_CTRL1_BOFFMSK_MASK        0x8000UL
  #define CAN_CTRL1_PSEG20_MASK         0x00010000UL
  #define CAN_CTRL1_PSEG21_MASK         0x00020000UL
  #define CAN_CTRL1_PSEG22_MASK         0x00040000UL
  #define CAN_CTRL1_PSEG10_MASK         0x00080000UL
  #define CAN_CTRL1_PSEG11_MASK         0x00100000UL
  #define CAN_CTRL1_PSEG12_MASK         0x00200000UL
  #define CAN_CTRL1_RJW0_MASK           0x00400000UL
  #define CAN_CTRL1_RJW1_MASK           0x00800000UL
  #define CAN_CTRL1_PRESDIV0_MASK       0x01000000UL
  #define CAN_CTRL1_PRESDIV1_MASK       0x02000000UL
  #define CAN_CTRL1_PRESDIV2_MASK       0x04000000UL
  #define CAN_CTRL1_PRESDIV3_MASK       0x08000000UL
  #define CAN_CTRL1_PRESDIV4_MASK       0x10000000UL
  #define CAN_CTRL1_PRESDIV5_MASK       0x20000000UL
  #define CAN_CTRL1_PRESDIV6_MASK       0x40000000UL
  #define CAN_CTRL1_PRESDIV7_MASK       0x80000000UL
  #define CAN_CTRL1_PROPSEG_MASK        0x07UL
  #define CAN_CTRL1_PROPSEG_BITNUM      0x00U
  #define CAN_CTRL1_PSEG2_MASK          0x00070000UL
  #define CAN_CTRL1_PSEG2_BITNUM        0x10U
  #define CAN_CTRL1_PSEG1_MASK          0x00380000UL
  #define CAN_CTRL1_PSEG1_BITNUM        0x13U
  #define CAN_CTRL1_RJW_MASK            0x00C00000UL
  #define CAN_CTRL1_RJW_BITNUM          0x16U
  #define CAN_CTRL1_PRESDIV_MASK        0xFF000000UL
  #define CAN_CTRL1_PRESDIV_BITNUM      0x18U
  #define CAN_CTRL1                     (*((volatile dword *)0x0000E802))


  /*** CAN_TIMER - Free Running Timer; 0x0000E804 ***/
  union {
    dword Dword;
  } CAN_TIMER_STR;

  #define CAN_TIMER_TIMER0_MASK         0x01UL
  #define CAN_TIMER_TIMER1_MASK         0x02UL
  #define CAN_TIMER_TIMER2_MASK         0x04UL
  #define CAN_TIMER_TIMER3_MASK         0x08UL
  #define CAN_TIMER_TIMER4_MASK         0x10UL
  #define CAN_TIMER_TIMER5_MASK         0x20UL
  #define CAN_TIMER_TIMER6_MASK         0x40UL
  #define CAN_TIMER_TIMER7_MASK         0x80UL
  #define CAN_TIMER_TIMER8_MASK         0x0100UL
  #define CAN_TIMER_TIMER9_MASK         0x0200UL
  #define CAN_TIMER_TIMER10_MASK        0x0400UL
  #define CAN_TIMER_TIMER11_MASK        0x0800UL
  #define CAN_TIMER_TIMER12_MASK        0x1000UL
  #define CAN_TIMER_TIMER13_MASK        0x2000UL
  #define CAN_TIMER_TIMER14_MASK        0x4000UL
  #define CAN_TIMER_TIMER15_MASK        0x8000UL
  #define CAN_TIMER_TIMER_MASK          0xFFFFUL
  #define CAN_TIMER_TIMER_BITNUM        0x00U
  #define CAN_TIMER                     (*((volatile dword *)0x0000E804))


  dword Reserved0[1];                  /* Reserved (unused) registers */

  /*** CAN_RXMGMASK - Rx Mailboxes Global Mask Register; 0x0000E808 ***/
  union {
    dword Dword;
  } CAN_RXMGMASK_STR;

  #define CAN_RXMGMASK                  (*((volatile dword *)0x0000E808))


  /*** CAN_RX14MASK - Rx 14 Mask Register; 0x0000E80A ***/
  union {
    dword Dword;
  } CAN_RX14MASK_STR;

  #define CAN_RX14MASK                  (*((volatile dword *)0x0000E80A))


  /*** CAN_RX15MASK - Rx 15 Mask Register; 0x0000E80C ***/
  union {
    dword Dword;
  } CAN_RX15MASK_STR;

  #define CAN_RX15MASK                  (*((volatile dword *)0x0000E80C))


  /*** CAN_ECR - Error Counter; 0x0000E80E ***/
  union {
    dword Dword;
  } CAN_ECR_STR;

  #define CAN_ECR_TXERRCNT0_MASK        0x01UL
  #define CAN_ECR_TXERRCNT1_MASK        0x02UL
  #define CAN_ECR_TXERRCNT2_MASK        0x04UL
  #define CAN_ECR_TXERRCNT3_MASK        0x08UL
  #define CAN_ECR_TXERRCNT4_MASK        0x10UL
  #define CAN_ECR_TXERRCNT5_MASK        0x20UL
  #define CAN_ECR_TXERRCNT6_MASK        0x40UL
  #define CAN_ECR_TXERRCNT7_MASK        0x80UL
  #define CAN_ECR_RXERRCNT0_MASK        0x0100UL
  #define CAN_ECR_RXERRCNT1_MASK        0x0200UL
  #define CAN_ECR_RXERRCNT2_MASK        0x0400UL
  #define CAN_ECR_RXERRCNT3_MASK        0x0800UL
  #define CAN_ECR_RXERRCNT4_MASK        0x1000UL
  #define CAN_ECR_RXERRCNT5_MASK        0x2000UL
  #define CAN_ECR_RXERRCNT6_MASK        0x4000UL
  #define CAN_ECR_RXERRCNT7_MASK        0x8000UL
  #define CAN_ECR_TXERRCNT_MASK         0xFFUL
  #define CAN_ECR_TXERRCNT_BITNUM       0x00U
  #define CAN_ECR_RXERRCNT_MASK         0xFF00UL
  #define CAN_ECR_RXERRCNT_BITNUM       0x08U
  #define CAN_ECR                       (*((volatile dword *)0x0000E80E))


  /*** CAN_ESR1 - Error and Status 1 Register; 0x0000E810 ***/
  union {
    dword Dword;
  } CAN_ESR1_STR;

  #define CAN_ESR1_WAKINT_MASK          0x01UL
  #define CAN_ESR1_ERRINT_MASK          0x02UL
  #define CAN_ESR1_BOFFINT_MASK         0x04UL
  #define CAN_ESR1_RX_MASK              0x08UL
  #define CAN_ESR1_FLTCONF0_MASK        0x10UL
  #define CAN_ESR1_FLTCONF1_MASK        0x20UL
  #define CAN_ESR1_TX_MASK              0x40UL
  #define CAN_ESR1_IDLE_MASK            0x80UL
  #define CAN_ESR1_RXWRN_MASK           0x0100UL
  #define CAN_ESR1_TXWRN_MASK           0x0200UL
  #define CAN_ESR1_STFERR_MASK          0x0400UL
  #define CAN_ESR1_FRMERR_MASK          0x0800UL
  #define CAN_ESR1_CRCERR_MASK          0x1000UL
  #define CAN_ESR1_ACKERR_MASK          0x2000UL
  #define CAN_ESR1_BIT0ERR_MASK         0x4000UL
  #define CAN_ESR1_BIT1ERR_MASK         0x8000UL
  #define CAN_ESR1_RWRNINT_MASK         0x00010000UL
  #define CAN_ESR1_TWRNINT_MASK         0x00020000UL
  #define CAN_ESR1_SYNCH_MASK           0x00040000UL
  #define CAN_ESR1_FLTCONF_MASK         0x30UL
  #define CAN_ESR1_FLTCONF_BITNUM       0x04U
  #define CAN_ESR1                      (*((volatile dword *)0x0000E810))


  /*** CAN_IMASK2 - Interrupt Masks 2 Register; 0x0000E812 ***/
  union {
    dword Dword;
  } CAN_IMASK2_STR;

  #define CAN_IMASK2                    (*((volatile dword *)0x0000E812))


  /*** CAN_IMASK1 - Interrupt Masks 1 Register; 0x0000E814 ***/
  union {
    dword Dword;
  } CAN_IMASK1_STR;

  #define CAN_IMASK1                    (*((volatile dword *)0x0000E814))


  /*** CAN_IFLAG2 - Interrupt Flags 2 Register; 0x0000E816 ***/
  union {
    dword Dword;
  } CAN_IFLAG2_STR;

  #define CAN_IFLAG2                    (*((volatile dword *)0x0000E816))


  /*** CAN_IFLAG1 - Interrupt Flags 1 Register; 0x0000E818 ***/
  union {
    dword Dword;
  } CAN_IFLAG1_STR;

  #define CAN_IFLAG1_BUF4TO0I0_MASK     0x01UL
  #define CAN_IFLAG1_BUF4TO0I1_MASK     0x02UL
  #define CAN_IFLAG1_BUF4TO0I2_MASK     0x04UL
  #define CAN_IFLAG1_BUF4TO0I3_MASK     0x08UL
  #define CAN_IFLAG1_BUF4TO0I4_MASK     0x10UL
  #define CAN_IFLAG1_BUF5I_MASK         0x20UL
  #define CAN_IFLAG1_BUF6I_MASK         0x40UL
  #define CAN_IFLAG1_BUF7I_MASK         0x80UL
  #define CAN_IFLAG1_BUF31TO8I0_MASK    0x0100UL
  #define CAN_IFLAG1_BUF31TO8I1_MASK    0x0200UL
  #define CAN_IFLAG1_BUF31TO8I2_MASK    0x0400UL
  #define CAN_IFLAG1_BUF31TO8I3_MASK    0x0800UL
  #define CAN_IFLAG1_BUF31TO8I4_MASK    0x1000UL
  #define CAN_IFLAG1_BUF31TO8I5_MASK    0x2000UL
  #define CAN_IFLAG1_BUF31TO8I6_MASK    0x4000UL
  #define CAN_IFLAG1_BUF31TO8I7_MASK    0x8000UL
  #define CAN_IFLAG1_BUF31TO8I8_MASK    0x00010000UL
  #define CAN_IFLAG1_BUF31TO8I9_MASK    0x00020000UL
  #define CAN_IFLAG1_BUF31TO8I10_MASK   0x00040000UL
  #define CAN_IFLAG1_BUF31TO8I11_MASK   0x00080000UL
  #define CAN_IFLAG1_BUF31TO8I12_MASK   0x00100000UL
  #define CAN_IFLAG1_BUF31TO8I13_MASK   0x00200000UL
  #define CAN_IFLAG1_BUF31TO8I14_MASK   0x00400000UL
  #define CAN_IFLAG1_BUF31TO8I15_MASK   0x00800000UL
  #define CAN_IFLAG1_BUF31TO8I16_MASK   0x01000000UL
  #define CAN_IFLAG1_BUF31TO8I17_MASK   0x02000000UL
  #define CAN_IFLAG1_BUF31TO8I18_MASK   0x04000000UL
  #define CAN_IFLAG1_BUF31TO8I19_MASK   0x08000000UL
  #define CAN_IFLAG1_BUF31TO8I20_MASK   0x10000000UL
  #define CAN_IFLAG1_BUF31TO8I21_MASK   0x20000000UL
  #define CAN_IFLAG1_BUF31TO8I22_MASK   0x40000000UL
  #define CAN_IFLAG1_BUF31TO8I23_MASK   0x80000000UL
  #define CAN_IFLAG1_BUF4TO0I_MASK      0x1FUL
  #define CAN_IFLAG1_BUF4TO0I_BITNUM    0x00U
  #define CAN_IFLAG1_BUF31TO8I_MASK     0xFFFFFF00UL
  #define CAN_IFLAG1_BUF31TO8I_BITNUM   0x08U
  #define CAN_IFLAG1                    (*((volatile dword *)0x0000E818))


  /*** CAN_CTRL2 - Control 2 Register; 0x0000E81A ***/
  union {
    dword Dword;
  } CAN_CTRL2_STR;

  #define CAN_CTRL2_EACEN_MASK          0x00010000UL
  #define CAN_CTRL2_RRS_MASK            0x00020000UL
  #define CAN_CTRL2_MRP_MASK            0x00040000UL
  #define CAN_CTRL2_TASD0_MASK          0x00080000UL
  #define CAN_CTRL2_TASD1_MASK          0x00100000UL
  #define CAN_CTRL2_TASD2_MASK          0x00200000UL
  #define CAN_CTRL2_TASD3_MASK          0x00400000UL
  #define CAN_CTRL2_TASD4_MASK          0x00800000UL
  #define CAN_CTRL2_RFFN0_MASK          0x01000000UL
  #define CAN_CTRL2_RFFN1_MASK          0x02000000UL
  #define CAN_CTRL2_RFFN2_MASK          0x04000000UL
  #define CAN_CTRL2_RFFN3_MASK          0x08000000UL
  #define CAN_CTRL2_WRMFRZ_MASK         0x10000000UL
  #define CAN_CTRL2_TASD_MASK           0x00F80000UL
  #define CAN_CTRL2_TASD_BITNUM         0x13U
  #define CAN_CTRL2_RFFN_MASK           0x0F000000UL
  #define CAN_CTRL2_RFFN_BITNUM         0x18U
  #define CAN_CTRL2                     (*((volatile dword *)0x0000E81A))


  /*** CAN_ESR2 - Error and Status 2 Register; 0x0000E81C ***/
  union {
    dword Dword;
  } CAN_ESR2_STR;

  #define CAN_ESR2_IMB_MASK             0x2000UL
  #define CAN_ESR2_VPS_MASK             0x4000UL
  #define CAN_ESR2_LPTM0_MASK           0x00010000UL
  #define CAN_ESR2_LPTM1_MASK           0x00020000UL
  #define CAN_ESR2_LPTM2_MASK           0x00040000UL
  #define CAN_ESR2_LPTM3_MASK           0x00080000UL
  #define CAN_ESR2_LPTM4_MASK           0x00100000UL
  #define CAN_ESR2_LPTM5_MASK           0x00200000UL
  #define CAN_ESR2_LPTM6_MASK           0x00400000UL
  #define CAN_ESR2_LPTM_MASK            0x007F0000UL
  #define CAN_ESR2_LPTM_BITNUM          0x10U
  #define CAN_ESR2                      (*((volatile dword *)0x0000E81C))


  dword Reserved1[2];                  /* Reserved (unused) registers */

  /*** CAN_CRCR - CRC Register; 0x0000E822 ***/
  union {
    dword Dword;
  } CAN_CRCR_STR;

  #define CAN_CRCR_TXCRC0_MASK          0x01UL
  #define CAN_CRCR_TXCRC1_MASK          0x02UL
  #define CAN_CRCR_TXCRC2_MASK          0x04UL
  #define CAN_CRCR_TXCRC3_MASK          0x08UL
  #define CAN_CRCR_TXCRC4_MASK          0x10UL
  #define CAN_CRCR_TXCRC5_MASK          0x20UL
  #define CAN_CRCR_TXCRC6_MASK          0x40UL
  #define CAN_CRCR_TXCRC7_MASK          0x80UL
  #define CAN_CRCR_TXCRC8_MASK          0x0100UL
  #define CAN_CRCR_TXCRC9_MASK          0x0200UL
  #define CAN_CRCR_TXCRC10_MASK         0x0400UL
  #define CAN_CRCR_TXCRC11_MASK         0x0800UL
  #define CAN_CRCR_TXCRC12_MASK         0x1000UL
  #define CAN_CRCR_TXCRC13_MASK         0x2000UL
  #define CAN_CRCR_TXCRC14_MASK         0x4000UL
  #define CAN_CRCR_MBCRC0_MASK          0x00010000UL
  #define CAN_CRCR_MBCRC1_MASK          0x00020000UL
  #define CAN_CRCR_MBCRC2_MASK          0x00040000UL
  #define CAN_CRCR_MBCRC3_MASK          0x00080000UL
  #define CAN_CRCR_MBCRC4_MASK          0x00100000UL
  #define CAN_CRCR_MBCRC5_MASK          0x00200000UL
  #define CAN_CRCR_MBCRC6_MASK          0x00400000UL
  #define CAN_CRCR_TXCRC_MASK           0x7FFFUL
  #define CAN_CRCR_TXCRC_BITNUM         0x00U
  #define CAN_CRCR_MBCRC_MASK           0x007F0000UL
  #define CAN_CRCR_MBCRC_BITNUM         0x10U
  #define CAN_CRCR                      (*((volatile dword *)0x0000E822))


  /*** CAN_RXFGMASK - Rx FIFO Global Mask Register; 0x0000E824 ***/
  union {
    dword Dword;
  } CAN_RXFGMASK_STR;

  #define CAN_RXFGMASK                  (*((volatile dword *)0x0000E824))


  /*** CAN_RXFIR - Rx FIFO Information Register; 0x0000E826 ***/
  union {
    dword Dword;
  } CAN_RXFIR_STR;

  #define CAN_RXFIR_IDHIT0_MASK         0x01UL
  #define CAN_RXFIR_IDHIT1_MASK         0x02UL
  #define CAN_RXFIR_IDHIT2_MASK         0x04UL
  #define CAN_RXFIR_IDHIT3_MASK         0x08UL
  #define CAN_RXFIR_IDHIT4_MASK         0x10UL
  #define CAN_RXFIR_IDHIT5_MASK         0x20UL
  #define CAN_RXFIR_IDHIT6_MASK         0x40UL
  #define CAN_RXFIR_IDHIT7_MASK         0x80UL
  #define CAN_RXFIR_IDHIT8_MASK         0x0100UL
  #define CAN_RXFIR_IDHIT_MASK          0x01FFUL
  #define CAN_RXFIR_IDHIT_BITNUM        0x00U
  #define CAN_RXFIR                     (*((volatile dword *)0x0000E826))


  dword Reserved2[12];                 /* Reserved (unused) registers */

  /*** CAN_CS0 - Message Buffer 0 CS Register; 0x0000E840 ***/
  union {
    dword Dword;
  } CAN_CS0_STR;

  #define CAN_CS0_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS0_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS0_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS0_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS0_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS0_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS0_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS0_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS0_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS0_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS0_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS0_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS0_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS0_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS0_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS0_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS0_DLC0_MASK             0x00010000UL
  #define CAN_CS0_DLC1_MASK             0x00020000UL
  #define CAN_CS0_DLC2_MASK             0x00040000UL
  #define CAN_CS0_DLC3_MASK             0x00080000UL
  #define CAN_CS0_RTR_MASK              0x00100000UL
  #define CAN_CS0_IDE_MASK              0x00200000UL
  #define CAN_CS0_SRR_MASK              0x00400000UL
  #define CAN_CS0_CODE0_MASK            0x01000000UL
  #define CAN_CS0_CODE1_MASK            0x02000000UL
  #define CAN_CS0_CODE2_MASK            0x04000000UL
  #define CAN_CS0_CODE3_MASK            0x08000000UL
  #define CAN_CS0_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS0_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS0_DLC_MASK              0x000F0000UL
  #define CAN_CS0_DLC_BITNUM            0x10U
  #define CAN_CS0_CODE_MASK             0x0F000000UL
  #define CAN_CS0_CODE_BITNUM           0x18U
  #define CAN_CS0                       (*((volatile dword *)0x0000E840))


  /*** CAN_ID0 - Message Buffer 0 ID Register; 0x0000E842 ***/
  union {
    dword Dword;
  } CAN_ID0_STR;

  #define CAN_ID0_EXT0_MASK             0x01UL
  #define CAN_ID0_EXT1_MASK             0x02UL
  #define CAN_ID0_EXT2_MASK             0x04UL
  #define CAN_ID0_EXT3_MASK             0x08UL
  #define CAN_ID0_EXT4_MASK             0x10UL
  #define CAN_ID0_EXT5_MASK             0x20UL
  #define CAN_ID0_EXT6_MASK             0x40UL
  #define CAN_ID0_EXT7_MASK             0x80UL
  #define CAN_ID0_EXT8_MASK             0x0100UL
  #define CAN_ID0_EXT9_MASK             0x0200UL
  #define CAN_ID0_EXT10_MASK            0x0400UL
  #define CAN_ID0_EXT11_MASK            0x0800UL
  #define CAN_ID0_EXT12_MASK            0x1000UL
  #define CAN_ID0_EXT13_MASK            0x2000UL
  #define CAN_ID0_EXT14_MASK            0x4000UL
  #define CAN_ID0_EXT15_MASK            0x8000UL
  #define CAN_ID0_EXT16_MASK            0x00010000UL
  #define CAN_ID0_EXT17_MASK            0x00020000UL
  #define CAN_ID0_STD0_MASK             0x00040000UL
  #define CAN_ID0_STD1_MASK             0x00080000UL
  #define CAN_ID0_STD2_MASK             0x00100000UL
  #define CAN_ID0_STD3_MASK             0x00200000UL
  #define CAN_ID0_STD4_MASK             0x00400000UL
  #define CAN_ID0_STD5_MASK             0x00800000UL
  #define CAN_ID0_STD6_MASK             0x01000000UL
  #define CAN_ID0_STD7_MASK             0x02000000UL
  #define CAN_ID0_STD8_MASK             0x04000000UL
  #define CAN_ID0_STD9_MASK             0x08000000UL
  #define CAN_ID0_STD10_MASK            0x10000000UL
  #define CAN_ID0_PRIO0_MASK            0x20000000UL
  #define CAN_ID0_PRIO1_MASK            0x40000000UL
  #define CAN_ID0_PRIO2_MASK            0x80000000UL
  #define CAN_ID0_EXT_MASK              0x0003FFFFUL
  #define CAN_ID0_EXT_BITNUM            0x00U
  #define CAN_ID0_STD_MASK              0x1FFC0000UL
  #define CAN_ID0_STD_BITNUM            0x12U
  #define CAN_ID0_PRIO_MASK             0xE0000000UL
  #define CAN_ID0_PRIO_BITNUM           0x1DU
  #define CAN_ID0                       (*((volatile dword *)0x0000E842))


  /*** CAN_WORD00 - Message Buffer 0 WORD0 Register; 0x0000E844 ***/
  union {
    dword Dword;
  } CAN_WORD00_STR;

  #define CAN_WORD00_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD00_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD00_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD00_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD00_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD00_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD00_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD00_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD00_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD00_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD00_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD00_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD00_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD00_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD00_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD00_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD00_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD00_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD00_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD00_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD00_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD00_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD00_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD00_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD00_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD00_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD00_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD00_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD00_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD00_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD00_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD00_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD00_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD00_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD00_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD00_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD00_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD00_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD00_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD00_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD00                    (*((volatile dword *)0x0000E844))


  /*** CAN_WORD10 - Message Buffer 0 WORD1 Register; 0x0000E846 ***/
  union {
    dword Dword;
  } CAN_WORD10_STR;

  #define CAN_WORD10_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD10_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD10_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD10_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD10_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD10_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD10_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD10_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD10_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD10_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD10_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD10_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD10_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD10_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD10_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD10_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD10_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD10_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD10_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD10_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD10_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD10_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD10_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD10_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD10_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD10_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD10_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD10_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD10_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD10_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD10_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD10_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD10_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD10_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD10_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD10_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD10_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD10_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD10_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD10_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD10                    (*((volatile dword *)0x0000E846))


  /*** CAN_CS1 - Message Buffer 1 CS Register; 0x0000E848 ***/
  union {
    dword Dword;
  } CAN_CS1_STR;

  #define CAN_CS1_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS1_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS1_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS1_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS1_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS1_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS1_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS1_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS1_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS1_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS1_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS1_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS1_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS1_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS1_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS1_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS1_DLC0_MASK             0x00010000UL
  #define CAN_CS1_DLC1_MASK             0x00020000UL
  #define CAN_CS1_DLC2_MASK             0x00040000UL
  #define CAN_CS1_DLC3_MASK             0x00080000UL
  #define CAN_CS1_RTR_MASK              0x00100000UL
  #define CAN_CS1_IDE_MASK              0x00200000UL
  #define CAN_CS1_SRR_MASK              0x00400000UL
  #define CAN_CS1_CODE0_MASK            0x01000000UL
  #define CAN_CS1_CODE1_MASK            0x02000000UL
  #define CAN_CS1_CODE2_MASK            0x04000000UL
  #define CAN_CS1_CODE3_MASK            0x08000000UL
  #define CAN_CS1_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS1_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS1_DLC_MASK              0x000F0000UL
  #define CAN_CS1_DLC_BITNUM            0x10U
  #define CAN_CS1_CODE_MASK             0x0F000000UL
  #define CAN_CS1_CODE_BITNUM           0x18U
  #define CAN_CS1                       (*((volatile dword *)0x0000E848))


  /*** CAN_ID1 - Message Buffer 1 ID Register; 0x0000E84A ***/
  union {
    dword Dword;
  } CAN_ID1_STR;

  #define CAN_ID1_EXT0_MASK             0x01UL
  #define CAN_ID1_EXT1_MASK             0x02UL
  #define CAN_ID1_EXT2_MASK             0x04UL
  #define CAN_ID1_EXT3_MASK             0x08UL
  #define CAN_ID1_EXT4_MASK             0x10UL
  #define CAN_ID1_EXT5_MASK             0x20UL
  #define CAN_ID1_EXT6_MASK             0x40UL
  #define CAN_ID1_EXT7_MASK             0x80UL
  #define CAN_ID1_EXT8_MASK             0x0100UL
  #define CAN_ID1_EXT9_MASK             0x0200UL
  #define CAN_ID1_EXT10_MASK            0x0400UL
  #define CAN_ID1_EXT11_MASK            0x0800UL
  #define CAN_ID1_EXT12_MASK            0x1000UL
  #define CAN_ID1_EXT13_MASK            0x2000UL
  #define CAN_ID1_EXT14_MASK            0x4000UL
  #define CAN_ID1_EXT15_MASK            0x8000UL
  #define CAN_ID1_EXT16_MASK            0x00010000UL
  #define CAN_ID1_EXT17_MASK            0x00020000UL
  #define CAN_ID1_STD0_MASK             0x00040000UL
  #define CAN_ID1_STD1_MASK             0x00080000UL
  #define CAN_ID1_STD2_MASK             0x00100000UL
  #define CAN_ID1_STD3_MASK             0x00200000UL
  #define CAN_ID1_STD4_MASK             0x00400000UL
  #define CAN_ID1_STD5_MASK             0x00800000UL
  #define CAN_ID1_STD6_MASK             0x01000000UL
  #define CAN_ID1_STD7_MASK             0x02000000UL
  #define CAN_ID1_STD8_MASK             0x04000000UL
  #define CAN_ID1_STD9_MASK             0x08000000UL
  #define CAN_ID1_STD10_MASK            0x10000000UL
  #define CAN_ID1_PRIO0_MASK            0x20000000UL
  #define CAN_ID1_PRIO1_MASK            0x40000000UL
  #define CAN_ID1_PRIO2_MASK            0x80000000UL
  #define CAN_ID1_EXT_MASK              0x0003FFFFUL
  #define CAN_ID1_EXT_BITNUM            0x00U
  #define CAN_ID1_STD_MASK              0x1FFC0000UL
  #define CAN_ID1_STD_BITNUM            0x12U
  #define CAN_ID1_PRIO_MASK             0xE0000000UL
  #define CAN_ID1_PRIO_BITNUM           0x1DU
  #define CAN_ID1                       (*((volatile dword *)0x0000E84A))


  /*** CAN_WORD01 - Message Buffer 1 WORD0 Register; 0x0000E84C ***/
  union {
    dword Dword;
  } CAN_WORD01_STR;

  #define CAN_WORD01_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD01_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD01_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD01_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD01_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD01_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD01_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD01_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD01_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD01_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD01_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD01_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD01_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD01_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD01_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD01_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD01_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD01_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD01_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD01_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD01_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD01_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD01_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD01_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD01_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD01_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD01_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD01_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD01_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD01_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD01_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD01_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD01_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD01_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD01_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD01_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD01_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD01_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD01_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD01_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD01                    (*((volatile dword *)0x0000E84C))


  /*** CAN_WORD11 - Message Buffer 1 WORD1 Register; 0x0000E84E ***/
  union {
    dword Dword;
  } CAN_WORD11_STR;

  #define CAN_WORD11_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD11_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD11_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD11_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD11_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD11_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD11_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD11_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD11_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD11_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD11_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD11_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD11_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD11_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD11_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD11_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD11_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD11_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD11_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD11_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD11_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD11_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD11_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD11_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD11_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD11_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD11_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD11_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD11_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD11_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD11_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD11_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD11_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD11_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD11_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD11_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD11_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD11_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD11_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD11_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD11                    (*((volatile dword *)0x0000E84E))


  /*** CAN_CS2 - Message Buffer 2 CS Register; 0x0000E850 ***/
  union {
    dword Dword;
  } CAN_CS2_STR;

  #define CAN_CS2_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS2_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS2_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS2_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS2_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS2_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS2_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS2_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS2_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS2_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS2_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS2_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS2_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS2_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS2_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS2_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS2_DLC0_MASK             0x00010000UL
  #define CAN_CS2_DLC1_MASK             0x00020000UL
  #define CAN_CS2_DLC2_MASK             0x00040000UL
  #define CAN_CS2_DLC3_MASK             0x00080000UL
  #define CAN_CS2_RTR_MASK              0x00100000UL
  #define CAN_CS2_IDE_MASK              0x00200000UL
  #define CAN_CS2_SRR_MASK              0x00400000UL
  #define CAN_CS2_CODE0_MASK            0x01000000UL
  #define CAN_CS2_CODE1_MASK            0x02000000UL
  #define CAN_CS2_CODE2_MASK            0x04000000UL
  #define CAN_CS2_CODE3_MASK            0x08000000UL
  #define CAN_CS2_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS2_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS2_DLC_MASK              0x000F0000UL
  #define CAN_CS2_DLC_BITNUM            0x10U
  #define CAN_CS2_CODE_MASK             0x0F000000UL
  #define CAN_CS2_CODE_BITNUM           0x18U
  #define CAN_CS2                       (*((volatile dword *)0x0000E850))


  /*** CAN_ID2 - Message Buffer 2 ID Register; 0x0000E852 ***/
  union {
    dword Dword;
  } CAN_ID2_STR;

  #define CAN_ID2_EXT0_MASK             0x01UL
  #define CAN_ID2_EXT1_MASK             0x02UL
  #define CAN_ID2_EXT2_MASK             0x04UL
  #define CAN_ID2_EXT3_MASK             0x08UL
  #define CAN_ID2_EXT4_MASK             0x10UL
  #define CAN_ID2_EXT5_MASK             0x20UL
  #define CAN_ID2_EXT6_MASK             0x40UL
  #define CAN_ID2_EXT7_MASK             0x80UL
  #define CAN_ID2_EXT8_MASK             0x0100UL
  #define CAN_ID2_EXT9_MASK             0x0200UL
  #define CAN_ID2_EXT10_MASK            0x0400UL
  #define CAN_ID2_EXT11_MASK            0x0800UL
  #define CAN_ID2_EXT12_MASK            0x1000UL
  #define CAN_ID2_EXT13_MASK            0x2000UL
  #define CAN_ID2_EXT14_MASK            0x4000UL
  #define CAN_ID2_EXT15_MASK            0x8000UL
  #define CAN_ID2_EXT16_MASK            0x00010000UL
  #define CAN_ID2_EXT17_MASK            0x00020000UL
  #define CAN_ID2_STD0_MASK             0x00040000UL
  #define CAN_ID2_STD1_MASK             0x00080000UL
  #define CAN_ID2_STD2_MASK             0x00100000UL
  #define CAN_ID2_STD3_MASK             0x00200000UL
  #define CAN_ID2_STD4_MASK             0x00400000UL
  #define CAN_ID2_STD5_MASK             0x00800000UL
  #define CAN_ID2_STD6_MASK             0x01000000UL
  #define CAN_ID2_STD7_MASK             0x02000000UL
  #define CAN_ID2_STD8_MASK             0x04000000UL
  #define CAN_ID2_STD9_MASK             0x08000000UL
  #define CAN_ID2_STD10_MASK            0x10000000UL
  #define CAN_ID2_PRIO0_MASK            0x20000000UL
  #define CAN_ID2_PRIO1_MASK            0x40000000UL
  #define CAN_ID2_PRIO2_MASK            0x80000000UL
  #define CAN_ID2_EXT_MASK              0x0003FFFFUL
  #define CAN_ID2_EXT_BITNUM            0x00U
  #define CAN_ID2_STD_MASK              0x1FFC0000UL
  #define CAN_ID2_STD_BITNUM            0x12U
  #define CAN_ID2_PRIO_MASK             0xE0000000UL
  #define CAN_ID2_PRIO_BITNUM           0x1DU
  #define CAN_ID2                       (*((volatile dword *)0x0000E852))


  /*** CAN_WORD02 - Message Buffer 2 WORD0 Register; 0x0000E854 ***/
  union {
    dword Dword;
  } CAN_WORD02_STR;

  #define CAN_WORD02_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD02_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD02_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD02_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD02_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD02_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD02_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD02_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD02_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD02_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD02_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD02_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD02_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD02_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD02_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD02_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD02_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD02_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD02_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD02_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD02_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD02_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD02_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD02_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD02_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD02_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD02_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD02_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD02_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD02_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD02_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD02_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD02_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD02_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD02_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD02_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD02_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD02_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD02_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD02_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD02                    (*((volatile dword *)0x0000E854))


  /*** CAN_WORD12 - Message Buffer 2 WORD1 Register; 0x0000E856 ***/
  union {
    dword Dword;
  } CAN_WORD12_STR;

  #define CAN_WORD12_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD12_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD12_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD12_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD12_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD12_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD12_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD12_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD12_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD12_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD12_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD12_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD12_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD12_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD12_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD12_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD12_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD12_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD12_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD12_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD12_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD12_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD12_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD12_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD12_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD12_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD12_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD12_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD12_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD12_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD12_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD12_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD12_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD12_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD12_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD12_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD12_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD12_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD12_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD12_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD12                    (*((volatile dword *)0x0000E856))


  /*** CAN_CS3 - Message Buffer 3 CS Register; 0x0000E858 ***/
  union {
    dword Dword;
  } CAN_CS3_STR;

  #define CAN_CS3_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS3_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS3_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS3_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS3_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS3_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS3_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS3_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS3_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS3_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS3_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS3_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS3_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS3_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS3_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS3_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS3_DLC0_MASK             0x00010000UL
  #define CAN_CS3_DLC1_MASK             0x00020000UL
  #define CAN_CS3_DLC2_MASK             0x00040000UL
  #define CAN_CS3_DLC3_MASK             0x00080000UL
  #define CAN_CS3_RTR_MASK              0x00100000UL
  #define CAN_CS3_IDE_MASK              0x00200000UL
  #define CAN_CS3_SRR_MASK              0x00400000UL
  #define CAN_CS3_CODE0_MASK            0x01000000UL
  #define CAN_CS3_CODE1_MASK            0x02000000UL
  #define CAN_CS3_CODE2_MASK            0x04000000UL
  #define CAN_CS3_CODE3_MASK            0x08000000UL
  #define CAN_CS3_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS3_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS3_DLC_MASK              0x000F0000UL
  #define CAN_CS3_DLC_BITNUM            0x10U
  #define CAN_CS3_CODE_MASK             0x0F000000UL
  #define CAN_CS3_CODE_BITNUM           0x18U
  #define CAN_CS3                       (*((volatile dword *)0x0000E858))


  /*** CAN_ID3 - Message Buffer 3 ID Register; 0x0000E85A ***/
  union {
    dword Dword;
  } CAN_ID3_STR;

  #define CAN_ID3_EXT0_MASK             0x01UL
  #define CAN_ID3_EXT1_MASK             0x02UL
  #define CAN_ID3_EXT2_MASK             0x04UL
  #define CAN_ID3_EXT3_MASK             0x08UL
  #define CAN_ID3_EXT4_MASK             0x10UL
  #define CAN_ID3_EXT5_MASK             0x20UL
  #define CAN_ID3_EXT6_MASK             0x40UL
  #define CAN_ID3_EXT7_MASK             0x80UL
  #define CAN_ID3_EXT8_MASK             0x0100UL
  #define CAN_ID3_EXT9_MASK             0x0200UL
  #define CAN_ID3_EXT10_MASK            0x0400UL
  #define CAN_ID3_EXT11_MASK            0x0800UL
  #define CAN_ID3_EXT12_MASK            0x1000UL
  #define CAN_ID3_EXT13_MASK            0x2000UL
  #define CAN_ID3_EXT14_MASK            0x4000UL
  #define CAN_ID3_EXT15_MASK            0x8000UL
  #define CAN_ID3_EXT16_MASK            0x00010000UL
  #define CAN_ID3_EXT17_MASK            0x00020000UL
  #define CAN_ID3_STD0_MASK             0x00040000UL
  #define CAN_ID3_STD1_MASK             0x00080000UL
  #define CAN_ID3_STD2_MASK             0x00100000UL
  #define CAN_ID3_STD3_MASK             0x00200000UL
  #define CAN_ID3_STD4_MASK             0x00400000UL
  #define CAN_ID3_STD5_MASK             0x00800000UL
  #define CAN_ID3_STD6_MASK             0x01000000UL
  #define CAN_ID3_STD7_MASK             0x02000000UL
  #define CAN_ID3_STD8_MASK             0x04000000UL
  #define CAN_ID3_STD9_MASK             0x08000000UL
  #define CAN_ID3_STD10_MASK            0x10000000UL
  #define CAN_ID3_PRIO0_MASK            0x20000000UL
  #define CAN_ID3_PRIO1_MASK            0x40000000UL
  #define CAN_ID3_PRIO2_MASK            0x80000000UL
  #define CAN_ID3_EXT_MASK              0x0003FFFFUL
  #define CAN_ID3_EXT_BITNUM            0x00U
  #define CAN_ID3_STD_MASK              0x1FFC0000UL
  #define CAN_ID3_STD_BITNUM            0x12U
  #define CAN_ID3_PRIO_MASK             0xE0000000UL
  #define CAN_ID3_PRIO_BITNUM           0x1DU
  #define CAN_ID3                       (*((volatile dword *)0x0000E85A))


  /*** CAN_WORD03 - Message Buffer 3 WORD0 Register; 0x0000E85C ***/
  union {
    dword Dword;
  } CAN_WORD03_STR;

  #define CAN_WORD03_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD03_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD03_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD03_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD03_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD03_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD03_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD03_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD03_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD03_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD03_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD03_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD03_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD03_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD03_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD03_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD03_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD03_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD03_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD03_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD03_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD03_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD03_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD03_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD03_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD03_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD03_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD03_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD03_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD03_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD03_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD03_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD03_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD03_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD03_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD03_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD03_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD03_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD03_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD03_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD03                    (*((volatile dword *)0x0000E85C))


  /*** CAN_WORD13 - Message Buffer 3 WORD1 Register; 0x0000E85E ***/
  union {
    dword Dword;
  } CAN_WORD13_STR;

  #define CAN_WORD13_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD13_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD13_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD13_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD13_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD13_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD13_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD13_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD13_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD13_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD13_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD13_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD13_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD13_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD13_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD13_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD13_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD13_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD13_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD13_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD13_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD13_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD13_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD13_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD13_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD13_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD13_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD13_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD13_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD13_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD13_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD13_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD13_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD13_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD13_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD13_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD13_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD13_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD13_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD13_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD13                    (*((volatile dword *)0x0000E85E))


  /*** CAN_CS4 - Message Buffer 4 CS Register; 0x0000E860 ***/
  union {
    dword Dword;
  } CAN_CS4_STR;

  #define CAN_CS4_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS4_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS4_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS4_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS4_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS4_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS4_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS4_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS4_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS4_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS4_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS4_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS4_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS4_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS4_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS4_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS4_DLC0_MASK             0x00010000UL
  #define CAN_CS4_DLC1_MASK             0x00020000UL
  #define CAN_CS4_DLC2_MASK             0x00040000UL
  #define CAN_CS4_DLC3_MASK             0x00080000UL
  #define CAN_CS4_RTR_MASK              0x00100000UL
  #define CAN_CS4_IDE_MASK              0x00200000UL
  #define CAN_CS4_SRR_MASK              0x00400000UL
  #define CAN_CS4_CODE0_MASK            0x01000000UL
  #define CAN_CS4_CODE1_MASK            0x02000000UL
  #define CAN_CS4_CODE2_MASK            0x04000000UL
  #define CAN_CS4_CODE3_MASK            0x08000000UL
  #define CAN_CS4_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS4_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS4_DLC_MASK              0x000F0000UL
  #define CAN_CS4_DLC_BITNUM            0x10U
  #define CAN_CS4_CODE_MASK             0x0F000000UL
  #define CAN_CS4_CODE_BITNUM           0x18U
  #define CAN_CS4                       (*((volatile dword *)0x0000E860))


  /*** CAN_ID4 - Message Buffer 4 ID Register; 0x0000E862 ***/
  union {
    dword Dword;
  } CAN_ID4_STR;

  #define CAN_ID4_EXT0_MASK             0x01UL
  #define CAN_ID4_EXT1_MASK             0x02UL
  #define CAN_ID4_EXT2_MASK             0x04UL
  #define CAN_ID4_EXT3_MASK             0x08UL
  #define CAN_ID4_EXT4_MASK             0x10UL
  #define CAN_ID4_EXT5_MASK             0x20UL
  #define CAN_ID4_EXT6_MASK             0x40UL
  #define CAN_ID4_EXT7_MASK             0x80UL
  #define CAN_ID4_EXT8_MASK             0x0100UL
  #define CAN_ID4_EXT9_MASK             0x0200UL
  #define CAN_ID4_EXT10_MASK            0x0400UL
  #define CAN_ID4_EXT11_MASK            0x0800UL
  #define CAN_ID4_EXT12_MASK            0x1000UL
  #define CAN_ID4_EXT13_MASK            0x2000UL
  #define CAN_ID4_EXT14_MASK            0x4000UL
  #define CAN_ID4_EXT15_MASK            0x8000UL
  #define CAN_ID4_EXT16_MASK            0x00010000UL
  #define CAN_ID4_EXT17_MASK            0x00020000UL
  #define CAN_ID4_STD0_MASK             0x00040000UL
  #define CAN_ID4_STD1_MASK             0x00080000UL
  #define CAN_ID4_STD2_MASK             0x00100000UL
  #define CAN_ID4_STD3_MASK             0x00200000UL
  #define CAN_ID4_STD4_MASK             0x00400000UL
  #define CAN_ID4_STD5_MASK             0x00800000UL
  #define CAN_ID4_STD6_MASK             0x01000000UL
  #define CAN_ID4_STD7_MASK             0x02000000UL
  #define CAN_ID4_STD8_MASK             0x04000000UL
  #define CAN_ID4_STD9_MASK             0x08000000UL
  #define CAN_ID4_STD10_MASK            0x10000000UL
  #define CAN_ID4_PRIO0_MASK            0x20000000UL
  #define CAN_ID4_PRIO1_MASK            0x40000000UL
  #define CAN_ID4_PRIO2_MASK            0x80000000UL
  #define CAN_ID4_EXT_MASK              0x0003FFFFUL
  #define CAN_ID4_EXT_BITNUM            0x00U
  #define CAN_ID4_STD_MASK              0x1FFC0000UL
  #define CAN_ID4_STD_BITNUM            0x12U
  #define CAN_ID4_PRIO_MASK             0xE0000000UL
  #define CAN_ID4_PRIO_BITNUM           0x1DU
  #define CAN_ID4                       (*((volatile dword *)0x0000E862))


  /*** CAN_WORD04 - Message Buffer 4 WORD0 Register; 0x0000E864 ***/
  union {
    dword Dword;
  } CAN_WORD04_STR;

  #define CAN_WORD04_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD04_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD04_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD04_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD04_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD04_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD04_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD04_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD04_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD04_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD04_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD04_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD04_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD04_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD04_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD04_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD04_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD04_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD04_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD04_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD04_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD04_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD04_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD04_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD04_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD04_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD04_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD04_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD04_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD04_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD04_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD04_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD04_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD04_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD04_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD04_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD04_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD04_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD04_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD04_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD04                    (*((volatile dword *)0x0000E864))


  /*** CAN_WORD14 - Message Buffer 4 WORD1 Register; 0x0000E866 ***/
  union {
    dword Dword;
  } CAN_WORD14_STR;

  #define CAN_WORD14_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD14_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD14_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD14_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD14_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD14_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD14_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD14_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD14_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD14_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD14_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD14_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD14_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD14_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD14_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD14_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD14_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD14_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD14_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD14_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD14_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD14_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD14_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD14_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD14_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD14_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD14_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD14_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD14_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD14_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD14_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD14_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD14_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD14_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD14_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD14_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD14_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD14_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD14_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD14_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD14                    (*((volatile dword *)0x0000E866))


  /*** CAN_CS5 - Message Buffer 5 CS Register; 0x0000E868 ***/
  union {
    dword Dword;
  } CAN_CS5_STR;

  #define CAN_CS5_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS5_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS5_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS5_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS5_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS5_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS5_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS5_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS5_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS5_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS5_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS5_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS5_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS5_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS5_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS5_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS5_DLC0_MASK             0x00010000UL
  #define CAN_CS5_DLC1_MASK             0x00020000UL
  #define CAN_CS5_DLC2_MASK             0x00040000UL
  #define CAN_CS5_DLC3_MASK             0x00080000UL
  #define CAN_CS5_RTR_MASK              0x00100000UL
  #define CAN_CS5_IDE_MASK              0x00200000UL
  #define CAN_CS5_SRR_MASK              0x00400000UL
  #define CAN_CS5_CODE0_MASK            0x01000000UL
  #define CAN_CS5_CODE1_MASK            0x02000000UL
  #define CAN_CS5_CODE2_MASK            0x04000000UL
  #define CAN_CS5_CODE3_MASK            0x08000000UL
  #define CAN_CS5_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS5_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS5_DLC_MASK              0x000F0000UL
  #define CAN_CS5_DLC_BITNUM            0x10U
  #define CAN_CS5_CODE_MASK             0x0F000000UL
  #define CAN_CS5_CODE_BITNUM           0x18U
  #define CAN_CS5                       (*((volatile dword *)0x0000E868))


  /*** CAN_ID5 - Message Buffer 5 ID Register; 0x0000E86A ***/
  union {
    dword Dword;
  } CAN_ID5_STR;

  #define CAN_ID5_EXT0_MASK             0x01UL
  #define CAN_ID5_EXT1_MASK             0x02UL
  #define CAN_ID5_EXT2_MASK             0x04UL
  #define CAN_ID5_EXT3_MASK             0x08UL
  #define CAN_ID5_EXT4_MASK             0x10UL
  #define CAN_ID5_EXT5_MASK             0x20UL
  #define CAN_ID5_EXT6_MASK             0x40UL
  #define CAN_ID5_EXT7_MASK             0x80UL
  #define CAN_ID5_EXT8_MASK             0x0100UL
  #define CAN_ID5_EXT9_MASK             0x0200UL
  #define CAN_ID5_EXT10_MASK            0x0400UL
  #define CAN_ID5_EXT11_MASK            0x0800UL
  #define CAN_ID5_EXT12_MASK            0x1000UL
  #define CAN_ID5_EXT13_MASK            0x2000UL
  #define CAN_ID5_EXT14_MASK            0x4000UL
  #define CAN_ID5_EXT15_MASK            0x8000UL
  #define CAN_ID5_EXT16_MASK            0x00010000UL
  #define CAN_ID5_EXT17_MASK            0x00020000UL
  #define CAN_ID5_STD0_MASK             0x00040000UL
  #define CAN_ID5_STD1_MASK             0x00080000UL
  #define CAN_ID5_STD2_MASK             0x00100000UL
  #define CAN_ID5_STD3_MASK             0x00200000UL
  #define CAN_ID5_STD4_MASK             0x00400000UL
  #define CAN_ID5_STD5_MASK             0x00800000UL
  #define CAN_ID5_STD6_MASK             0x01000000UL
  #define CAN_ID5_STD7_MASK             0x02000000UL
  #define CAN_ID5_STD8_MASK             0x04000000UL
  #define CAN_ID5_STD9_MASK             0x08000000UL
  #define CAN_ID5_STD10_MASK            0x10000000UL
  #define CAN_ID5_PRIO0_MASK            0x20000000UL
  #define CAN_ID5_PRIO1_MASK            0x40000000UL
  #define CAN_ID5_PRIO2_MASK            0x80000000UL
  #define CAN_ID5_EXT_MASK              0x0003FFFFUL
  #define CAN_ID5_EXT_BITNUM            0x00U
  #define CAN_ID5_STD_MASK              0x1FFC0000UL
  #define CAN_ID5_STD_BITNUM            0x12U
  #define CAN_ID5_PRIO_MASK             0xE0000000UL
  #define CAN_ID5_PRIO_BITNUM           0x1DU
  #define CAN_ID5                       (*((volatile dword *)0x0000E86A))


  /*** CAN_WORD05 - Message Buffer 5 WORD0 Register; 0x0000E86C ***/
  union {
    dword Dword;
  } CAN_WORD05_STR;

  #define CAN_WORD05_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD05_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD05_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD05_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD05_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD05_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD05_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD05_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD05_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD05_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD05_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD05_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD05_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD05_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD05_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD05_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD05_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD05_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD05_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD05_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD05_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD05_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD05_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD05_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD05_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD05_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD05_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD05_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD05_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD05_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD05_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD05_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD05_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD05_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD05_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD05_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD05_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD05_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD05_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD05_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD05                    (*((volatile dword *)0x0000E86C))


  /*** CAN_WORD15 - Message Buffer 5 WORD1 Register; 0x0000E86E ***/
  union {
    dword Dword;
  } CAN_WORD15_STR;

  #define CAN_WORD15_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD15_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD15_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD15_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD15_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD15_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD15_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD15_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD15_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD15_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD15_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD15_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD15_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD15_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD15_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD15_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD15_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD15_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD15_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD15_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD15_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD15_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD15_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD15_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD15_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD15_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD15_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD15_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD15_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD15_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD15_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD15_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD15_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD15_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD15_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD15_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD15_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD15_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD15_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD15_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD15                    (*((volatile dword *)0x0000E86E))


  /*** CAN_CS6 - Message Buffer 6 CS Register; 0x0000E870 ***/
  union {
    dword Dword;
  } CAN_CS6_STR;

  #define CAN_CS6_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS6_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS6_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS6_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS6_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS6_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS6_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS6_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS6_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS6_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS6_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS6_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS6_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS6_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS6_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS6_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS6_DLC0_MASK             0x00010000UL
  #define CAN_CS6_DLC1_MASK             0x00020000UL
  #define CAN_CS6_DLC2_MASK             0x00040000UL
  #define CAN_CS6_DLC3_MASK             0x00080000UL
  #define CAN_CS6_RTR_MASK              0x00100000UL
  #define CAN_CS6_IDE_MASK              0x00200000UL
  #define CAN_CS6_SRR_MASK              0x00400000UL
  #define CAN_CS6_CODE0_MASK            0x01000000UL
  #define CAN_CS6_CODE1_MASK            0x02000000UL
  #define CAN_CS6_CODE2_MASK            0x04000000UL
  #define CAN_CS6_CODE3_MASK            0x08000000UL
  #define CAN_CS6_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS6_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS6_DLC_MASK              0x000F0000UL
  #define CAN_CS6_DLC_BITNUM            0x10U
  #define CAN_CS6_CODE_MASK             0x0F000000UL
  #define CAN_CS6_CODE_BITNUM           0x18U
  #define CAN_CS6                       (*((volatile dword *)0x0000E870))


  /*** CAN_ID6 - Message Buffer 6 ID Register; 0x0000E872 ***/
  union {
    dword Dword;
  } CAN_ID6_STR;

  #define CAN_ID6_EXT0_MASK             0x01UL
  #define CAN_ID6_EXT1_MASK             0x02UL
  #define CAN_ID6_EXT2_MASK             0x04UL
  #define CAN_ID6_EXT3_MASK             0x08UL
  #define CAN_ID6_EXT4_MASK             0x10UL
  #define CAN_ID6_EXT5_MASK             0x20UL
  #define CAN_ID6_EXT6_MASK             0x40UL
  #define CAN_ID6_EXT7_MASK             0x80UL
  #define CAN_ID6_EXT8_MASK             0x0100UL
  #define CAN_ID6_EXT9_MASK             0x0200UL
  #define CAN_ID6_EXT10_MASK            0x0400UL
  #define CAN_ID6_EXT11_MASK            0x0800UL
  #define CAN_ID6_EXT12_MASK            0x1000UL
  #define CAN_ID6_EXT13_MASK            0x2000UL
  #define CAN_ID6_EXT14_MASK            0x4000UL
  #define CAN_ID6_EXT15_MASK            0x8000UL
  #define CAN_ID6_EXT16_MASK            0x00010000UL
  #define CAN_ID6_EXT17_MASK            0x00020000UL
  #define CAN_ID6_STD0_MASK             0x00040000UL
  #define CAN_ID6_STD1_MASK             0x00080000UL
  #define CAN_ID6_STD2_MASK             0x00100000UL
  #define CAN_ID6_STD3_MASK             0x00200000UL
  #define CAN_ID6_STD4_MASK             0x00400000UL
  #define CAN_ID6_STD5_MASK             0x00800000UL
  #define CAN_ID6_STD6_MASK             0x01000000UL
  #define CAN_ID6_STD7_MASK             0x02000000UL
  #define CAN_ID6_STD8_MASK             0x04000000UL
  #define CAN_ID6_STD9_MASK             0x08000000UL
  #define CAN_ID6_STD10_MASK            0x10000000UL
  #define CAN_ID6_PRIO0_MASK            0x20000000UL
  #define CAN_ID6_PRIO1_MASK            0x40000000UL
  #define CAN_ID6_PRIO2_MASK            0x80000000UL
  #define CAN_ID6_EXT_MASK              0x0003FFFFUL
  #define CAN_ID6_EXT_BITNUM            0x00U
  #define CAN_ID6_STD_MASK              0x1FFC0000UL
  #define CAN_ID6_STD_BITNUM            0x12U
  #define CAN_ID6_PRIO_MASK             0xE0000000UL
  #define CAN_ID6_PRIO_BITNUM           0x1DU
  #define CAN_ID6                       (*((volatile dword *)0x0000E872))


  /*** CAN_WORD06 - Message Buffer 6 WORD0 Register; 0x0000E874 ***/
  union {
    dword Dword;
  } CAN_WORD06_STR;

  #define CAN_WORD06_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD06_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD06_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD06_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD06_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD06_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD06_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD06_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD06_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD06_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD06_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD06_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD06_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD06_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD06_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD06_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD06_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD06_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD06_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD06_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD06_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD06_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD06_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD06_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD06_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD06_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD06_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD06_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD06_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD06_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD06_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD06_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD06_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD06_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD06_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD06_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD06_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD06_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD06_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD06_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD06                    (*((volatile dword *)0x0000E874))


  /*** CAN_WORD16 - Message Buffer 6 WORD1 Register; 0x0000E876 ***/
  union {
    dword Dword;
  } CAN_WORD16_STR;

  #define CAN_WORD16_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD16_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD16_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD16_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD16_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD16_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD16_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD16_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD16_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD16_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD16_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD16_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD16_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD16_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD16_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD16_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD16_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD16_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD16_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD16_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD16_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD16_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD16_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD16_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD16_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD16_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD16_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD16_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD16_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD16_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD16_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD16_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD16_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD16_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD16_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD16_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD16_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD16_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD16_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD16_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD16                    (*((volatile dword *)0x0000E876))


  /*** CAN_CS7 - Message Buffer 7 CS Register; 0x0000E878 ***/
  union {
    dword Dword;
  } CAN_CS7_STR;

  #define CAN_CS7_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS7_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS7_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS7_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS7_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS7_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS7_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS7_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS7_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS7_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS7_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS7_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS7_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS7_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS7_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS7_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS7_DLC0_MASK             0x00010000UL
  #define CAN_CS7_DLC1_MASK             0x00020000UL
  #define CAN_CS7_DLC2_MASK             0x00040000UL
  #define CAN_CS7_DLC3_MASK             0x00080000UL
  #define CAN_CS7_RTR_MASK              0x00100000UL
  #define CAN_CS7_IDE_MASK              0x00200000UL
  #define CAN_CS7_SRR_MASK              0x00400000UL
  #define CAN_CS7_CODE0_MASK            0x01000000UL
  #define CAN_CS7_CODE1_MASK            0x02000000UL
  #define CAN_CS7_CODE2_MASK            0x04000000UL
  #define CAN_CS7_CODE3_MASK            0x08000000UL
  #define CAN_CS7_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS7_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS7_DLC_MASK              0x000F0000UL
  #define CAN_CS7_DLC_BITNUM            0x10U
  #define CAN_CS7_CODE_MASK             0x0F000000UL
  #define CAN_CS7_CODE_BITNUM           0x18U
  #define CAN_CS7                       (*((volatile dword *)0x0000E878))


  /*** CAN_ID7 - Message Buffer 7 ID Register; 0x0000E87A ***/
  union {
    dword Dword;
  } CAN_ID7_STR;

  #define CAN_ID7_EXT0_MASK             0x01UL
  #define CAN_ID7_EXT1_MASK             0x02UL
  #define CAN_ID7_EXT2_MASK             0x04UL
  #define CAN_ID7_EXT3_MASK             0x08UL
  #define CAN_ID7_EXT4_MASK             0x10UL
  #define CAN_ID7_EXT5_MASK             0x20UL
  #define CAN_ID7_EXT6_MASK             0x40UL
  #define CAN_ID7_EXT7_MASK             0x80UL
  #define CAN_ID7_EXT8_MASK             0x0100UL
  #define CAN_ID7_EXT9_MASK             0x0200UL
  #define CAN_ID7_EXT10_MASK            0x0400UL
  #define CAN_ID7_EXT11_MASK            0x0800UL
  #define CAN_ID7_EXT12_MASK            0x1000UL
  #define CAN_ID7_EXT13_MASK            0x2000UL
  #define CAN_ID7_EXT14_MASK            0x4000UL
  #define CAN_ID7_EXT15_MASK            0x8000UL
  #define CAN_ID7_EXT16_MASK            0x00010000UL
  #define CAN_ID7_EXT17_MASK            0x00020000UL
  #define CAN_ID7_STD0_MASK             0x00040000UL
  #define CAN_ID7_STD1_MASK             0x00080000UL
  #define CAN_ID7_STD2_MASK             0x00100000UL
  #define CAN_ID7_STD3_MASK             0x00200000UL
  #define CAN_ID7_STD4_MASK             0x00400000UL
  #define CAN_ID7_STD5_MASK             0x00800000UL
  #define CAN_ID7_STD6_MASK             0x01000000UL
  #define CAN_ID7_STD7_MASK             0x02000000UL
  #define CAN_ID7_STD8_MASK             0x04000000UL
  #define CAN_ID7_STD9_MASK             0x08000000UL
  #define CAN_ID7_STD10_MASK            0x10000000UL
  #define CAN_ID7_PRIO0_MASK            0x20000000UL
  #define CAN_ID7_PRIO1_MASK            0x40000000UL
  #define CAN_ID7_PRIO2_MASK            0x80000000UL
  #define CAN_ID7_EXT_MASK              0x0003FFFFUL
  #define CAN_ID7_EXT_BITNUM            0x00U
  #define CAN_ID7_STD_MASK              0x1FFC0000UL
  #define CAN_ID7_STD_BITNUM            0x12U
  #define CAN_ID7_PRIO_MASK             0xE0000000UL
  #define CAN_ID7_PRIO_BITNUM           0x1DU
  #define CAN_ID7                       (*((volatile dword *)0x0000E87A))


  /*** CAN_WORD07 - Message Buffer 7 WORD0 Register; 0x0000E87C ***/
  union {
    dword Dword;
  } CAN_WORD07_STR;

  #define CAN_WORD07_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD07_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD07_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD07_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD07_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD07_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD07_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD07_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD07_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD07_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD07_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD07_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD07_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD07_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD07_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD07_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD07_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD07_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD07_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD07_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD07_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD07_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD07_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD07_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD07_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD07_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD07_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD07_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD07_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD07_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD07_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD07_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD07_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD07_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD07_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD07_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD07_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD07_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD07_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD07_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD07                    (*((volatile dword *)0x0000E87C))


  /*** CAN_WORD17 - Message Buffer 7 WORD1 Register; 0x0000E87E ***/
  union {
    dword Dword;
  } CAN_WORD17_STR;

  #define CAN_WORD17_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD17_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD17_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD17_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD17_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD17_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD17_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD17_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD17_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD17_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD17_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD17_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD17_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD17_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD17_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD17_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD17_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD17_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD17_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD17_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD17_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD17_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD17_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD17_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD17_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD17_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD17_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD17_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD17_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD17_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD17_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD17_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD17_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD17_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD17_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD17_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD17_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD17_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD17_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD17_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD17                    (*((volatile dword *)0x0000E87E))


  /*** CAN_CS8 - Message Buffer 8 CS Register; 0x0000E880 ***/
  union {
    dword Dword;
  } CAN_CS8_STR;

  #define CAN_CS8_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS8_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS8_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS8_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS8_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS8_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS8_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS8_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS8_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS8_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS8_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS8_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS8_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS8_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS8_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS8_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS8_DLC0_MASK             0x00010000UL
  #define CAN_CS8_DLC1_MASK             0x00020000UL
  #define CAN_CS8_DLC2_MASK             0x00040000UL
  #define CAN_CS8_DLC3_MASK             0x00080000UL
  #define CAN_CS8_RTR_MASK              0x00100000UL
  #define CAN_CS8_IDE_MASK              0x00200000UL
  #define CAN_CS8_SRR_MASK              0x00400000UL
  #define CAN_CS8_CODE0_MASK            0x01000000UL
  #define CAN_CS8_CODE1_MASK            0x02000000UL
  #define CAN_CS8_CODE2_MASK            0x04000000UL
  #define CAN_CS8_CODE3_MASK            0x08000000UL
  #define CAN_CS8_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS8_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS8_DLC_MASK              0x000F0000UL
  #define CAN_CS8_DLC_BITNUM            0x10U
  #define CAN_CS8_CODE_MASK             0x0F000000UL
  #define CAN_CS8_CODE_BITNUM           0x18U
  #define CAN_CS8                       (*((volatile dword *)0x0000E880))


  /*** CAN_ID8 - Message Buffer 8 ID Register; 0x0000E882 ***/
  union {
    dword Dword;
  } CAN_ID8_STR;

  #define CAN_ID8_EXT0_MASK             0x01UL
  #define CAN_ID8_EXT1_MASK             0x02UL
  #define CAN_ID8_EXT2_MASK             0x04UL
  #define CAN_ID8_EXT3_MASK             0x08UL
  #define CAN_ID8_EXT4_MASK             0x10UL
  #define CAN_ID8_EXT5_MASK             0x20UL
  #define CAN_ID8_EXT6_MASK             0x40UL
  #define CAN_ID8_EXT7_MASK             0x80UL
  #define CAN_ID8_EXT8_MASK             0x0100UL
  #define CAN_ID8_EXT9_MASK             0x0200UL
  #define CAN_ID8_EXT10_MASK            0x0400UL
  #define CAN_ID8_EXT11_MASK            0x0800UL
  #define CAN_ID8_EXT12_MASK            0x1000UL
  #define CAN_ID8_EXT13_MASK            0x2000UL
  #define CAN_ID8_EXT14_MASK            0x4000UL
  #define CAN_ID8_EXT15_MASK            0x8000UL
  #define CAN_ID8_EXT16_MASK            0x00010000UL
  #define CAN_ID8_EXT17_MASK            0x00020000UL
  #define CAN_ID8_STD0_MASK             0x00040000UL
  #define CAN_ID8_STD1_MASK             0x00080000UL
  #define CAN_ID8_STD2_MASK             0x00100000UL
  #define CAN_ID8_STD3_MASK             0x00200000UL
  #define CAN_ID8_STD4_MASK             0x00400000UL
  #define CAN_ID8_STD5_MASK             0x00800000UL
  #define CAN_ID8_STD6_MASK             0x01000000UL
  #define CAN_ID8_STD7_MASK             0x02000000UL
  #define CAN_ID8_STD8_MASK             0x04000000UL
  #define CAN_ID8_STD9_MASK             0x08000000UL
  #define CAN_ID8_STD10_MASK            0x10000000UL
  #define CAN_ID8_PRIO0_MASK            0x20000000UL
  #define CAN_ID8_PRIO1_MASK            0x40000000UL
  #define CAN_ID8_PRIO2_MASK            0x80000000UL
  #define CAN_ID8_EXT_MASK              0x0003FFFFUL
  #define CAN_ID8_EXT_BITNUM            0x00U
  #define CAN_ID8_STD_MASK              0x1FFC0000UL
  #define CAN_ID8_STD_BITNUM            0x12U
  #define CAN_ID8_PRIO_MASK             0xE0000000UL
  #define CAN_ID8_PRIO_BITNUM           0x1DU
  #define CAN_ID8                       (*((volatile dword *)0x0000E882))


  /*** CAN_WORD08 - Message Buffer 8 WORD0 Register; 0x0000E884 ***/
  union {
    dword Dword;
  } CAN_WORD08_STR;

  #define CAN_WORD08_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD08_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD08_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD08_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD08_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD08_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD08_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD08_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD08_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD08_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD08_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD08_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD08_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD08_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD08_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD08_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD08_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD08_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD08_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD08_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD08_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD08_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD08_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD08_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD08_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD08_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD08_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD08_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD08_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD08_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD08_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD08_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD08_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD08_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD08_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD08_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD08_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD08_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD08_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD08_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD08                    (*((volatile dword *)0x0000E884))


  /*** CAN_WORD18 - Message Buffer 8 WORD1 Register; 0x0000E886 ***/
  union {
    dword Dword;
  } CAN_WORD18_STR;

  #define CAN_WORD18_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD18_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD18_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD18_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD18_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD18_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD18_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD18_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD18_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD18_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD18_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD18_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD18_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD18_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD18_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD18_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD18_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD18_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD18_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD18_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD18_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD18_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD18_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD18_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD18_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD18_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD18_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD18_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD18_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD18_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD18_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD18_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD18_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD18_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD18_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD18_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD18_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD18_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD18_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD18_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD18                    (*((volatile dword *)0x0000E886))


  /*** CAN_CS9 - Message Buffer 9 CS Register; 0x0000E888 ***/
  union {
    dword Dword;
  } CAN_CS9_STR;

  #define CAN_CS9_TIME_STAMP0_MASK      0x01UL
  #define CAN_CS9_TIME_STAMP1_MASK      0x02UL
  #define CAN_CS9_TIME_STAMP2_MASK      0x04UL
  #define CAN_CS9_TIME_STAMP3_MASK      0x08UL
  #define CAN_CS9_TIME_STAMP4_MASK      0x10UL
  #define CAN_CS9_TIME_STAMP5_MASK      0x20UL
  #define CAN_CS9_TIME_STAMP6_MASK      0x40UL
  #define CAN_CS9_TIME_STAMP7_MASK      0x80UL
  #define CAN_CS9_TIME_STAMP8_MASK      0x0100UL
  #define CAN_CS9_TIME_STAMP9_MASK      0x0200UL
  #define CAN_CS9_TIME_STAMP10_MASK     0x0400UL
  #define CAN_CS9_TIME_STAMP11_MASK     0x0800UL
  #define CAN_CS9_TIME_STAMP12_MASK     0x1000UL
  #define CAN_CS9_TIME_STAMP13_MASK     0x2000UL
  #define CAN_CS9_TIME_STAMP14_MASK     0x4000UL
  #define CAN_CS9_TIME_STAMP15_MASK     0x8000UL
  #define CAN_CS9_DLC0_MASK             0x00010000UL
  #define CAN_CS9_DLC1_MASK             0x00020000UL
  #define CAN_CS9_DLC2_MASK             0x00040000UL
  #define CAN_CS9_DLC3_MASK             0x00080000UL
  #define CAN_CS9_RTR_MASK              0x00100000UL
  #define CAN_CS9_IDE_MASK              0x00200000UL
  #define CAN_CS9_SRR_MASK              0x00400000UL
  #define CAN_CS9_CODE0_MASK            0x01000000UL
  #define CAN_CS9_CODE1_MASK            0x02000000UL
  #define CAN_CS9_CODE2_MASK            0x04000000UL
  #define CAN_CS9_CODE3_MASK            0x08000000UL
  #define CAN_CS9_TIME_STAMP_MASK       0xFFFFUL
  #define CAN_CS9_TIME_STAMP_BITNUM     0x00U
  #define CAN_CS9_DLC_MASK              0x000F0000UL
  #define CAN_CS9_DLC_BITNUM            0x10U
  #define CAN_CS9_CODE_MASK             0x0F000000UL
  #define CAN_CS9_CODE_BITNUM           0x18U
  #define CAN_CS9                       (*((volatile dword *)0x0000E888))


  /*** CAN_ID9 - Message Buffer 9 ID Register; 0x0000E88A ***/
  union {
    dword Dword;
  } CAN_ID9_STR;

  #define CAN_ID9_EXT0_MASK             0x01UL
  #define CAN_ID9_EXT1_MASK             0x02UL
  #define CAN_ID9_EXT2_MASK             0x04UL
  #define CAN_ID9_EXT3_MASK             0x08UL
  #define CAN_ID9_EXT4_MASK             0x10UL
  #define CAN_ID9_EXT5_MASK             0x20UL
  #define CAN_ID9_EXT6_MASK             0x40UL
  #define CAN_ID9_EXT7_MASK             0x80UL
  #define CAN_ID9_EXT8_MASK             0x0100UL
  #define CAN_ID9_EXT9_MASK             0x0200UL
  #define CAN_ID9_EXT10_MASK            0x0400UL
  #define CAN_ID9_EXT11_MASK            0x0800UL
  #define CAN_ID9_EXT12_MASK            0x1000UL
  #define CAN_ID9_EXT13_MASK            0x2000UL
  #define CAN_ID9_EXT14_MASK            0x4000UL
  #define CAN_ID9_EXT15_MASK            0x8000UL
  #define CAN_ID9_EXT16_MASK            0x00010000UL
  #define CAN_ID9_EXT17_MASK            0x00020000UL
  #define CAN_ID9_STD0_MASK             0x00040000UL
  #define CAN_ID9_STD1_MASK             0x00080000UL
  #define CAN_ID9_STD2_MASK             0x00100000UL
  #define CAN_ID9_STD3_MASK             0x00200000UL
  #define CAN_ID9_STD4_MASK             0x00400000UL
  #define CAN_ID9_STD5_MASK             0x00800000UL
  #define CAN_ID9_STD6_MASK             0x01000000UL
  #define CAN_ID9_STD7_MASK             0x02000000UL
  #define CAN_ID9_STD8_MASK             0x04000000UL
  #define CAN_ID9_STD9_MASK             0x08000000UL
  #define CAN_ID9_STD10_MASK            0x10000000UL
  #define CAN_ID9_PRIO0_MASK            0x20000000UL
  #define CAN_ID9_PRIO1_MASK            0x40000000UL
  #define CAN_ID9_PRIO2_MASK            0x80000000UL
  #define CAN_ID9_EXT_MASK              0x0003FFFFUL
  #define CAN_ID9_EXT_BITNUM            0x00U
  #define CAN_ID9_STD_MASK              0x1FFC0000UL
  #define CAN_ID9_STD_BITNUM            0x12U
  #define CAN_ID9_PRIO_MASK             0xE0000000UL
  #define CAN_ID9_PRIO_BITNUM           0x1DU
  #define CAN_ID9                       (*((volatile dword *)0x0000E88A))


  /*** CAN_WORD09 - Message Buffer 9 WORD0 Register; 0x0000E88C ***/
  union {
    dword Dword;
  } CAN_WORD09_STR;

  #define CAN_WORD09_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD09_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD09_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD09_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD09_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD09_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD09_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD09_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD09_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD09_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD09_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD09_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD09_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD09_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD09_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD09_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD09_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD09_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD09_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD09_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD09_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD09_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD09_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD09_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD09_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD09_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD09_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD09_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD09_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD09_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD09_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD09_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD09_DATA_BYTE_3_MASK   0xFFUL
  #define CAN_WORD09_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD09_DATA_BYTE_2_MASK   0xFF00UL
  #define CAN_WORD09_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD09_DATA_BYTE_1_MASK   0x00FF0000UL
  #define CAN_WORD09_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD09_DATA_BYTE_0_MASK   0xFF000000UL
  #define CAN_WORD09_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD09                    (*((volatile dword *)0x0000E88C))


  /*** CAN_WORD19 - Message Buffer 9 WORD1 Register; 0x0000E88E ***/
  union {
    dword Dword;
  } CAN_WORD19_STR;

  #define CAN_WORD19_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD19_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD19_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD19_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD19_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD19_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD19_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD19_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD19_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD19_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD19_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD19_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD19_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD19_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD19_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD19_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD19_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD19_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD19_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD19_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD19_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD19_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD19_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD19_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD19_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD19_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD19_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD19_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD19_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD19_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD19_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD19_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD19_DATA_BYTE_7_MASK   0xFFUL
  #define CAN_WORD19_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD19_DATA_BYTE_6_MASK   0xFF00UL
  #define CAN_WORD19_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD19_DATA_BYTE_5_MASK   0x00FF0000UL
  #define CAN_WORD19_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD19_DATA_BYTE_4_MASK   0xFF000000UL
  #define CAN_WORD19_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD19                    (*((volatile dword *)0x0000E88E))


  /*** CAN_CS10 - Message Buffer 10 CS Register; 0x0000E890 ***/
  union {
    dword Dword;
  } CAN_CS10_STR;

  #define CAN_CS10_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS10_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS10_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS10_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS10_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS10_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS10_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS10_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS10_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS10_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS10_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS10_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS10_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS10_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS10_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS10_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS10_DLC0_MASK            0x00010000UL
  #define CAN_CS10_DLC1_MASK            0x00020000UL
  #define CAN_CS10_DLC2_MASK            0x00040000UL
  #define CAN_CS10_DLC3_MASK            0x00080000UL
  #define CAN_CS10_RTR_MASK             0x00100000UL
  #define CAN_CS10_IDE_MASK             0x00200000UL
  #define CAN_CS10_SRR_MASK             0x00400000UL
  #define CAN_CS10_CODE0_MASK           0x01000000UL
  #define CAN_CS10_CODE1_MASK           0x02000000UL
  #define CAN_CS10_CODE2_MASK           0x04000000UL
  #define CAN_CS10_CODE3_MASK           0x08000000UL
  #define CAN_CS10_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS10_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS10_DLC_MASK             0x000F0000UL
  #define CAN_CS10_DLC_BITNUM           0x10U
  #define CAN_CS10_CODE_MASK            0x0F000000UL
  #define CAN_CS10_CODE_BITNUM          0x18U
  #define CAN_CS10                      (*((volatile dword *)0x0000E890))


  /*** CAN_ID10 - Message Buffer 10 ID Register; 0x0000E892 ***/
  union {
    dword Dword;
  } CAN_ID10_STR;

  #define CAN_ID10_EXT0_MASK            0x01UL
  #define CAN_ID10_EXT1_MASK            0x02UL
  #define CAN_ID10_EXT2_MASK            0x04UL
  #define CAN_ID10_EXT3_MASK            0x08UL
  #define CAN_ID10_EXT4_MASK            0x10UL
  #define CAN_ID10_EXT5_MASK            0x20UL
  #define CAN_ID10_EXT6_MASK            0x40UL
  #define CAN_ID10_EXT7_MASK            0x80UL
  #define CAN_ID10_EXT8_MASK            0x0100UL
  #define CAN_ID10_EXT9_MASK            0x0200UL
  #define CAN_ID10_EXT10_MASK           0x0400UL
  #define CAN_ID10_EXT11_MASK           0x0800UL
  #define CAN_ID10_EXT12_MASK           0x1000UL
  #define CAN_ID10_EXT13_MASK           0x2000UL
  #define CAN_ID10_EXT14_MASK           0x4000UL
  #define CAN_ID10_EXT15_MASK           0x8000UL
  #define CAN_ID10_EXT16_MASK           0x00010000UL
  #define CAN_ID10_EXT17_MASK           0x00020000UL
  #define CAN_ID10_STD0_MASK            0x00040000UL
  #define CAN_ID10_STD1_MASK            0x00080000UL
  #define CAN_ID10_STD2_MASK            0x00100000UL
  #define CAN_ID10_STD3_MASK            0x00200000UL
  #define CAN_ID10_STD4_MASK            0x00400000UL
  #define CAN_ID10_STD5_MASK            0x00800000UL
  #define CAN_ID10_STD6_MASK            0x01000000UL
  #define CAN_ID10_STD7_MASK            0x02000000UL
  #define CAN_ID10_STD8_MASK            0x04000000UL
  #define CAN_ID10_STD9_MASK            0x08000000UL
  #define CAN_ID10_STD10_MASK           0x10000000UL
  #define CAN_ID10_PRIO0_MASK           0x20000000UL
  #define CAN_ID10_PRIO1_MASK           0x40000000UL
  #define CAN_ID10_PRIO2_MASK           0x80000000UL
  #define CAN_ID10_EXT_MASK             0x0003FFFFUL
  #define CAN_ID10_EXT_BITNUM           0x00U
  #define CAN_ID10_STD_MASK             0x1FFC0000UL
  #define CAN_ID10_STD_BITNUM           0x12U
  #define CAN_ID10_PRIO_MASK            0xE0000000UL
  #define CAN_ID10_PRIO_BITNUM          0x1DU
  #define CAN_ID10                      (*((volatile dword *)0x0000E892))


  /*** CAN_WORD010 - Message Buffer 10 WORD0 Register; 0x0000E894 ***/
  union {
    dword Dword;
  } CAN_WORD010_STR;

  #define CAN_WORD010_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD010_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD010_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD010_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD010_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD010_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD010_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD010_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD010_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD010_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD010_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD010_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD010_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD010_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD010_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD010_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD010_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD010_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD010_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD010_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD010_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD010_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD010_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD010_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD010_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD010_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD010_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD010_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD010_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD010_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD010_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD010_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD010_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD010_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD010_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD010_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD010_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD010_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD010_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD010_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD010                   (*((volatile dword *)0x0000E894))


  /*** CAN_WORD110 - Message Buffer 10 WORD1 Register; 0x0000E896 ***/
  union {
    dword Dword;
  } CAN_WORD110_STR;

  #define CAN_WORD110_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD110_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD110_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD110_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD110_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD110_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD110_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD110_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD110_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD110_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD110_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD110_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD110_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD110_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD110_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD110_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD110_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD110_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD110_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD110_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD110_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD110_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD110_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD110_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD110_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD110_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD110_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD110_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD110_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD110_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD110_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD110_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD110_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD110_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD110_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD110_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD110_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD110_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD110_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD110_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD110                   (*((volatile dword *)0x0000E896))


  /*** CAN_CS11 - Message Buffer 11 CS Register; 0x0000E898 ***/
  union {
    dword Dword;
  } CAN_CS11_STR;

  #define CAN_CS11_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS11_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS11_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS11_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS11_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS11_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS11_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS11_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS11_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS11_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS11_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS11_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS11_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS11_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS11_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS11_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS11_DLC0_MASK            0x00010000UL
  #define CAN_CS11_DLC1_MASK            0x00020000UL
  #define CAN_CS11_DLC2_MASK            0x00040000UL
  #define CAN_CS11_DLC3_MASK            0x00080000UL
  #define CAN_CS11_RTR_MASK             0x00100000UL
  #define CAN_CS11_IDE_MASK             0x00200000UL
  #define CAN_CS11_SRR_MASK             0x00400000UL
  #define CAN_CS11_CODE0_MASK           0x01000000UL
  #define CAN_CS11_CODE1_MASK           0x02000000UL
  #define CAN_CS11_CODE2_MASK           0x04000000UL
  #define CAN_CS11_CODE3_MASK           0x08000000UL
  #define CAN_CS11_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS11_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS11_DLC_MASK             0x000F0000UL
  #define CAN_CS11_DLC_BITNUM           0x10U
  #define CAN_CS11_CODE_MASK            0x0F000000UL
  #define CAN_CS11_CODE_BITNUM          0x18U
  #define CAN_CS11                      (*((volatile dword *)0x0000E898))


  /*** CAN_ID11 - Message Buffer 11 ID Register; 0x0000E89A ***/
  union {
    dword Dword;
  } CAN_ID11_STR;

  #define CAN_ID11_EXT0_MASK            0x01UL
  #define CAN_ID11_EXT1_MASK            0x02UL
  #define CAN_ID11_EXT2_MASK            0x04UL
  #define CAN_ID11_EXT3_MASK            0x08UL
  #define CAN_ID11_EXT4_MASK            0x10UL
  #define CAN_ID11_EXT5_MASK            0x20UL
  #define CAN_ID11_EXT6_MASK            0x40UL
  #define CAN_ID11_EXT7_MASK            0x80UL
  #define CAN_ID11_EXT8_MASK            0x0100UL
  #define CAN_ID11_EXT9_MASK            0x0200UL
  #define CAN_ID11_EXT10_MASK           0x0400UL
  #define CAN_ID11_EXT11_MASK           0x0800UL
  #define CAN_ID11_EXT12_MASK           0x1000UL
  #define CAN_ID11_EXT13_MASK           0x2000UL
  #define CAN_ID11_EXT14_MASK           0x4000UL
  #define CAN_ID11_EXT15_MASK           0x8000UL
  #define CAN_ID11_EXT16_MASK           0x00010000UL
  #define CAN_ID11_EXT17_MASK           0x00020000UL
  #define CAN_ID11_STD0_MASK            0x00040000UL
  #define CAN_ID11_STD1_MASK            0x00080000UL
  #define CAN_ID11_STD2_MASK            0x00100000UL
  #define CAN_ID11_STD3_MASK            0x00200000UL
  #define CAN_ID11_STD4_MASK            0x00400000UL
  #define CAN_ID11_STD5_MASK            0x00800000UL
  #define CAN_ID11_STD6_MASK            0x01000000UL
  #define CAN_ID11_STD7_MASK            0x02000000UL
  #define CAN_ID11_STD8_MASK            0x04000000UL
  #define CAN_ID11_STD9_MASK            0x08000000UL
  #define CAN_ID11_STD10_MASK           0x10000000UL
  #define CAN_ID11_PRIO0_MASK           0x20000000UL
  #define CAN_ID11_PRIO1_MASK           0x40000000UL
  #define CAN_ID11_PRIO2_MASK           0x80000000UL
  #define CAN_ID11_EXT_MASK             0x0003FFFFUL
  #define CAN_ID11_EXT_BITNUM           0x00U
  #define CAN_ID11_STD_MASK             0x1FFC0000UL
  #define CAN_ID11_STD_BITNUM           0x12U
  #define CAN_ID11_PRIO_MASK            0xE0000000UL
  #define CAN_ID11_PRIO_BITNUM          0x1DU
  #define CAN_ID11                      (*((volatile dword *)0x0000E89A))


  /*** CAN_WORD011 - Message Buffer 11 WORD0 Register; 0x0000E89C ***/
  union {
    dword Dword;
  } CAN_WORD011_STR;

  #define CAN_WORD011_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD011_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD011_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD011_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD011_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD011_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD011_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD011_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD011_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD011_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD011_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD011_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD011_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD011_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD011_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD011_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD011_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD011_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD011_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD011_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD011_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD011_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD011_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD011_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD011_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD011_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD011_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD011_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD011_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD011_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD011_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD011_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD011_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD011_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD011_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD011_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD011_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD011_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD011_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD011_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD011                   (*((volatile dword *)0x0000E89C))


  /*** CAN_WORD111 - Message Buffer 11 WORD1 Register; 0x0000E89E ***/
  union {
    dword Dword;
  } CAN_WORD111_STR;

  #define CAN_WORD111_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD111_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD111_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD111_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD111_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD111_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD111_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD111_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD111_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD111_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD111_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD111_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD111_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD111_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD111_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD111_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD111_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD111_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD111_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD111_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD111_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD111_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD111_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD111_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD111_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD111_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD111_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD111_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD111_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD111_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD111_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD111_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD111_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD111_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD111_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD111_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD111_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD111_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD111_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD111_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD111                   (*((volatile dword *)0x0000E89E))


  /*** CAN_CS12 - Message Buffer 12 CS Register; 0x0000E8A0 ***/
  union {
    dword Dword;
  } CAN_CS12_STR;

  #define CAN_CS12_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS12_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS12_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS12_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS12_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS12_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS12_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS12_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS12_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS12_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS12_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS12_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS12_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS12_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS12_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS12_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS12_DLC0_MASK            0x00010000UL
  #define CAN_CS12_DLC1_MASK            0x00020000UL
  #define CAN_CS12_DLC2_MASK            0x00040000UL
  #define CAN_CS12_DLC3_MASK            0x00080000UL
  #define CAN_CS12_RTR_MASK             0x00100000UL
  #define CAN_CS12_IDE_MASK             0x00200000UL
  #define CAN_CS12_SRR_MASK             0x00400000UL
  #define CAN_CS12_CODE0_MASK           0x01000000UL
  #define CAN_CS12_CODE1_MASK           0x02000000UL
  #define CAN_CS12_CODE2_MASK           0x04000000UL
  #define CAN_CS12_CODE3_MASK           0x08000000UL
  #define CAN_CS12_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS12_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS12_DLC_MASK             0x000F0000UL
  #define CAN_CS12_DLC_BITNUM           0x10U
  #define CAN_CS12_CODE_MASK            0x0F000000UL
  #define CAN_CS12_CODE_BITNUM          0x18U
  #define CAN_CS12                      (*((volatile dword *)0x0000E8A0))


  /*** CAN_ID12 - Message Buffer 12 ID Register; 0x0000E8A2 ***/
  union {
    dword Dword;
  } CAN_ID12_STR;

  #define CAN_ID12_EXT0_MASK            0x01UL
  #define CAN_ID12_EXT1_MASK            0x02UL
  #define CAN_ID12_EXT2_MASK            0x04UL
  #define CAN_ID12_EXT3_MASK            0x08UL
  #define CAN_ID12_EXT4_MASK            0x10UL
  #define CAN_ID12_EXT5_MASK            0x20UL
  #define CAN_ID12_EXT6_MASK            0x40UL
  #define CAN_ID12_EXT7_MASK            0x80UL
  #define CAN_ID12_EXT8_MASK            0x0100UL
  #define CAN_ID12_EXT9_MASK            0x0200UL
  #define CAN_ID12_EXT10_MASK           0x0400UL
  #define CAN_ID12_EXT11_MASK           0x0800UL
  #define CAN_ID12_EXT12_MASK           0x1000UL
  #define CAN_ID12_EXT13_MASK           0x2000UL
  #define CAN_ID12_EXT14_MASK           0x4000UL
  #define CAN_ID12_EXT15_MASK           0x8000UL
  #define CAN_ID12_EXT16_MASK           0x00010000UL
  #define CAN_ID12_EXT17_MASK           0x00020000UL
  #define CAN_ID12_STD0_MASK            0x00040000UL
  #define CAN_ID12_STD1_MASK            0x00080000UL
  #define CAN_ID12_STD2_MASK            0x00100000UL
  #define CAN_ID12_STD3_MASK            0x00200000UL
  #define CAN_ID12_STD4_MASK            0x00400000UL
  #define CAN_ID12_STD5_MASK            0x00800000UL
  #define CAN_ID12_STD6_MASK            0x01000000UL
  #define CAN_ID12_STD7_MASK            0x02000000UL
  #define CAN_ID12_STD8_MASK            0x04000000UL
  #define CAN_ID12_STD9_MASK            0x08000000UL
  #define CAN_ID12_STD10_MASK           0x10000000UL
  #define CAN_ID12_PRIO0_MASK           0x20000000UL
  #define CAN_ID12_PRIO1_MASK           0x40000000UL
  #define CAN_ID12_PRIO2_MASK           0x80000000UL
  #define CAN_ID12_EXT_MASK             0x0003FFFFUL
  #define CAN_ID12_EXT_BITNUM           0x00U
  #define CAN_ID12_STD_MASK             0x1FFC0000UL
  #define CAN_ID12_STD_BITNUM           0x12U
  #define CAN_ID12_PRIO_MASK            0xE0000000UL
  #define CAN_ID12_PRIO_BITNUM          0x1DU
  #define CAN_ID12                      (*((volatile dword *)0x0000E8A2))


  /*** CAN_WORD012 - Message Buffer 12 WORD0 Register; 0x0000E8A4 ***/
  union {
    dword Dword;
  } CAN_WORD012_STR;

  #define CAN_WORD012_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD012_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD012_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD012_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD012_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD012_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD012_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD012_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD012_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD012_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD012_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD012_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD012_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD012_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD012_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD012_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD012_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD012_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD012_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD012_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD012_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD012_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD012_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD012_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD012_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD012_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD012_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD012_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD012_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD012_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD012_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD012_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD012_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD012_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD012_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD012_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD012_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD012_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD012_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD012_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD012                   (*((volatile dword *)0x0000E8A4))


  /*** CAN_WORD112 - Message Buffer 12 WORD1 Register; 0x0000E8A6 ***/
  union {
    dword Dword;
  } CAN_WORD112_STR;

  #define CAN_WORD112_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD112_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD112_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD112_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD112_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD112_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD112_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD112_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD112_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD112_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD112_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD112_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD112_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD112_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD112_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD112_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD112_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD112_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD112_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD112_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD112_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD112_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD112_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD112_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD112_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD112_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD112_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD112_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD112_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD112_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD112_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD112_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD112_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD112_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD112_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD112_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD112_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD112_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD112_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD112_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD112                   (*((volatile dword *)0x0000E8A6))


  /*** CAN_CS13 - Message Buffer 13 CS Register; 0x0000E8A8 ***/
  union {
    dword Dword;
  } CAN_CS13_STR;

  #define CAN_CS13_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS13_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS13_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS13_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS13_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS13_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS13_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS13_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS13_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS13_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS13_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS13_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS13_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS13_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS13_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS13_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS13_DLC0_MASK            0x00010000UL
  #define CAN_CS13_DLC1_MASK            0x00020000UL
  #define CAN_CS13_DLC2_MASK            0x00040000UL
  #define CAN_CS13_DLC3_MASK            0x00080000UL
  #define CAN_CS13_RTR_MASK             0x00100000UL
  #define CAN_CS13_IDE_MASK             0x00200000UL
  #define CAN_CS13_SRR_MASK             0x00400000UL
  #define CAN_CS13_CODE0_MASK           0x01000000UL
  #define CAN_CS13_CODE1_MASK           0x02000000UL
  #define CAN_CS13_CODE2_MASK           0x04000000UL
  #define CAN_CS13_CODE3_MASK           0x08000000UL
  #define CAN_CS13_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS13_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS13_DLC_MASK             0x000F0000UL
  #define CAN_CS13_DLC_BITNUM           0x10U
  #define CAN_CS13_CODE_MASK            0x0F000000UL
  #define CAN_CS13_CODE_BITNUM          0x18U
  #define CAN_CS13                      (*((volatile dword *)0x0000E8A8))


  /*** CAN_ID13 - Message Buffer 13 ID Register; 0x0000E8AA ***/
  union {
    dword Dword;
  } CAN_ID13_STR;

  #define CAN_ID13_EXT0_MASK            0x01UL
  #define CAN_ID13_EXT1_MASK            0x02UL
  #define CAN_ID13_EXT2_MASK            0x04UL
  #define CAN_ID13_EXT3_MASK            0x08UL
  #define CAN_ID13_EXT4_MASK            0x10UL
  #define CAN_ID13_EXT5_MASK            0x20UL
  #define CAN_ID13_EXT6_MASK            0x40UL
  #define CAN_ID13_EXT7_MASK            0x80UL
  #define CAN_ID13_EXT8_MASK            0x0100UL
  #define CAN_ID13_EXT9_MASK            0x0200UL
  #define CAN_ID13_EXT10_MASK           0x0400UL
  #define CAN_ID13_EXT11_MASK           0x0800UL
  #define CAN_ID13_EXT12_MASK           0x1000UL
  #define CAN_ID13_EXT13_MASK           0x2000UL
  #define CAN_ID13_EXT14_MASK           0x4000UL
  #define CAN_ID13_EXT15_MASK           0x8000UL
  #define CAN_ID13_EXT16_MASK           0x00010000UL
  #define CAN_ID13_EXT17_MASK           0x00020000UL
  #define CAN_ID13_STD0_MASK            0x00040000UL
  #define CAN_ID13_STD1_MASK            0x00080000UL
  #define CAN_ID13_STD2_MASK            0x00100000UL
  #define CAN_ID13_STD3_MASK            0x00200000UL
  #define CAN_ID13_STD4_MASK            0x00400000UL
  #define CAN_ID13_STD5_MASK            0x00800000UL
  #define CAN_ID13_STD6_MASK            0x01000000UL
  #define CAN_ID13_STD7_MASK            0x02000000UL
  #define CAN_ID13_STD8_MASK            0x04000000UL
  #define CAN_ID13_STD9_MASK            0x08000000UL
  #define CAN_ID13_STD10_MASK           0x10000000UL
  #define CAN_ID13_PRIO0_MASK           0x20000000UL
  #define CAN_ID13_PRIO1_MASK           0x40000000UL
  #define CAN_ID13_PRIO2_MASK           0x80000000UL
  #define CAN_ID13_EXT_MASK             0x0003FFFFUL
  #define CAN_ID13_EXT_BITNUM           0x00U
  #define CAN_ID13_STD_MASK             0x1FFC0000UL
  #define CAN_ID13_STD_BITNUM           0x12U
  #define CAN_ID13_PRIO_MASK            0xE0000000UL
  #define CAN_ID13_PRIO_BITNUM          0x1DU
  #define CAN_ID13                      (*((volatile dword *)0x0000E8AA))


  /*** CAN_WORD013 - Message Buffer 13 WORD0 Register; 0x0000E8AC ***/
  union {
    dword Dword;
  } CAN_WORD013_STR;

  #define CAN_WORD013_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD013_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD013_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD013_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD013_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD013_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD013_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD013_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD013_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD013_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD013_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD013_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD013_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD013_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD013_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD013_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD013_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD013_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD013_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD013_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD013_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD013_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD013_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD013_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD013_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD013_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD013_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD013_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD013_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD013_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD013_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD013_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD013_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD013_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD013_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD013_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD013_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD013_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD013_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD013_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD013                   (*((volatile dword *)0x0000E8AC))


  /*** CAN_WORD113 - Message Buffer 13 WORD1 Register; 0x0000E8AE ***/
  union {
    dword Dword;
  } CAN_WORD113_STR;

  #define CAN_WORD113_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD113_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD113_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD113_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD113_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD113_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD113_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD113_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD113_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD113_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD113_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD113_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD113_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD113_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD113_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD113_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD113_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD113_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD113_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD113_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD113_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD113_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD113_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD113_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD113_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD113_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD113_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD113_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD113_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD113_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD113_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD113_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD113_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD113_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD113_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD113_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD113_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD113_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD113_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD113_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD113                   (*((volatile dword *)0x0000E8AE))


  /*** CAN_CS14 - Message Buffer 14 CS Register; 0x0000E8B0 ***/
  union {
    dword Dword;
  } CAN_CS14_STR;

  #define CAN_CS14_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS14_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS14_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS14_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS14_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS14_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS14_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS14_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS14_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS14_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS14_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS14_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS14_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS14_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS14_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS14_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS14_DLC0_MASK            0x00010000UL
  #define CAN_CS14_DLC1_MASK            0x00020000UL
  #define CAN_CS14_DLC2_MASK            0x00040000UL
  #define CAN_CS14_DLC3_MASK            0x00080000UL
  #define CAN_CS14_RTR_MASK             0x00100000UL
  #define CAN_CS14_IDE_MASK             0x00200000UL
  #define CAN_CS14_SRR_MASK             0x00400000UL
  #define CAN_CS14_CODE0_MASK           0x01000000UL
  #define CAN_CS14_CODE1_MASK           0x02000000UL
  #define CAN_CS14_CODE2_MASK           0x04000000UL
  #define CAN_CS14_CODE3_MASK           0x08000000UL
  #define CAN_CS14_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS14_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS14_DLC_MASK             0x000F0000UL
  #define CAN_CS14_DLC_BITNUM           0x10U
  #define CAN_CS14_CODE_MASK            0x0F000000UL
  #define CAN_CS14_CODE_BITNUM          0x18U
  #define CAN_CS14                      (*((volatile dword *)0x0000E8B0))


  /*** CAN_ID14 - Message Buffer 14 ID Register; 0x0000E8B2 ***/
  union {
    dword Dword;
  } CAN_ID14_STR;

  #define CAN_ID14_EXT0_MASK            0x01UL
  #define CAN_ID14_EXT1_MASK            0x02UL
  #define CAN_ID14_EXT2_MASK            0x04UL
  #define CAN_ID14_EXT3_MASK            0x08UL
  #define CAN_ID14_EXT4_MASK            0x10UL
  #define CAN_ID14_EXT5_MASK            0x20UL
  #define CAN_ID14_EXT6_MASK            0x40UL
  #define CAN_ID14_EXT7_MASK            0x80UL
  #define CAN_ID14_EXT8_MASK            0x0100UL
  #define CAN_ID14_EXT9_MASK            0x0200UL
  #define CAN_ID14_EXT10_MASK           0x0400UL
  #define CAN_ID14_EXT11_MASK           0x0800UL
  #define CAN_ID14_EXT12_MASK           0x1000UL
  #define CAN_ID14_EXT13_MASK           0x2000UL
  #define CAN_ID14_EXT14_MASK           0x4000UL
  #define CAN_ID14_EXT15_MASK           0x8000UL
  #define CAN_ID14_EXT16_MASK           0x00010000UL
  #define CAN_ID14_EXT17_MASK           0x00020000UL
  #define CAN_ID14_STD0_MASK            0x00040000UL
  #define CAN_ID14_STD1_MASK            0x00080000UL
  #define CAN_ID14_STD2_MASK            0x00100000UL
  #define CAN_ID14_STD3_MASK            0x00200000UL
  #define CAN_ID14_STD4_MASK            0x00400000UL
  #define CAN_ID14_STD5_MASK            0x00800000UL
  #define CAN_ID14_STD6_MASK            0x01000000UL
  #define CAN_ID14_STD7_MASK            0x02000000UL
  #define CAN_ID14_STD8_MASK            0x04000000UL
  #define CAN_ID14_STD9_MASK            0x08000000UL
  #define CAN_ID14_STD10_MASK           0x10000000UL
  #define CAN_ID14_PRIO0_MASK           0x20000000UL
  #define CAN_ID14_PRIO1_MASK           0x40000000UL
  #define CAN_ID14_PRIO2_MASK           0x80000000UL
  #define CAN_ID14_EXT_MASK             0x0003FFFFUL
  #define CAN_ID14_EXT_BITNUM           0x00U
  #define CAN_ID14_STD_MASK             0x1FFC0000UL
  #define CAN_ID14_STD_BITNUM           0x12U
  #define CAN_ID14_PRIO_MASK            0xE0000000UL
  #define CAN_ID14_PRIO_BITNUM          0x1DU
  #define CAN_ID14                      (*((volatile dword *)0x0000E8B2))


  /*** CAN_WORD014 - Message Buffer 14 WORD0 Register; 0x0000E8B4 ***/
  union {
    dword Dword;
  } CAN_WORD014_STR;

  #define CAN_WORD014_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD014_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD014_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD014_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD014_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD014_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD014_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD014_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD014_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD014_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD014_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD014_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD014_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD014_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD014_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD014_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD014_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD014_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD014_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD014_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD014_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD014_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD014_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD014_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD014_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD014_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD014_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD014_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD014_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD014_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD014_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD014_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD014_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD014_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD014_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD014_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD014_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD014_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD014_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD014_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD014                   (*((volatile dword *)0x0000E8B4))


  /*** CAN_WORD114 - Message Buffer 14 WORD1 Register; 0x0000E8B6 ***/
  union {
    dword Dword;
  } CAN_WORD114_STR;

  #define CAN_WORD114_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD114_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD114_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD114_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD114_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD114_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD114_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD114_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD114_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD114_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD114_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD114_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD114_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD114_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD114_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD114_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD114_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD114_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD114_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD114_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD114_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD114_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD114_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD114_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD114_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD114_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD114_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD114_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD114_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD114_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD114_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD114_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD114_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD114_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD114_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD114_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD114_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD114_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD114_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD114_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD114                   (*((volatile dword *)0x0000E8B6))


  /*** CAN_CS15 - Message Buffer 15 CS Register; 0x0000E8B8 ***/
  union {
    dword Dword;
  } CAN_CS15_STR;

  #define CAN_CS15_TIME_STAMP0_MASK     0x01UL
  #define CAN_CS15_TIME_STAMP1_MASK     0x02UL
  #define CAN_CS15_TIME_STAMP2_MASK     0x04UL
  #define CAN_CS15_TIME_STAMP3_MASK     0x08UL
  #define CAN_CS15_TIME_STAMP4_MASK     0x10UL
  #define CAN_CS15_TIME_STAMP5_MASK     0x20UL
  #define CAN_CS15_TIME_STAMP6_MASK     0x40UL
  #define CAN_CS15_TIME_STAMP7_MASK     0x80UL
  #define CAN_CS15_TIME_STAMP8_MASK     0x0100UL
  #define CAN_CS15_TIME_STAMP9_MASK     0x0200UL
  #define CAN_CS15_TIME_STAMP10_MASK    0x0400UL
  #define CAN_CS15_TIME_STAMP11_MASK    0x0800UL
  #define CAN_CS15_TIME_STAMP12_MASK    0x1000UL
  #define CAN_CS15_TIME_STAMP13_MASK    0x2000UL
  #define CAN_CS15_TIME_STAMP14_MASK    0x4000UL
  #define CAN_CS15_TIME_STAMP15_MASK    0x8000UL
  #define CAN_CS15_DLC0_MASK            0x00010000UL
  #define CAN_CS15_DLC1_MASK            0x00020000UL
  #define CAN_CS15_DLC2_MASK            0x00040000UL
  #define CAN_CS15_DLC3_MASK            0x00080000UL
  #define CAN_CS15_RTR_MASK             0x00100000UL
  #define CAN_CS15_IDE_MASK             0x00200000UL
  #define CAN_CS15_SRR_MASK             0x00400000UL
  #define CAN_CS15_CODE0_MASK           0x01000000UL
  #define CAN_CS15_CODE1_MASK           0x02000000UL
  #define CAN_CS15_CODE2_MASK           0x04000000UL
  #define CAN_CS15_CODE3_MASK           0x08000000UL
  #define CAN_CS15_TIME_STAMP_MASK      0xFFFFUL
  #define CAN_CS15_TIME_STAMP_BITNUM    0x00U
  #define CAN_CS15_DLC_MASK             0x000F0000UL
  #define CAN_CS15_DLC_BITNUM           0x10U
  #define CAN_CS15_CODE_MASK            0x0F000000UL
  #define CAN_CS15_CODE_BITNUM          0x18U
  #define CAN_CS15                      (*((volatile dword *)0x0000E8B8))


  /*** CAN_ID15 - Message Buffer 15 ID Register; 0x0000E8BA ***/
  union {
    dword Dword;
  } CAN_ID15_STR;

  #define CAN_ID15_EXT0_MASK            0x01UL
  #define CAN_ID15_EXT1_MASK            0x02UL
  #define CAN_ID15_EXT2_MASK            0x04UL
  #define CAN_ID15_EXT3_MASK            0x08UL
  #define CAN_ID15_EXT4_MASK            0x10UL
  #define CAN_ID15_EXT5_MASK            0x20UL
  #define CAN_ID15_EXT6_MASK            0x40UL
  #define CAN_ID15_EXT7_MASK            0x80UL
  #define CAN_ID15_EXT8_MASK            0x0100UL
  #define CAN_ID15_EXT9_MASK            0x0200UL
  #define CAN_ID15_EXT10_MASK           0x0400UL
  #define CAN_ID15_EXT11_MASK           0x0800UL
  #define CAN_ID15_EXT12_MASK           0x1000UL
  #define CAN_ID15_EXT13_MASK           0x2000UL
  #define CAN_ID15_EXT14_MASK           0x4000UL
  #define CAN_ID15_EXT15_MASK           0x8000UL
  #define CAN_ID15_EXT16_MASK           0x00010000UL
  #define CAN_ID15_EXT17_MASK           0x00020000UL
  #define CAN_ID15_STD0_MASK            0x00040000UL
  #define CAN_ID15_STD1_MASK            0x00080000UL
  #define CAN_ID15_STD2_MASK            0x00100000UL
  #define CAN_ID15_STD3_MASK            0x00200000UL
  #define CAN_ID15_STD4_MASK            0x00400000UL
  #define CAN_ID15_STD5_MASK            0x00800000UL
  #define CAN_ID15_STD6_MASK            0x01000000UL
  #define CAN_ID15_STD7_MASK            0x02000000UL
  #define CAN_ID15_STD8_MASK            0x04000000UL
  #define CAN_ID15_STD9_MASK            0x08000000UL
  #define CAN_ID15_STD10_MASK           0x10000000UL
  #define CAN_ID15_PRIO0_MASK           0x20000000UL
  #define CAN_ID15_PRIO1_MASK           0x40000000UL
  #define CAN_ID15_PRIO2_MASK           0x80000000UL
  #define CAN_ID15_EXT_MASK             0x0003FFFFUL
  #define CAN_ID15_EXT_BITNUM           0x00U
  #define CAN_ID15_STD_MASK             0x1FFC0000UL
  #define CAN_ID15_STD_BITNUM           0x12U
  #define CAN_ID15_PRIO_MASK            0xE0000000UL
  #define CAN_ID15_PRIO_BITNUM          0x1DU
  #define CAN_ID15                      (*((volatile dword *)0x0000E8BA))


  /*** CAN_WORD015 - Message Buffer 15 WORD0 Register; 0x0000E8BC ***/
  union {
    dword Dword;
  } CAN_WORD015_STR;

  #define CAN_WORD015_DATA_BYTE_3_0_MASK 0x01UL
  #define CAN_WORD015_DATA_BYTE_3_1_MASK 0x02UL
  #define CAN_WORD015_DATA_BYTE_3_2_MASK 0x04UL
  #define CAN_WORD015_DATA_BYTE_3_3_MASK 0x08UL
  #define CAN_WORD015_DATA_BYTE_3_4_MASK 0x10UL
  #define CAN_WORD015_DATA_BYTE_3_5_MASK 0x20UL
  #define CAN_WORD015_DATA_BYTE_3_6_MASK 0x40UL
  #define CAN_WORD015_DATA_BYTE_3_7_MASK 0x80UL
  #define CAN_WORD015_DATA_BYTE_2_0_MASK 0x0100UL
  #define CAN_WORD015_DATA_BYTE_2_1_MASK 0x0200UL
  #define CAN_WORD015_DATA_BYTE_2_2_MASK 0x0400UL
  #define CAN_WORD015_DATA_BYTE_2_3_MASK 0x0800UL
  #define CAN_WORD015_DATA_BYTE_2_4_MASK 0x1000UL
  #define CAN_WORD015_DATA_BYTE_2_5_MASK 0x2000UL
  #define CAN_WORD015_DATA_BYTE_2_6_MASK 0x4000UL
  #define CAN_WORD015_DATA_BYTE_2_7_MASK 0x8000UL
  #define CAN_WORD015_DATA_BYTE_1_0_MASK 0x00010000UL
  #define CAN_WORD015_DATA_BYTE_1_1_MASK 0x00020000UL
  #define CAN_WORD015_DATA_BYTE_1_2_MASK 0x00040000UL
  #define CAN_WORD015_DATA_BYTE_1_3_MASK 0x00080000UL
  #define CAN_WORD015_DATA_BYTE_1_4_MASK 0x00100000UL
  #define CAN_WORD015_DATA_BYTE_1_5_MASK 0x00200000UL
  #define CAN_WORD015_DATA_BYTE_1_6_MASK 0x00400000UL
  #define CAN_WORD015_DATA_BYTE_1_7_MASK 0x00800000UL
  #define CAN_WORD015_DATA_BYTE_0_0_MASK 0x01000000UL
  #define CAN_WORD015_DATA_BYTE_0_1_MASK 0x02000000UL
  #define CAN_WORD015_DATA_BYTE_0_2_MASK 0x04000000UL
  #define CAN_WORD015_DATA_BYTE_0_3_MASK 0x08000000UL
  #define CAN_WORD015_DATA_BYTE_0_4_MASK 0x10000000UL
  #define CAN_WORD015_DATA_BYTE_0_5_MASK 0x20000000UL
  #define CAN_WORD015_DATA_BYTE_0_6_MASK 0x40000000UL
  #define CAN_WORD015_DATA_BYTE_0_7_MASK 0x80000000UL
  #define CAN_WORD015_DATA_BYTE_3_MASK  0xFFUL
  #define CAN_WORD015_DATA_BYTE_3_BITNUM 0x00U
  #define CAN_WORD015_DATA_BYTE_2_MASK  0xFF00UL
  #define CAN_WORD015_DATA_BYTE_2_BITNUM 0x08U
  #define CAN_WORD015_DATA_BYTE_1_MASK  0x00FF0000UL
  #define CAN_WORD015_DATA_BYTE_1_BITNUM 0x10U
  #define CAN_WORD015_DATA_BYTE_0_MASK  0xFF000000UL
  #define CAN_WORD015_DATA_BYTE_0_BITNUM 0x18U
  #define CAN_WORD015                   (*((volatile dword *)0x0000E8BC))


  /*** CAN_WORD115 - Message Buffer 15 WORD1 Register; 0x0000E8BE ***/
  union {
    dword Dword;
  } CAN_WORD115_STR;

  #define CAN_WORD115_DATA_BYTE_7_0_MASK 0x01UL
  #define CAN_WORD115_DATA_BYTE_7_1_MASK 0x02UL
  #define CAN_WORD115_DATA_BYTE_7_2_MASK 0x04UL
  #define CAN_WORD115_DATA_BYTE_7_3_MASK 0x08UL
  #define CAN_WORD115_DATA_BYTE_7_4_MASK 0x10UL
  #define CAN_WORD115_DATA_BYTE_7_5_MASK 0x20UL
  #define CAN_WORD115_DATA_BYTE_7_6_MASK 0x40UL
  #define CAN_WORD115_DATA_BYTE_7_7_MASK 0x80UL
  #define CAN_WORD115_DATA_BYTE_6_0_MASK 0x0100UL
  #define CAN_WORD115_DATA_BYTE_6_1_MASK 0x0200UL
  #define CAN_WORD115_DATA_BYTE_6_2_MASK 0x0400UL
  #define CAN_WORD115_DATA_BYTE_6_3_MASK 0x0800UL
  #define CAN_WORD115_DATA_BYTE_6_4_MASK 0x1000UL
  #define CAN_WORD115_DATA_BYTE_6_5_MASK 0x2000UL
  #define CAN_WORD115_DATA_BYTE_6_6_MASK 0x4000UL
  #define CAN_WORD115_DATA_BYTE_6_7_MASK 0x8000UL
  #define CAN_WORD115_DATA_BYTE_5_0_MASK 0x00010000UL
  #define CAN_WORD115_DATA_BYTE_5_1_MASK 0x00020000UL
  #define CAN_WORD115_DATA_BYTE_5_2_MASK 0x00040000UL
  #define CAN_WORD115_DATA_BYTE_5_3_MASK 0x00080000UL
  #define CAN_WORD115_DATA_BYTE_5_4_MASK 0x00100000UL
  #define CAN_WORD115_DATA_BYTE_5_5_MASK 0x00200000UL
  #define CAN_WORD115_DATA_BYTE_5_6_MASK 0x00400000UL
  #define CAN_WORD115_DATA_BYTE_5_7_MASK 0x00800000UL
  #define CAN_WORD115_DATA_BYTE_4_0_MASK 0x01000000UL
  #define CAN_WORD115_DATA_BYTE_4_1_MASK 0x02000000UL
  #define CAN_WORD115_DATA_BYTE_4_2_MASK 0x04000000UL
  #define CAN_WORD115_DATA_BYTE_4_3_MASK 0x08000000UL
  #define CAN_WORD115_DATA_BYTE_4_4_MASK 0x10000000UL
  #define CAN_WORD115_DATA_BYTE_4_5_MASK 0x20000000UL
  #define CAN_WORD115_DATA_BYTE_4_6_MASK 0x40000000UL
  #define CAN_WORD115_DATA_BYTE_4_7_MASK 0x80000000UL
  #define CAN_WORD115_DATA_BYTE_7_MASK  0xFFUL
  #define CAN_WORD115_DATA_BYTE_7_BITNUM 0x00U
  #define CAN_WORD115_DATA_BYTE_6_MASK  0xFF00UL
  #define CAN_WORD115_DATA_BYTE_6_BITNUM 0x08U
  #define CAN_WORD115_DATA_BYTE_5_MASK  0x00FF0000UL
  #define CAN_WORD115_DATA_BYTE_5_BITNUM 0x10U
  #define CAN_WORD115_DATA_BYTE_4_MASK  0xFF000000UL
  #define CAN_WORD115_DATA_BYTE_4_BITNUM 0x18U
  #define CAN_WORD115                   (*((volatile dword *)0x0000E8BE))


  dword Reserved3[448];                /* Reserved (unused) registers */

  /*** CAN_RXIMR0 - Rx Individual Mask Registers; 0x0000EC40 ***/
  union {
    dword Dword;
  } CAN_RXIMR0_STR;

  #define CAN_RXIMR0                    (*((volatile dword *)0x0000EC40))


  /*** CAN_RXIMR1 - Rx Individual Mask Registers; 0x0000EC42 ***/
  union {
    dword Dword;
  } CAN_RXIMR1_STR;

  #define CAN_RXIMR1                    (*((volatile dword *)0x0000EC42))


  /*** CAN_RXIMR2 - Rx Individual Mask Registers; 0x0000EC44 ***/
  union {
    dword Dword;
  } CAN_RXIMR2_STR;

  #define CAN_RXIMR2                    (*((volatile dword *)0x0000EC44))


  /*** CAN_RXIMR3 - Rx Individual Mask Registers; 0x0000EC46 ***/
  union {
    dword Dword;
  } CAN_RXIMR3_STR;

  #define CAN_RXIMR3                    (*((volatile dword *)0x0000EC46))


  /*** CAN_RXIMR4 - Rx Individual Mask Registers; 0x0000EC48 ***/
  union {
    dword Dword;
  } CAN_RXIMR4_STR;

  #define CAN_RXIMR4                    (*((volatile dword *)0x0000EC48))


  /*** CAN_RXIMR5 - Rx Individual Mask Registers; 0x0000EC4A ***/
  union {
    dword Dword;
  } CAN_RXIMR5_STR;

  #define CAN_RXIMR5                    (*((volatile dword *)0x0000EC4A))


  /*** CAN_RXIMR6 - Rx Individual Mask Registers; 0x0000EC4C ***/
  union {
    dword Dword;
  } CAN_RXIMR6_STR;

  #define CAN_RXIMR6                    (*((volatile dword *)0x0000EC4C))


  /*** CAN_RXIMR7 - Rx Individual Mask Registers; 0x0000EC4E ***/
  union {
    dword Dword;
  } CAN_RXIMR7_STR;

  #define CAN_RXIMR7                    (*((volatile dword *)0x0000EC4E))


  /*** CAN_RXIMR8 - Rx Individual Mask Registers; 0x0000EC50 ***/
  union {
    dword Dword;
  } CAN_RXIMR8_STR;

  #define CAN_RXIMR8                    (*((volatile dword *)0x0000EC50))


  /*** CAN_RXIMR9 - Rx Individual Mask Registers; 0x0000EC52 ***/
  union {
    dword Dword;
  } CAN_RXIMR9_STR;

  #define CAN_RXIMR9                    (*((volatile dword *)0x0000EC52))


  /*** CAN_RXIMR10 - Rx Individual Mask Registers; 0x0000EC54 ***/
  union {
    dword Dword;
  } CAN_RXIMR10_STR;

  #define CAN_RXIMR10                   (*((volatile dword *)0x0000EC54))


  /*** CAN_RXIMR11 - Rx Individual Mask Registers; 0x0000EC56 ***/
  union {
    dword Dword;
  } CAN_RXIMR11_STR;

  #define CAN_RXIMR11                   (*((volatile dword *)0x0000EC56))


  /*** CAN_RXIMR12 - Rx Individual Mask Registers; 0x0000EC58 ***/
  union {
    dword Dword;
  } CAN_RXIMR12_STR;

  #define CAN_RXIMR12                   (*((volatile dword *)0x0000EC58))


  /*** CAN_RXIMR13 - Rx Individual Mask Registers; 0x0000EC5A ***/
  union {
    dword Dword;
  } CAN_RXIMR13_STR;

  #define CAN_RXIMR13                   (*((volatile dword *)0x0000EC5A))


  /*** CAN_RXIMR14 - Rx Individual Mask Registers; 0x0000EC5C ***/
  union {
    dword Dword;
  } CAN_RXIMR14_STR;

  #define CAN_RXIMR14                   (*((volatile dword *)0x0000EC5C))


  /*** CAN_RXIMR15 - Rx Individual Mask Registers; 0x0000EC5E ***/
  union {
    dword Dword;
  } CAN_RXIMR15_STR;

  #define CAN_RXIMR15                   (*((volatile dword *)0x0000EC5E))


} CAN_PRPH;

















































#endif
/* __IO_Map_H */

/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
