/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : CyclicADC.c
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : Init_ADC
**     Version     : Component 01.349, Driver 01.25, CPU db: 3.50.001
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-05-15, 17:58, # CodeGen: 5
**     Abstract    :
**         This "Init_ADC" Peripheral Inspector implements the
**         Analog-to-Digital converter module (ADC), basic 
**         initialization and settings.
**     Settings    :
**          Component name                                 : CyclicADC
**          Device                                         : ADC12
**          Settings                                       : 
**            Clock setting                                : 
**              Clock divisor select value                 : 10
**              A/D Frequency                              : 10 MHz
**              Speed control                              : clock frequency =< 5MHz
**              Clock divisor select value 1               : 10
**              A/D Frequency 1                            : 10 MHz
**              Speed control 1                            : clock frequency =< 5MHz
**            Stop mode (0)                                : yes
**            Stop mode 1                                  : yes
**            ADC mode                                     : Triggered Parallel
**            Parallel mode                                : simultaneous
**            Trigger mode (0)                             : SYNC input or START bit
**            Trigger mode 1                               : SYNC input or START bit
**            Sampling time (0)                            : 2 ADC clocks
**            Sampling time 1                              : 2 ADC clocks
**            Power savings mode                           : Disabled
**            Power-up delay                               : 26
**            Auto standby                                 : Disabled
**            DMA trigger source                           : EOSI
**            High volt. ref. source 0                     : internal
**            Low volt. ref. source 0                      : internal
**            High volt. ref. source 1                     : internal
**            Low volt. ref. source 1                      : internal
**            A/D Channels                                 : 
**              Channels configuration                     : 
**                ANA0-ANA1                                : Single ended mode
**                ANA2-ANA3                                : Single ended mode
**                ANB0-ANB1                                : Single ended mode
**                ANB2-ANB3                                : Single ended mode
**                ANA4-ANA5                                : Differential mode
**                ANA6-ANA7                                : Differential mode
**                ANB4-ANB5                                : Differential mode
**                ANB6-ANB7                                : Differential mode
**              Sample 0                                   : Enabled
**                Channel                                  : GPIOA4/ANA4/ANC8/CMPD_IN0
**                Channel signal                           : rt4
**                Negative input                           : Enabled
**                  Channel                                : GPIOA5/ANA5/ANC9
**                  Channel signal                         : rt3
**              Sample 1                                   : Enabled
**                Channel                                  : GPIOA6/ANA6/ANC10
**                Channel signal                           : 
**                Negative input                           : Enabled
**                  Channel                                : GPIOA7/ANA7/ANC11
**                  Channel signal                         : 
**              Sample 2                                   : Disabled
**              Sample 3                                   : Disabled
**              Sample 4                                   : Disabled
**              Sample 5                                   : Disabled
**              Sample 6                                   : Disabled
**              Sample 7                                   : Disabled
**              Sample 8                                   : Enabled
**                Channel                                  : GPIOB4/ANB4/ANC12/CMPC_IN1
**                Channel signal                           : rt1
**                Negative input                           : Enabled
**                  Channel                                : GPIOB5/ANB5/ANC13/CMPC_IN2
**                  Channel signal                         : 
**              Sample 9                                   : Enabled
**                Channel                                  : GPIOB6/ANB6/ANC14/CMPB_IN1
**                Channel signal                           : rt2
**                Negative input                           : Enabled
**                  Channel                                : GPIOB7/ANB7/ANC15/CMPB_IN2
**                  Channel signal                         : 
**              Sample 10                                  : Disabled
**              Sample 11                                  : Disabled
**              Sample 12                                  : Disabled
**              Sample 13                                  : Disabled
**              Sample 14                                  : Disabled
**              Sample 15                                  : Disabled
**              Internal trigger (0)                       : Disabled
**              Internal trigger 1                         : Disabled
**            Zero crossing                                : 
**              Sample 0                                   : disabled
**              Sample 1                                   : disabled
**              Sample 2                                   : disabled
**              Sample 3                                   : disabled
**              Sample 4                                   : disabled
**              Sample 5                                   : disabled
**              Sample 6                                   : disabled
**              Sample 7                                   : disabled
**              Sample 8                                   : disabled
**              Sample 9                                   : disabled
**              Sample 10                                  : disabled
**              Sample 11                                  : disabled
**              Sample 12                                  : disabled
**              Sample 13                                  : disabled
**              Sample 14                                  : disabled
**              Sample 15                                  : disabled
**            Low limit                                    : 
**              Low limit register 0                       : 0
**              Low limit register 1                       : 0
**              Low limit register 2                       : 0
**              Low limit register 3                       : 0
**              Low limit register 4                       : 0
**              Low limit register 5                       : 0
**              Low limit register 6                       : 0
**              Low limit register 7                       : 0
**              Low limit register 8                       : 0
**              Low limit register 9                       : 0
**              Low limit register 10                      : 0
**              Low limit register 11                      : 0
**              Low limit register 12                      : 0
**              Low limit register 13                      : 0
**              Low limit register 14                      : 0
**              Low limit register 15                      : 0
**            High limit                                   : 
**              High limit register 0                      : 7FF8
**              High limit register 1                      : 7FF8
**              High limit register 2                      : 7FF8
**              High limit register 3                      : 7FF8
**              High limit register 4                      : 7FF8
**              High limit register 5                      : 7FF8
**              High limit register 6                      : 7FF8
**              High limit register 7                      : 7FF8
**              High limit register 8                      : 7FF8
**              High limit register 9                      : 7FF8
**              High limit register 10                     : 7FF8
**              High limit register 11                     : 7FF8
**              High limit register 12                     : 7FF8
**              High limit register 13                     : 7FF8
**              High limit register 14                     : 7FF8
**              High limit register 15                     : 7FF8
**            Offset                                       : 
**              Offset register 0                          : 4000
**              Offset register 1                          : 4000
**              Offset register 2                          : 4000
**              Offset register 3                          : 4000
**              Offset register 4                          : 4000
**              Offset register 5                          : 4000
**              Offset register 6                          : 4000
**              Offset register 7                          : 4000
**              Offset register 8                          : 4000
**              Offset register 9                          : 4000
**              Offset register 10                         : 4000
**              Offset register 11                         : 4000
**              Offset register 12                         : 4000
**              Offset register 13                         : 4000
**              Offset register 14                         : 4000
**              Offset register 15                         : 4000
**            Gain control                                 : 
**              ANA0                                       : x1 amplification
**              ANA1                                       : x1 amplification
**              ANA2                                       : x1 amplification
**              ANA3                                       : x1 amplification
**              ANA4                                       : x1 amplification
**              ANA5                                       : x1 amplification
**              ANA6                                       : x2 amplification
**              ANA7                                       : x2 amplification
**              ANB0                                       : x1 amplification
**              ANB1                                       : x1 amplification
**              ANB2                                       : x1 amplification
**              ANB3                                       : x1 amplification
**              ANB4                                       : x4 amplification
**              ANB5                                       : x4 amplification
**              ANB6                                       : x1 amplification
**              ANB7                                       : x1 amplification
**            Scan control                                 : 
**              Sample 0                                   : Continue
**              Sample 1                                   : Continue
**              Sample 2                                   : Continue
**              Sample 3                                   : Continue
**              Sample 4                                   : Continue
**              Sample 5                                   : Continue
**              Sample 6                                   : Continue
**              Sample 7                                   : Continue
**              Sample 8                                   : Continue
**              Sample 9                                   : Continue
**              Sample 10                                  : Continue
**              Sample 11                                  : Continue
**              Sample 12                                  : Continue
**              Sample 13                                  : Continue
**              Sample 14                                  : Continue
**              Sample 15                                  : Continue
**          Interrupts/DMA                                 : 
**            Conversion complete (0)                      : 
**              Interrupt                                  : INT_ADC12_CC0
**              End of scan interrupt                      : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : ADC_EndofScanISR
**              DMA request                                : Disabled
**            Conversion complete 1                        : 
**              Interrupt                                  : INT_ADC12_CC1
**              End of scan interrupt                      : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : 
**              DMA request                                : Disabled
**            Scan halted interrupt enable                 : 
**              Sample 0                                   : Disabled
**              Sample 1                                   : Disabled
**              Sample 2                                   : Disabled
**              Sample 3                                   : Disabled
**              Sample 4                                   : Disabled
**              Sample 5                                   : Disabled
**              Sample 6                                   : Disabled
**              Sample 7                                   : Disabled
**              Sample 8                                   : Disabled
**              Sample 9                                   : Disabled
**              Sample 10                                  : Disabled
**              Sample 11                                  : Disabled
**              Sample 12                                  : Disabled
**              Sample 13                                  : Disabled
**              Sample 14                                  : Disabled
**              Sample 15                                  : Disabled
**            Zero crossing or limit error                 : 
**              Interrupt                                  : INT_ADC12_ERR
**              Zero crossing interrupt                    : Disabled
**              Low limit error interrupt                  : Disabled
**              High limit error interrupt                 : Disabled
**              Interrupt priority                         : medium priority
**              ISR name                                   : 
**          Initialization                                 : 
**            Call Init method                             : yes
**            Enable peripheral clock                      : yes
**            Start ADC conversion (0)                     : no
**            Start ADC conversion 1                       : no
**            Power down ADC 0                             : no
**            Power down ADC 1                             : no
**     Contents    :
**         Init - void CyclicADC_Init(void);
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

/* MODULE CyclicADC. */

#include "CyclicADC.h"

/*
** ###################################################################
**
**  The interrupt service routine(s) must be implemented
**  by user in one of the following user modules.
**
**  If the "Generate ISR" option is enabled, Processor Expert generates
**  ISR templates in the CPU event module.
**
**  User modules:
**      ProcessorExpert.c
**      Events.c
**
** ###################################################################
#if defined(ADC_EndofScanISR_FAST_INT)
#pragma interrupt fast
#elif defined(ADC_EndofScanISR_VECT_TABLE_ISR_FAST_INT)
#pragma define_section interrupt_fast "interrupt_fast.text"  RX
#pragma section interrupt_fast begin
#pragma interrupt fast
#else
#pragma interrupt
#endif
void ADC_EndofScanISR(void)
{
// NOTE: The routine should include actions to clear the appropriate
//       interrupt flags.
//
}
*/
  
/*
** ===================================================================
**     Method      :  CyclicADC_Init (component Init_ADC)
**
**     Description :
**         This method initializes registers of the ADC module
**         according to this Peripheral Initialization settings. Call
**         this method in the user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void CyclicADC_Init(void)
{
  /* ADC12_SDIS: DS=0xFCFC */
  setReg16(ADC12_SDIS, 0xFCFCU);       /* Set sample disable register */ 
  /* ADC12_CLIST1: SAMPLE3=0,SAMPLE2=0,SAMPLE1=6,SAMPLE0=4 */
  setReg16(ADC12_CLIST1, 0x64U);       /* Set channel list register 1 */ 
  /* ADC12_CLIST3: SAMPLE11=0,SAMPLE10=0,SAMPLE9=0x0E,SAMPLE8=0x0C */
  setReg16(ADC12_CLIST3, 0xECU);       /* Set channel list register 3 */ 
  /* ADC12_LOLIM0: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM0, 0x00U);       /* Set low limit register 0 */ 
  /* ADC12_LOLIM1: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM1, 0x00U);       /* Set low limit register 1 */ 
  /* ADC12_LOLIM2: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM2, 0x00U);       /* Set low limit register 2 */ 
  /* ADC12_LOLIM3: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM3, 0x00U);       /* Set low limit register 3 */ 
  /* ADC12_LOLIM4: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM4, 0x00U);       /* Set low limit register 4 */ 
  /* ADC12_LOLIM5: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM5, 0x00U);       /* Set low limit register 5 */ 
  /* ADC12_LOLIM6: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM6, 0x00U);       /* Set low limit register 6 */ 
  /* ADC12_LOLIM7: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM7, 0x00U);       /* Set low limit register 7 */ 
  /* ADC12_LOLIM8: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM8, 0x00U);       /* Set low limit register 8 */ 
  /* ADC12_LOLIM9: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM9, 0x00U);       /* Set low limit register 9 */ 
  /* ADC12_LOLIM10: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM10, 0x00U);      /* Set low limit register 10 */ 
  /* ADC12_LOLIM11: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM11, 0x00U);      /* Set low limit register 11 */ 
  /* ADC12_LOLIM12: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM12, 0x00U);      /* Set low limit register 12 */ 
  /* ADC12_LOLIM13: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM13, 0x00U);      /* Set low limit register 13 */ 
  /* ADC12_LOLIM14: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM14, 0x00U);      /* Set low limit register 14 */ 
  /* ADC12_LOLIM15: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC12_LOLIM15, 0x00U);      /* Set low limit register 15 */ 
  /* ADC12_HILIM0: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM0, 0x7FF8U);     /* Set high limit register 0 */ 
  /* ADC12_HILIM1: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM1, 0x7FF8U);     /* Set high limit register 1 */ 
  /* ADC12_HILIM2: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM2, 0x7FF8U);     /* Set high limit register 2 */ 
  /* ADC12_HILIM3: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM3, 0x7FF8U);     /* Set high limit register 3 */ 
  /* ADC12_HILIM4: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM4, 0x7FF8U);     /* Set high limit register 4 */ 
  /* ADC12_HILIM5: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM5, 0x7FF8U);     /* Set high limit register 5 */ 
  /* ADC12_HILIM6: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM6, 0x7FF8U);     /* Set high limit register 6 */ 
  /* ADC12_HILIM7: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM7, 0x7FF8U);     /* Set high limit register 7 */ 
  /* ADC12_HILIM8: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM8, 0x7FF8U);     /* Set high limit register 8 */ 
  /* ADC12_HILIM9: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM9, 0x7FF8U);     /* Set high limit register 9 */ 
  /* ADC12_HILIM10: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM10, 0x7FF8U);    /* Set high limit register 10 */ 
  /* ADC12_HILIM11: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM11, 0x7FF8U);    /* Set high limit register 11 */ 
  /* ADC12_HILIM12: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM12, 0x7FF8U);    /* Set high limit register 12 */ 
  /* ADC12_HILIM13: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM13, 0x7FF8U);    /* Set high limit register 13 */ 
  /* ADC12_HILIM14: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM14, 0x7FF8U);    /* Set high limit register 14 */ 
  /* ADC12_HILIM15: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC12_HILIM15, 0x7FF8U);    /* Set high limit register 15 */ 
  /* ADC12_OFFST0: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST0, 0x4000U);     /* Set offset register 0 */ 
  /* ADC12_OFFST1: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST1, 0x4000U);     /* Set offset register 1 */ 
  /* ADC12_OFFST2: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST2, 0x4000U);     /* Set offset register 2 */ 
  /* ADC12_OFFST3: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST3, 0x4000U);     /* Set offset register 3 */ 
  /* ADC12_OFFST4: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST4, 0x4000U);     /* Set offset register 4 */ 
  /* ADC12_OFFST5: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST5, 0x4000U);     /* Set offset register 5 */ 
  /* ADC12_OFFST6: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST6, 0x4000U);     /* Set offset register 6 */ 
  /* ADC12_OFFST7: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST7, 0x4000U);     /* Set offset register 7 */ 
  /* ADC12_OFFST8: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST8, 0x4000U);     /* Set offset register 8 */ 
  /* ADC12_OFFST9: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST9, 0x4000U);     /* Set offset register 9 */ 
  /* ADC12_OFFST10: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST10, 0x4000U);    /* Set offset register 10 */ 
  /* ADC12_OFFST11: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST11, 0x4000U);    /* Set offset register 11 */ 
  /* ADC12_OFFST12: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST12, 0x4000U);    /* Set offset register 12 */ 
  /* ADC12_OFFST13: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST13, 0x4000U);    /* Set offset register 13 */ 
  /* ADC12_OFFST14: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST14, 0x4000U);    /* Set offset register 14 */ 
  /* ADC12_OFFST15: ??=0,OFFSET=0x0800,??=0,??=0,??=0 */
  setReg16(ADC12_OFFST15, 0x4000U);    /* Set offset register 15 */ 
  /* ADC12_ZXCTRL1: ZCE7=0,ZCE6=0,ZCE5=0,ZCE4=0,ZCE3=0,ZCE2=0,ZCE1=0,ZCE0=0 */
  setReg16(ADC12_ZXCTRL1, 0x00U);      /* Set zero crossing control register */ 
  /* ADC12_ZXCTRL2: ZCE15=0,ZCE14=0,ZCE13=0,ZCE12=0,ZCE11=0,ZCE10=0,ZCE9=0,ZCE8=0 */
  setReg16(ADC12_ZXCTRL2, 0x00U);      /* Set zero crossing control register */ 
  /* ADC12_GC1: GAIN7=1,GAIN6=1,GAIN5=0,GAIN4=0,GAIN3=0,GAIN2=0,GAIN1=0,GAIN0=0 */
  setReg16(ADC12_GC1, 0x5000U);        /* Set gain control 1 register */ 
  /* ADC12_GC2: GAIN15=0,GAIN14=0,GAIN13=2,GAIN12=2,GAIN11=0,GAIN10=0,GAIN9=0,GAIN8=0 */
  setReg16(ADC12_GC2, 0x0A00U);        /* Set gain control 2 register */ 
  /* ADC12_SCTRL: SC=0 */
  setReg16(ADC12_SCTRL, 0x00U);        /* Set scan control register */ 
  /* ADC12_SCHLTEN: SCHLTEN=0xFFFF */
  setReg16(ADC12_SCHLTEN, 0xFFFFU);    /* Set scan halted interrupt enable register */ 
  /* ADC12_CAL: SEL_VREFH_B=0,SEL_VREFLO_B=0,SEL_VREFH_A=0,SEL_VREFLO_A=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SEL_DAC_B=0,SEL_DAC_A=0 */
  setReg16(ADC12_CAL, 0x00U);          /* Set AD calibration mode and references */ 
  /* ADC12_PWR2: ??=0,??=0,DIV1=9,??=0,??=0,??=0,??=0,SPEEDB=0,SPEEDA=0 */
  setReg16(ADC12_PWR2, 0x0900U);       /* Set Power 2 register */ 
  /* ADC12_CTRL3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMASRC=0,SCNT1=0,SCNT0=0 */
  setReg16(ADC12_CTRL3, 0x00U);        /* Set control register 3 */ 
  /* ADC12_CTRL2: DMAEN1=0,STOP1=1,START1=0,SYNC1=1,EOSIE1=0,CHNCFG_H=0x0F,SIMULT=1,DIV0=9 */
  setReg16(ADC12_CTRL2, 0x57C9U);      /* Set control register 2 */ 
  /* ADC12_CTRL1: DMAEN0=0,STOP0=1,START0=0,SYNC0=1,EOSIE0=0,ZCIE=0,LLMTIE=0,HLMTIE=0,CHNCFG_L=0,??=0,SMODE=5 */
  setReg16(ADC12_CTRL1, 0x5005U);      /* Set control register 1 */ 
  /* ADC12_STAT: CIP0=0,CIP1=0,??=0,EOSI1=0,EOSI0=1,ZCI=0,LLMTI=0,HLMTI=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(ADC12_STAT, 0x0800U);       /* Clear EOSI flag(s) */ 
  /* ADC12_HILIMSTAT: HLS=0xFFFF */
  setReg16(ADC12_HILIMSTAT, 0xFFFFU);  /* Clear limit status flags */ 
  /* ADC12_LOLIMSTAT: LLS=0xFFFF */
  setReg16(ADC12_LOLIMSTAT, 0xFFFFU);  /* Clear limit status flags */ 
  /* ADC12_ZXSTAT: ZCS=0xFFFF */
  setReg16(ADC12_ZXSTAT, 0xFFFFU);     /* Clear limit status flags */ 
  /* ADC12_PWR: ASB=0,??=0,??=0,??=0,PSTS1=0,PSTS0=0,PUDELAY=0x1A,APD=0,??=0,PD1=0,PD0=0 */
  setReg16(ADC12_PWR, 0x01A0U);        /* Set power control register */ 
}

/* END CyclicADC. */

/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
