/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename    : TMR1.c
**     Project     : ProcessorExpert
**     Processor   : MC56F84789VLL
**     Component   : Init_TMR
**     Version     : Component 01.158, Driver 02.07, CPU db: 3.50.001
**     Compiler    : Metrowerks DSP C Compiler
**     Date/Time   : 2012-05-15, 17:58, # CodeGen: 5
**     Abstract    :
**         This "Init_TMR" Peripheral Inspector implements the
**         Quad Timer module (TMR), basic initialization
**         and settings.
**     Settings    :
**          Component name                                 : TMR1
**          Device                                         : TMRB0
**          Settings                                       : 
**            Clock settings                               : 
**              Primary source                             : 
**                Primary source                           : prescaler (IP BUS clock / 64)
**              Secondary source                           : 
**                Secondary source                         : counter 0 input pin
**            Operation mode                               : Count mode
**            Count once                                   : count repeatedly
**            Count length                                 : count till compare, then reinitialize
**            Count direction                              : up
**            Master mode                                  : Disabled
**            External OFLAG force                         : Disabled
**            Forced OFLAG value                           : 0
**            Force OFLAG output                           : no
**            Output enable                                : no
**            Output polarity                              : true
**            Input polarity                               : true
**            Co-channel initialization                    : Disabled
**            Input capture mode                           : Disabled
**            Reload on Capture                            : no
**            OutputMode                                   : toggle OFLAG output on successful compare
**            Compare load control 1                       : Disabled
**            Compare load control 2                       : Disabled
**            Debug mode action                            : Normal operation
**            Fault                                        : Disabled
**            Alternative load                             : Disabled
**            Input filter                                 : Disabled
**          Pins                                           : 
**            Output                                       : Disabled
**            Input 0                                      : Disabled
**            Input 1                                      : Disabled
**            Input 2                                      : Disabled
**            Input 3                                      : Disabled
**          Interrupts / DMA                               : 
**            Timer Channel                                : 
**              Interrupt                                  : INT_TMRB_0
**              Timer compare interrupt                    : Disabled
**              Timer overflow interrupt                   : Disabled
**              Input edge interrupt                       : Disabled
**              Compare 1 interrupt                        : Disabled
**              Compare 2 interrupt                        : Disabled
**              Interrupt priority                         : default
**              ISR name                                   : 
**              Input edge DMA                             : Disabled
**              Compare 1 DMA                              : Disabled
**              Compare 2 DMA                              : Disabled
**          Registers                                      : 
**            Timer Compare register 1                     : 782
**            Timer Compare register 2                     : 0000
**            Timer Capture register                       : 0000
**            Timer Load register                          : 0000
**            Timer Counter register                       : 0000
**            Timer Comparator Load register 1             : 0000
**            Timer Comparator Load register 2             : 0000
**          Initialization                                 : 
**            Call Init method                             : yes
**            Enable peripheral clock                      : yes
**            Enable channel                               : yes
**     Contents    :
**         Init - void TMR1_Init(void);
**
**     Copyright : 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**     
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

/* MODULE TMR1. */

#include "TMR1.h"

/*
** ===================================================================
**     Method      :  TMR1_Init (component Init_TMR)
**
**     Description :
**         This method initializes registers of the TMR module
**         according to this Peripheral Initialization Bean settings.
**         Call this method in the user code to initialize the
**         module. By default, the method is called by PE
**         automatically; see "Call Init method" property of the
**         bean for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void TMR1_Init(void)
{
  /* TMRB_0_CTRL: CM=0,PCS=0,SCS=0,ONCE=0,LENGTH=0,DIR=0,COINIT=0,OUTMODE=0 */
  setReg16(TMRB_0_CTRL, 0x00U);        /* Disable timer */ 
  setReg16(TMRB_0_COMP1, 0x030EU);     /* Set the Compare register 1 */ 
  setReg16(TMRB_0_COMP2, 0x00U);       /* Set the Compare register 2 */ 
  setReg16(TMRB_0_CAPT, 0x00U);        /* Set the Capture register */ 
  setReg16(TMRB_0_LOAD, 0x00U);        /* Set the Load register */ 
  setReg16(TMRB_0_CNTR, 0x00U);        /* Set the Counter register */ 
  /* TMRB_0_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=1,CAPTURE_MODE=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
  setReg16(TMRB_0_SCTRL, 0x0100U);     /* Set the Status and control register */ 
  /* TMRB_0_CMPLD1: COMPARATOR_LOAD_1=0 */
  setReg16(TMRB_0_CMPLD1, 0x00U);      /* Set the Comparator load register 1 */ 
  /* TMRB_0_CMPLD2: COMPARATOR_LOAD_2=0 */
  setReg16(TMRB_0_CMPLD2, 0x00U);      /* Set the Comparator load register 2 */ 
  /* TMRB_0_CSCTRL: DBG_EN=0,FAULT=0,ALT_LOAD=0,ROC=0,TCI=0,UP=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
  setReg16(TMRB_0_CSCTRL, 0x00U);      /* Set the Comparator status/control register */ 
  /* TMRB_0_FILT: ??=0,??=0,??=0,??=0,??=0,FILT_CNT=0,FILT_PER=0 */
  setReg16(TMRB_0_FILT, 0x00U);        /* Set Filter register */ 
  /* TMRB_0_DMA: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CMPLD2DE=0,CMPLD1DE=0,IEFDE=0 */
  setReg16(TMRB_0_DMA, 0x00U);         /* Set the DMA register */ 
  /* TMRB_0_CTRL: CM=1,PCS=0x0E,SCS=0,ONCE=0,LENGTH=1,DIR=0,COINIT=0,OUTMODE=3 */
  setReg16(TMRB_0_CTRL, 0x3C23U);      /* Set the Control register */ 
}

/* END TMR1. */

/*
** ###################################################################
**
**     This file was created by Processor Expert 5.3 [05.01]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/
