Scalable, Entry-Level 32-bit Microcontrollers (MCUs)

LPC11AXX

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特征

系统

  • Arm Cortex-M0 or Arm Cortex-M0+ processor, running at frequencies of up to 50 MHz
  • Arm Cortex-M0 or Arm Cortex-M0+ built-in nested vectored interrupt controller (NVIC)
  • Serial wire debug (SWD) and JTAG boundary scan modes supported
  • 系统节拍定时器

存储器

  • 高达 32 KB 的片上闪存编程存储器
  • Up to 4 KB on-chip EEPROM data memory; byte erasable and byte programmable
  • Up to 8 KB SRAM data memory
  • 16 KB boot ROM
  • In-System programming (ISP) and In-application programming (IAP) for flash and EEPROM via on-chip bootloader software
  • 包括基于ROM的32位整数除法以及I2C总线驱动程序

数字外设

  • Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode
  • Up to 16 pins are configurable with a digital input glitch filter for removing glitches with widths of 10ns or less and two pins are configurable for 50ns glitch filters
  • GPIO引脚可用作边沿和电平敏感的中断源
  • 单个引脚上的大电流输出驱动器(20 mA)
  • High-current sink drivers (20 mA) on two open-drain pins
  • Four general purpose counter/timers with a total of 16 capture inputs and 14 match outputs.
  • Programmable windowed watchdog timer (WWDT) with a dedicated, internal low-power watchdog oscillator (WDOsc)

模拟外设

  • 在8引脚中输入多路复用的10位ADC
  • 10位DAC,具有灵活的转换触发
  • 高度灵活的模拟比较器,具有可编程基准电压
  • 集成式温度传感器
  • 内部基准电压
  • Undervoltage lockout (UVLO) protection against power-supply droop below 2.4V

串行接口

  • USART with fractional baud rate generation, internal FIFO, and support for RS-485/9-bi mode and synchronous mode
  • 2个SSP控制器,带FIFO和多协议功能。Support data rates of up to 25 Mbit/s
  • I2C-bus interface supporting the full I2C-bus specification and fast-mode plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode

时钟生成

  • 工作范围从1 MHz到25 MHz的晶体振荡器
  • 12 MHz internal RC oscillator (IRC) trimmed to 1 % accuracy that can optionally be used as a system clock
  • Internal low-power, low-frequency oscillator (LFOsc) with programmable frequency output
  • 外部系统时钟的时钟输入(典型值为25 MHz)
  • PLL allows CPU operation up to the maximum CPU rate with the IRC, the external clock or the SysOsc as clock sources
  • Clock output function with divider that can reflect the SysOsc, IRC, the main clock, or the LFOsc

功率控制

  • Supports on reduced power mode: the Arm Sleep mode
  • Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call
  • 可利用任意中断将处理器从低功耗模式中唤醒
  • Power-on reset (POR).
  • Brownout detect (BOD) with two programmable thresholds for interrupt and one hardware controlled reset trip point
  • POR and BOD are always enabled for rapid UVLO protection against power supply voltage droop below 2.4

其他特性

  • 可用作芯片识别的唯一序列号
  • 3.3 V单电源(2.6 V至3.6 V)
  • Available as LQFP48, HVQFN33, and WLCSP20 packages

部件编号包含: LPC11A02UK, LPC11A04UK, LPC11A11FHN33, LPC11A12FBD48, LPC11A12FHN33, LPC11A13FHI33, LPC11A13JHI33, LPC11A14FBD48, LPC11A14FHN33, LPC11A14JBD48.

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