ISF  2.1
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ci_protocol_mbox.h
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1 /*
2  *
3  * Copyright (c) 2014, Freescale Semiconductor, Inc.
4  *
5 */
6 
7 /*!
8  * @file ci_protocol_mbox.h
9  *
10  * @brief Command interpreter header file for the legacy mailbox protocol.
11  *
12  */
13 
14 
15 #ifndef CI_PROTOCOL_MBOX_H_
16 #define CI_PROTOCOL_MBOX_H_
17 
18 
19 
20 
21 #include <IO_Map.h>
22 #include "isf.h"
23 
24 
25 
26 /*! @brief Define to enable CRC check. When enabled, CRC calculation is performed and CRC bytes
27  * are included in packets sent to the host. Also, CRC check is performed on receiving packets.
28  */
29 //#define MBOX_ENABLE_CRC
30 
31 
32 #ifdef MBOX_ENABLE_CRC
33  #define MBOX_CRC_BYTE_SIZE (2)
34 #else
35  #define MBOX_CRC_BYTE_SIZE (0)
36 #endif
37 
38 
39 #define SP_MB0 (0)
40 #define SP_MB1 (1)
41 #define SP_MB2 (2)
42 #define SP_MB3 (3)
43 #define SP_MB4 (4)
44 #define ISF_APP_ID_NULL (0)
45 
46 
47 
48 /*!
49  * @brief Mailbox designation for host command packet for read/write.
50  *
51 */
52 
53 // Write command message format. Host requesting to write.
54 #define MB_HOST_APP_ID pciMailboxes[0]
55 #define MB_HOST_CMD pciMailboxes[1]
56 #define MB_HOST_OFFSET pciMailboxes[2]
57 #define MB_HOST_COUNT pciMailboxes[3]
58 #define MB_HOST_CMD_SIZE(x) (GET_EXTENSION_BIT(x) == 0) ? 4 : 5 // Host command is 4 bytes normal mode, 6 is for extension mode, MB0-3
59 #define MB_HOST_OFFSET_EXT (uint16)((pciMailboxes[2] << 8) | pciMailboxes[3])
60 #define MB_HOST_COUNT_EXT pciMailboxes[4]
61 #define MB_HOST_WR_DATA_START (4)
62 
63 // Read command message format. Host requesting to read.
64 #define MB_RESP_APP_ID pciMailboxes[0]
65 #define MB_RESP_STATUS_CC pciMailboxes[1]
66 #define MB_RESP_BYTES_XFER pciMailboxes[2]
67 #define MB_RESP_COUNT pciMailboxes[3]
68 #define MB_RESP_INDEX_APP_ID (0)
69 #define MB_RESP_INDEX_STATUS_CC (1)
70 #define MB_RESP_INDEX_BYTES_XFER (2)
71 #define MB_RESP_INDEX_COUNT (3)
72 
73 #define MB_APP_RESP_SIZE (4) // App response is 4 bytes, MB0-3
74 #define MB_APP_RESP_DATA_START (4)
75 
76 #define CI_STREAMING_MODE (1)
77 #define CI_NON_STREAMING_MODE (0)
78 
79 
80 
81 
82 
83 /*!
84  * @brief Mailboxes write bit. Bit setting for the 4 byte \n
85  * command packet from host. Bit position has same meaning \n
86  * as the SP_WSTS0 register.
87 */
88 #define CMD_PACKET_BITS (0x0000000f) /// MB3 - MB0
89 
90 
91 /*!
92  * @brief Mailbox COCO bit position and mask.
93  *
94 */
95 #define COCO_BIT (7) // Bit position (starting at 0)
96 #define COCO_BIT_MASK (1 << COCO_BIT)
97 
98 /*!
99  * @brief Extension for length and offset.
100 */
101 #define EXTENSION_LENGTH_BIT (1) // Bit for 1 byte extension for offset and length
102 #define EXTENSION_LENGTH_BIT_BIT_MASK (1 << 7)
103 #define GET_EXTENSION_BIT(x) (((x) & EXTENSION_LENGTH_BIT_BIT_MASK )>> 7)
104 
105 /*!
106  * @brief Command byte partition. Command byte contains instruction \n
107  * value in all bits. This\n
108  * command is written by host to MB0.
109 */
110 #define WR_CMD_RSHIFT (0)
111 #define WR_CMD_MASK (0xff) // b[6:0]
112 #define WR_CMD_ID_MASK (0x7f)
113 
114 
115 
116 
117 /*! @brief Number of mailboxes available on this sytem.
118  */
119 #define MAX_NUM_MAILBOXES (32)
120 
121 
122 /*!
123  * @brief First mailbox number for data transfer at powerup.\n
124  * Note that the actual first mailbox available for data transfer\n
125  * depends on how the host configures the mailboxes for quick\n
126  * read.
127  */
128 #define FIRST_DATA_MAILBOX_NUM (4) // First 4 mailboxes (0-3) reserved for command packet
129 
130 /*!
131  * @brief Maximum number of mailboxes available on this system for \n
132  * data from/to host. Note that not all mailboxes designated for \n
133  * data payload may be available since the host could configure
134  * them for quick read.
135  */
136 #define NUM_DATA_MAILBOXES (MAX_NUM_MAILBOXES-FIRST_DATA_MAILBOX_NUM)
137 
138 
139 /*!
140  * @brief First mailbox number that can be configured for quick\n
141  * read data. Quick read data can be written to this mailbox\n
142  * mailbox number up 31.
143  */
144 #define FIRST_QR_MAILBOX_NUM (4) // First 4 mailboxes (0-3) reserved for command packet
145 
146 /*!
147  * @brief Quick read mask that is applied to mailboxes read by host\n
148  * to mask out mailboxes read by the host but not configured for\n
149  * quick read.
150  */
151 #define QR_MAILBOX_MASK ((uint32)0xffffffff << FIRST_QR_MAILBOX_NUM)
152 
153 
154 /*!
155  * @brief Maximum number of mailboxes available on this system for \n
156  * quick read. Note that not all mailboxes designated for \n
157  * data payload may be available since the host could configure
158  * them for quick read.
159  */
160 #define NUM_QR_MAILBOXES (MAX_NUM_MAILBOXES-FIRST_QR_MAILBOX_NUM)
161 
162 
163 #if (FIRST_QR_MAILBOX_NUM < FIRST_DATA_MAILBOX_NUM)
164 ERROR: Quick read starting mailbox cannot be less than first data mailbox!
165 #endif
166 
167 
168 
169 
170 
171 /*!
172  * @brief This structure holds the quick read configuration for all \n
173  * applicable mailboxes. The first 4 mailboxes are used for the \n
174  * command packet read/write. All other mailboxes can be configured \n
175  * as quick read.
176  *
177  * Note that this structure must be 2 bytes per Eve's command interpreter \n
178  * spec.
179  *
180  * @struct qr_config_t
181 */
182 typedef struct
183 {
186 } qr_config_t;
187 
188 
189 
190 
191 /*!
192  * @brief Command Interpreter Control Register Structure. \n
193  *
194  * reserved1 : Reserved Bits \n
195  * reserved2 : Reserved Bits \n
196  * blockTransferMode : 1 - Streaming mode enabled. 0 - Streaming mode disabled. \n
197  * reserved3 : Reserved Bits
198  *
199  * @struct ci_ctrl_reg_t
200  */
201 typedef union {
203  struct {
204  uint8 reserved1 :1; // Reserved
205  uint8 reserved2 :1; // Reserved
206  uint8 blockTransferMode :1; // Block Transfer mode
207  uint8 reserved3 :5; // Reserved
208  } Bits;
209 } ci_ctrl_reg_t;
210 
211 
212 /*!
213  * @brief Command Interpreter Registers Structure. Contains all CI registers. \n
214  *
215  * @struct ci_regs_t
216  */
217 typedef struct
218 {
221 } ci_regs_t;
222 
223 
224 /*! @brief Debug commands */
225 #define CI_CMD_DEBUG_LOOPBACK (120) // Must be greater than CI_CMD_LAST
226 
227 
228 extern isf_status_t ci_mbox_init(uint8 aprotocolID, void *apInitData);
229 extern isf_status_t ci_protocol_CB_mbox(uint32 anumBytes, uint8 *apSrc, uint32 *apnumDestBytes, uint8 *apDest);
230 
231 
232 #define ci_get_wr_appid() ((uint8)MB_HOST_APP_ID)
233 #define ci_get_wr_appid() ((uint8)MB_HOST_APP_ID)
234 #define ci_get_wr_cmd() ((uint8)((MB_HOST_CMD & WR_CMD_MASK) >> WR_CMD_RSHIFT))
235 #define ci_get_wr_cmdId() ((uint8)((MB_HOST_CMD & WR_CMD_ID_MASK) >> WR_CMD_RSHIFT))
236 #define ci_get_wr_offset(x) (GET_EXTENSION_BIT(x) == 0)? (uint16)(MB_HOST_OFFSET) : (uint16)(MB_HOST_OFFSET_EXT)
237 #define ci_get_wr_cnt(x) (GET_EXTENSION_BIT(x) == 0)? (uint16)(MB_HOST_COUNT) : (uint16)(MB_HOST_COUNT_EXT)
238 #define ci_get_first_mailbox(x) (GET_EXTENSION_BIT(x) == 0)? 4 : 5
239 
240 
241 // Initialize quick read configuration. Use a unique loop counter name so that
242 // it does not conflict with variables already in the function.
243 #define qr_config_clear() { \
244  int iii = MAX_NUM_MAILBOXES-1; \
245  do \
246  { \
247  ciRegisters.qr_config[iii].appId = 0; \
248  ciRegisters.qr_config[iii].byte_id = 0; \
249  } while(--iii >= 0); \
250  }
251 
252 // Note that the msb of the CRC value comes first. The CRC value is placed at the
253 // end of the buffer.
254 #define ci_insert_crc(insert_offset, crc16_value, pBuf) { \
255  pBuf[insert_offset + 0] = (uint8)((uint16)(crc16_value & 0xff00) >> 8);\
256  pBuf[insert_offset + 1] = (uint8)(crc16_value & 0xff);\
257  }
258 
259 
260 
261 
262 
263 
264 
265 #endif // CI_PROTOCOL_MBOX_H_
unsigned char uint8
This defines uint8 as unsigned char.
Definition: isf_types.h:18
Command Interpreter Registers Structure. Contains all CI registers. .
ci_ctrl_reg_t ciCtrlReg
#define NUM_QR_MAILBOXES
Maximum number of mailboxes available on this system for quick read. Note that not all mailboxes de...
unsigned long uint32
This defines uint32 as unsigned long.
Definition: isf_types.h:36
This structure holds the quick read configuration for all applicable mailboxes. The first 4 mailbox...
Command Interpreter Control Register Structure. .
isf_status_t ci_mbox_init(uint8 aprotocolID, void *apInitData)
Main ISF header file. Contains code common to all ISF components.
int32 isf_status_t
ISF return status type.
Definition: isf.h:51
isf_status_t ci_protocol_CB_mbox(uint32 anumBytes, uint8 *apSrc, uint32 *apnumDestBytes, uint8 *apDest)