73 #define MMA865x_WHOAMI_VALUE_8652 (0x4A)
74 #define MMA865x_WHOAMI_VALUE_8653 (0x5A)
81 #define MMA865x_SET_FIELD(name,val) (((val)<<MMA865x_##name##_SHIFT)&(MMA865x_##name##_MASK))
82 #define MMA865x_GET_FIELD(name,val) ((val&MMA865x_##name##_MASK)>>MMA865x_##name##_SHIFT)
87 #define MMA865x_ZYXOW_MASK 0x80
88 #define MMA865x_ZYXOW_SHIFT 7
89 #define MMA865x_ZOW_MASK 0x40
90 #define MMA865x_YOW_MASK 0x20
91 #define MMA865x_XOW_MASK 0x10
92 #define MMA865x_ZYXDR_MASK 0x08
93 #define MMA865x_ZYXDR_SHIFT 3
94 #define MMA865x_ZDR_MASK 0x04
95 #define MMA865x_YDR_MASK 0x02
96 #define MMA865x_XDR_MASK 0x01
107 #define MMA865x_F_OVF_MASK 0x80
108 #define MMA865x_F_WMRK_FLAG_MASK 0x40
109 #define MMA865x_F_CNT5_MASK 0x20
110 #define MMA865x_F_CNT4_MASK 0x10
111 #define MMA865x_F_CNT3_MASK 0x08
112 #define MMA865x_F_CNT2_MASK 0x04
113 #define MMA865x_F_CNT1_MASK 0x02
114 #define MMA865x_F_CNT0_MASK 0x01
115 #define MMA865x_F_CNT_MASK 0x3F
121 #define MMA865x_F_MODE1_MASK 0x80
122 #define MMA865x_F_MODE0_MASK 0x40
123 #define MMA865x_F_WMRK5_MASK 0x20
124 #define MMA865x_F_WMRK4_MASK 0x10
125 #define MMA865x_F_WMRK3_MASK 0x08
126 #define MMA865x_F_WMRK2_MASK 0x04
127 #define MMA865x_F_WMRK1_MASK 0x02
128 #define MMA865x_F_WMRK0_MASK 0x01
129 #define MMA865x_F_MODE_MASK 0xC0
130 #define MMA865x_F_WMRK_MASK 0x3F
132 #define MMA865x_F_MODE_DISABLED 0x00
133 #define MMA865x_F_MODE_CIRCULAR (MMA865x_F_MODE0_MASK)
134 #define MMA865x_F_MODE_FILL (MMA865x_F_MODE1_MASK)
135 #define MMA865x_F_MODE_TRIGGER (MMA865x_F_MODE1_MASK+MMA865x_F_MODE0_MASK)
141 #define MMA865x_TRIG_TRANS_MASK 0x20
142 #define MMA865x_TRIG_LNDPRT_MASK 0x10
143 #define MMA865x_TRIG_PULSE_MASK 0x08
144 #define MMA865x_TRIG_FF_MT_MASK 0x04
150 #define MMA865x_FGERR_MASK 0x80
151 #define MMA865x_FGT_4_MASK 0x40
152 #define MMA865x_FGT_3_MASK 0x20
153 #define MMA865x_FGT_2_MASK 0x10
154 #define MMA865x_FGT_1_MASK 0x08
155 #define MMA865x_FGT_0_MASK 0x04
156 #define MMA865x_FGT_MASK 0x7C
157 #define MMA865x_SYSMOD_MASK 0x03
159 #define MMA865x_SYSMOD_STANDBY 0x00
160 #define MMA865x_SYSMOD_WAKE 0x01
161 #define MMA865x_SYSMOD_SLEEP 0x02
166 #define MMA865x_SRC_ASLP_MASK 0x80
167 #define MMA865x_SRC_FIFO_MASK 0x40 // MMA865x only
168 #define MMA865x_SRC_TRANS_MASK 0x20
169 #define MMA865x_SRC_LNDPRT_MASK 0x10
170 #define MMA865x_SRC_PULSE_MASK 0x08
171 #define MMA865x_SRC_FF_MT_MASK 0x04
172 #define MMA865x_SRC_DRDY_MASK 0x01
177 #define MMA865x_MMA865xQ 0x0D
183 #define MMA865x_HPF_OUT_MASK 0x10 // MMA865x only
184 #define MMA865x_HPF_OUT_SHIFT 4
185 #define MMA865x_FS1_MASK 0x02
186 #define MMA865x_FS0_MASK 0x01
187 #define MMA865x_FS_MASK 0x03
188 #define MMA865x_FS_SHIFT 0
190 #define MMA865x_FULL_SCALE_2G 0x00
191 #define MMA865x_FULL_SCALE_4G (MMA865x_FS0_MASK)
192 #define MMA865x_FULL_SCALE_8G (MMA865x_FS1_MASK)
198 #define MMA865x_PULSE_HPF_BYP_MASK 0x20
199 #define MMA865x_PULSE_HPF_BYP_SHIFT 5
200 #define MMA865x_PULSE_LPF_EN_MASK 0x10
201 #define MMA865x_PULSE_LPF_EN_SHIFT 4
202 #define MMA865x_SEL1_MASK 0x02
203 #define MMA865x_SEL0_MASK 0x01
204 #define MMA865x_SEL_MASK 0x03
205 #define MMA865x_SEL_SHIFT 0
210 #define MMA865x_NEWLP_MASK 0x80
211 #define MMA865x_LO_MASK 0x40
212 #define MMA865x_LO_SHIFT 6
213 #define MMA865x_LAPO1_MASK 0x04
214 #define MMA865x_LAPO0_MASK 0x02
215 #define MMA865x_LAPO_MASK 0x06
216 #define MMA865x_LAPO_SHIFT 1
217 #define MMA865x_BAFRO_MASK 0x01
218 #define MMA865x_BAFRO_SHIFT 0
222 #define MMA865x_DBCNTM_MASK 0x80
223 #define MMA865x_DBCNTM_SHIFT 7
224 #define MMA865x_PL_EN_MASK 0x40
225 #define MMA865x_PL_EN_SHIFT 6
230 #define MMA865x_BKFR1_MASK 0x80
231 #define MMA865x_BKFR0_MASK 0x40
232 #define MMA865x_ZLOCK2_MASK 0x04
233 #define MMA865x_ZLOCK1_MASK 0x02
234 #define MMA865x_ZLOCK0_MASK 0x01
235 #define MMA865x_BKFR_MASK 0xC0
236 #define MMA865x_BKFR_SHIFT 6
237 #define MMA865x_ZLOCK_MASK 0x07
238 #define MMA865x_ZLOCK_SHIFT 0
243 #define MMA865x_P_L_THS4_MASK 0x80
244 #define MMA865x_P_L_THS3_MASK 0x40
245 #define MMA865x_P_L_THS2_MASK 0x20
246 #define MMA865x_P_L_THS1_MASK 0x10
247 #define MMA865x_P_L_THS0_MASK 0x08
248 #define MMA865x_HYS2_MASK 0x04
249 #define MMA865x_HYS1_MASK 0x02
250 #define MMA865x_HYS0_MASK 0x01
251 #define MMA865x_P_L_THS_MASK 0xF8
252 #define MMA865x_P_L_THS_SHIFT 3
253 #define MMA865x_HYS_MASK 0x07
254 #define MMA865x_HYS_SHIFT 0
259 #define MMA865x_ELE_MASK 0x80
260 #define MMA865x_ELE_SHIFT 7
261 #define MMA865x_OAE_MASK 0x40
262 #define MMA865x_OAE_SHIFT 6
263 #define MMA865x_ZEFE_MASK 0x20
264 #define MMA865x_ZEFE_SHIFT 5
265 #define MMA865x_YEFE_MASK 0x10
266 #define MMA865x_YEFE_SHIFT 4
267 #define MMA865x_XEFE_MASK 0x08
268 #define MMA865x_XEFE_SHIFT 3
272 #define MMA865x_EA_MASK 0x80
273 #define MMA865x_ZHE_MASK 0x20
274 #define MMA865x_ZHP_MASK 0x10
275 #define MMA865x_YHE_MASK 0x08
276 #define MMA865x_YHP_MASK 0x04
277 #define MMA865x_XHE_MASK 0x02
278 #define MMA865x_XHP_MASK 0x01
283 #define MMA865x_DBCNTM_MASK 0x80
284 #define MMA865x_DBCNTM_SHIFT 7
285 #define MMA865x_THS6_MASK 0x40
286 #define MMA865x_THS5_MASK 0x20
287 #define MMA865x_THS4_MASK 0x10
288 #define MMA865x_THS3_MASK 0x08
289 #define MMA865x_THS2_MASK 0x04
290 #define MMA865x_TXS1_MASK 0x02
291 #define MMA865x_THS0_MASK 0x01
292 #define MMA865x_THS_MASK 0x7F
293 #define MMA865x_THS_SHIFT 0
299 #define MMA865x_TELE_MASK 0x10
300 #define MMA865x_TELE_SHIFT 4
301 #define MMA865x_ZTEFE_MASK 0x08
302 #define MMA865x_ZTEFE_SHIFT 3
303 #define MMA865x_YTEFE_MASK 0x04
304 #define MMA865x_YTEFE_SHIFT 2
305 #define MMA865x_XTEFE_MASK 0x02
306 #define MMA865x_XTEFE_SHIFT 1
307 #define MMA865x_HPF_BYP_MASK 0x01
308 #define MMA865x_HPF_BYP_SHIFT 0
314 #define MMA865x_TEA_MASK 0x40
315 #define MMA865x_ZTRANSE_MASK 0x20
316 #define MMA865x_Z_TRANS_POL_MASK 0x10
317 #define MMA865x_YTRANSE_MASK 0x08
318 #define MMA865x_Y_TRANS_POL_MASK 0x04
319 #define MMA865x_XTRANSE_MASK 0x02
320 #define MMA865x_X_TRANS_POL_MASK 0x01
326 #define MMA865x_DPA_MASK 0x80
327 #define MMA865x_DPA_SHIFT 7
328 #define MMA865x_PELE_MASK 0x40
329 #define MMA865x_PELE_SHIFT 6
330 #define MMA865x_ZDPEFE_MASK 0x20
331 #define MMA865x_ZDPEFE_SHIFT 5
332 #define MMA865x_ZSPEFE_MASK 0x10
333 #define MMA865x_ZSPEFE_SHIFT 4
334 #define MMA865x_YDPEFE_MASK 0x08
335 #define MMA865x_YDPEFE_SHIFT 3
336 #define MMA865x_YSPEFE_MASK 0x04
337 #define MMA865x_YSPEFE_SHIFT 2
338 #define MMA865x_XDPEFE_MASK 0x02
339 #define MMA865x_XDPEFE_SHIFT 1
340 #define MMA865x_XSPEFE_MASK 0x01
341 #define MMA865x_XSPEFE_SHIFT 0
346 #define MMA865x_PEA_MASK 0x80
347 #define MMA865x_AXZ_MASK 0x40
348 #define MMA865x_AXY_MASK 0x20
349 #define MMA865x_AXX_MASK 0x10
350 #define MMA865x_DPE_MASK 0x08
351 #define MMA865x_POLZ_MASK 0x04
352 #define MMA865x_POLY_MASK 0x02
353 #define MMA865x_POLX_MASK 0x01
358 #define MMA865x_PTHS_MASK 0x7F
359 #define MMA865x_PTHS_SHIFT 0
364 #define MMA865x_ASLP_RATE1_MASK 0x80
365 #define MMA865x_ASLP_RATE0_MASK 0x40
366 #define MMA865x_DR2_MASK 0x20
367 #define MMA865x_DR1_MASK 0x10
368 #define MMA865x_DR0_MASK 0x08
369 #define MMA865x_LNOISE_MASK 0x04
370 #define MMA865x_FREAD_MASK 0x02
371 #define MMA865x_FREAD_SHIFT 1
372 #define MMA865x_ACTIVE_MASK 0x01
373 #define MMA865x_ASLP_RATE_MASK 0xC0
374 #define MMA865x_ASLP_RATE_SHIFT 6
375 #define MMA865x_DR_MASK 0x38
376 #define MMA865x_DR_SHIFT 3
378 #define MMA865x_ASLP_RATE_20MS 0x00
379 #define MMA865x_ASLP_RATE_80MS (MMA865x_ASLP_RATE0_MASK)
380 #define MMA865x_ASLP_RATE_160MS (MMA865x_ASLP_RATE1_MASK)
381 #define MMA865x_ASLP_RATE_640MS (MMA865x_ASLP_RATE1_MASK+MMA865x_ASLP_RATE0_MASK)
383 #define MMA865x_ASLP_RATE_50HZ (MMA865x_ASLP_RATE_20MS)
384 #define MMA865x_ASLP_RATE_12_5HZ (MMA865x_ASLP_RATE_80MS)
385 #define MMA865x_ASLP_RATE_6_25HZ (MMA865x_ASLP_RATE_160MS)
386 #define MMA865x_ASLP_RATE_1_56HZ (MMA865x_ASLP_RATE_640MS)
388 #define MMA865x_DATA_RATE_1250US 0x00
389 #define MMA865x_DATA_RATE_2500US (MMA865x_DR0_MASK)
390 #define MMA865x_DATA_RATE_5MS (MMA865x_DR1_MASK)
391 #define MMA865x_DATA_RATE_10MS (MMA865x_DR1_MASK+MMA865x_DR0_MASK)
392 #define MMA865x_DATA_RATE_20MS (MMA865x_DR2_MASK)
393 #define MMA865x_DATA_RATE_80MS (MMA865x_DR2_MASK+MMA865x_DR0_MASK)
394 #define MMA865x_DATA_RATE_160MS (MMA865x_DR2_MASK+MMA865x_DR1_MASK)
395 #define MMA865x_DATA_RATE_640MS (MMA865x_DR2_MASK+MMA865x_DR1_MASK+MMA865x_DR0_MASK)
397 #define MMA865x_DATA_RATE_800HZ (MMA865x_DATA_RATE_1250US)
398 #define MMA865x_DATA_RATE_400HZ (MMA865x_DATA_RATE_2500US)
399 #define MMA865x_DATA_RATE_200HZ (MMA865x_DATA_RATE_5MS)
400 #define MMA865x_DATA_RATE_100HZ (MMA865x_DATA_RATE_10MS)
401 #define MMA865x_DATA_RATE_50HZ (MMA865x_DATA_RATE_20MS)
402 #define MMA865x_DATA_RATE_12_5HZ (MMA865x_DATA_RATE_80MS)
403 #define MMA865x_DATA_RATE_6_25HZ (MMA865x_DATA_RATE_160MS)
404 #define MMA865x_DATA_RATE_1_56HZ (MMA865x_DATA_RATE_640MS)
406 #define MMA865x_ACTIVE (MMA865x_ACTIVE_MASK)
407 #define MMA865x_STANDBY 0x00
412 #define MMA865x_ST_MASK 0x80
413 #define MMA865x_ST_SHIFT 7
414 #define MMA865x_RST_MASK 0x40
415 #define MMA865x_RST_SHIFT 6
416 #define MMA865x_SMODS1_MASK 0x10
417 #define MMA865x_SMODS0_MASK 0x08
418 #define MMA865x_SLPE_MASK 0x04
419 #define MMA865x_SLPE_SHIFT 2
420 #define MMA865x_MODS1_MASK 0x02
421 #define MMA865x_MODS0_MASK 0x01
422 #define MMA865x_SMODS_MASK 0x18
423 #define MMA865x_SMODS_SHIFT 3
424 #define MMA865x_MODS_MASK 0x03
425 #define MMA865x_MODS_SHIFT 0
427 #define MMA865x_SMOD_NORMAL 0x00
428 #define MMA865x_SMOD_LOW_NOISE (MMA865x_SMODS0_MASK)
429 #define MMA865x_SMOD_HIGH_RES (MMA865x_SMODS1_MASK)
430 #define MMA865x_SMOD_LOW_POWER (MMA865x_SMODS1_MASK+MMA865x_SMODS0_MASK)
432 #define MMA865x_MOD_NORMAL 0x00
433 #define MMA865x_MOD_LOW_NOISE (MMA865x_MODS0_MASK)
434 #define MMA865x_MOD_HIGH_RES (MMA865x_MODS1_MASK)
435 #define MMA865x_MOD_LOW_POWER (MMA865x_MODS1_MASK+MMA865x_MODS0_MASK)
440 #define MMA865x_FIFO_GATE_MASK 0x80 // MMA865x only
441 #define MMA865x_FIFO_GATE_SHIFT 7
442 #define MMA865x_WAKE_TRANS_MASK 0x40 // MMA865x only
443 #define MMA865x_WAKE_TRANS_SHIFT 6
444 #define MMA865x_WAKE_LNDPRT_MASK 0x20
445 #define MMA865x_WAKE_LNDPRT_SHIFT 5
446 #define MMA865x_WAKE_PULSE_MASK 0x10 // MMA865x only
447 #define MMA865x_WAKE_PULSE_SHIFT 4
448 #define MMA865x_WAKE_FF_MT_MASK 0x08
449 #define MMA865x_WAKE_FF_MT_SHIFT 3
450 #define MMA865x_IPOL_MASK 0x02
451 #define MMA865x_IPOL_SHIFT 1
452 #define MMA865x_PP_OD_MASK 0x01
453 #define MMA865x_PP_OD_SHIFT 0
457 #define MMA865x_INT_EN_ASLP_MASK 0x80
458 #define MMA865x_INT_EN_ASLP_SHIFT 7
459 #define MMA865x_INT_EN_FIFO_MASK 0x40 // MMA865x only
460 #define MMA865x_INT_EN_FIFO_SHIFT 6
461 #define MMA865x_INT_EN_TRANS_MASK 0x20 // MMA865x only
462 #define MMA865x_INT_EN_TRANS_SHIFT 5
463 #define MMA865x_INT_EN_LNDPRT_MASK 0x10
464 #define MMA865x_INT_EN_LNDPRT_SHIFT 4
465 #define MMA865x_INT_EN_PULSE_MASK 0x08 // MMA865x only
466 #define MMA865x_INT_EN_PULSE_SHIFT 3
467 #define MMA865x_INT_EN_FF_MT_MASK 0x04
468 #define MMA865x_INT_EN_FF_MT_SHIFT 2
469 #define MMA865x_INT_EN_DRDY_MASK 0x01
470 #define MMA865x_INT_EN_DRDY_SHIFT 0
475 #define MMA865x_INT_CFG_ASLP_MASK 0x80
476 #define MMA865x_INT_CFG_ASLP_SHIFT 7
477 #define MMA865x_INT_CFG_FIFO_MASK 0x40 // MMA865x only
478 #define MMA865x_INT_CFG_FIFO_SHIFT 6
479 #define MMA865x_INT_CFG_TRANS_MASK 0x20 // MMA865x only
480 #define MMA865x_INT_CFG_TRANS_SHIFT 5
481 #define MMA865x_INT_CFG_LNDPRT_MASK 0x10
482 #define MMA865x_INT_CFG_LNDPRT_SHIFT 4
483 #define MMA865x_INT_CFG_PULSE_MASK 0x08 // MMA865x only
484 #define MMA865x_INT_CFG_PULSE_SHIFT 3
485 #define MMA865x_INT_CFG_FF_MT_MASK 0x04
486 #define MMA865x_INT_CFG_FF_MT_SHIFT 2
487 #define MMA865x_INT_CFG_DRDY_MASK 0x01
488 #define MMA865x_INT_CFG_DRDY_SHIFT 0
491 #define MMA865x_PL_OUTPUT_EN 0x01
492 #define MMA865x_FFMT_OUTPUT_EN 0x02
493 #define MMA865x_TRANS_OUTPUT_EN 0x04
494 #define MMA865x_PULSE_OUTPUT_EN 0x08
unsigned char uint8
This defines uint8 as unsigned char.
uint8 accelFullScaleRange
unsigned long uint32
This defines uint32 as unsigned long.