#ifndef _APPCFG_H_
#define _APPCFG_H_

// configurations goes from here
// MAKE SURE YOUR PIN CONFIGURATIONS FITS TO YOUR BOARD CONNECTION!
// otherwise not only no image, but also can damage camera!

// define this macro to non-zero after you have configured
#define IS_CFG_DONE 	1

// 0 = color, non-0 = grayscale
#define IS_GRAYSCALE	0


// the following 5 configurations have different combinations, you can test with different values
// and there are up to 384 different combinations that works, with different phenomenon
// default is:
//	IS_M0_HANDLE_SGPIO = 1, IS_USE_ANTI_TEAR = 1, IS_TWIN_RXBUF = 1, FRABUF_Q_CAPACITY = 2, TEST_MODE = TEST_NONE
//	usually, you should always set IS_USE_ANTI_TEAR to 1 (of course!), IS_TWIN_RXBUF = 1, FRABUF_Q_CAPACITY >= 2


// whether use M0 to handle SGPIO, M0 can offload M4 and make FPS higher
// seems always need to use M0 if running from SPIFI
//#define IS_M0_HANDLE_SGPIO	1

// set to non-zero if you want anti-tearing enabled, should always be the case unless you want to reproduce the tearing effect
//#define IS_USE_ANTI_TEAR	1

// use twin receving buffers or not
// this has NOTHING to do with tearing effect
// but twin receiving buffer can make FPS higher by eliminating "1 frame latency",
// this is achieved by allowing camera to "pre-fetch" new image
#define IS_TWIN_RXBUF		1	// 0 = single receiving buffer, !0 = twin receiving buffer

// define capacity of LCD framebuffer queue, 
//	>3 is in most cases, just killing memory (if you envy them that they are always free from work:) ) ;
//		or if you work on a unstable network, to cache recent images
//		but it will introduce latency if framebuffer consume speed is lower than produce speed, ---- test with "TEST_OVERRUN"
//		in this case, larger number introduce more latency, but less possibility of framebuffer getting starved.
//		note : latency is only introduced if framebuffer production is the bottleneck!
//	3 is the equivalent of triple buffering, required on plain LCD ctrlr., but don't required on LPC's LCD ctrlr.
//	2 is the equivalent of double buffering, recommendded on LPC
//	1 is similar to 2, but will slightly lower FPS, because it disables parallisim of LCD refreshing and framebuffer preparing
//  Hint: 2 is almost always enough, 3 is really always enough
#define FRABUF_Q_CAPACITY	2 // 2


// 模拟不同情况下，因刷新过慢导致接收缓冲与显示缓冲全部被冲满的情况，或因接收过慢导致接收缓冲与显示缓冲全部被用光的情况
// #define TEST_MODE	TEST_UNDERRUN
// #define TEST_MODE	TEST_OVERRUN
// #define TEST_MODE	TEST_NONE

// >>> following configuration must match your board and camera, unlike the above 5 configurations that you can set to anything as you wish!

#define CAMERA_SEL	CAMERA_OV7670


#define LCD_PANEL_MCB4300	1
#define LCD_PANEL	LCD_PANEL_MCB4300

/*! @brief width (in pixel) of preview rectangle on LCD
*
* Must <= CAM_CAP_W and <= CAM_LCD_W */
#define CAM_PREVIEW_W	320
/*! @brief height (in line) of preview rectangle on LCD
*
* Must <= CAM_CAP_H and <= CAM_LCD_W */
#define CAM_PREVIEW_H	240
//! width of video capture, limited by camera resolution
#define CAM_CAP_W		320
//! height of video capture, limited by camera resolution
#define CAM_CAP_H		240


#define MICROSEC_PER_TICK	250		// better do NOT change this setting!


// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

// Pin configurations goes from here



// following are pin and function configurations, the naming convention is:
// 
// (mandatory)  SPT_XXX : XXX in SCU Port number 	(0x0 - 0xF for general pins, 0x10 - 0x1A for special pins)
// (mandatory)  SPN_XXX : XXX in SCU pin number 		(0 - 31)
// (mandatory)  ALT_XXX : XXX in SCU's alternate function number (0-7). If used as GPIO, define it to GLT_XXX (see following)
// (optional, only applicable if a pin is used as GPIO)   GPT_XXX : XXX in GPIO port number
// (optional, only applicable if a pin is used as GPIO)   GPN_XXX : XXX in GPIO pin number
// (optional, only applicable if a pin is used as GPIO)   GLT_XXX : XXX in SCU's alternate function number, WHEN USED AS GPIO
// (optional, only applicable if a pin is used as SGPIO)  SLC_XXX : XXX in SGPIO slice number (0-15, but not recommendded to use numbers directly)
// (optional, only applicable if a pin is used as SGPIO)  SGP_XXX : XXX in SGPIO pin number (0-15)
// (optional, only applicable if a pin is used to trigger GPIO pin interrupt)  PIQ_XXX : XXX in pin interrupt IRQ number (0-7)
//		warning: Unless others, PIQ_XXX can't assure correct initialization of pin interrupt, since each pin IRQ
//		requires 8 bits to designate selection and there are 2 registers in SCU on it: (PIntSel0&1)


#define SPT_SGPD0		9
#define SPN_SGPD0		0
#define ALT_SGPD0		6
#define SLC_SGPD0		pin0Slice
	
#define SPT_SGPD1		9
#define SPN_SGPD1		1
#define ALT_SGPD1		6
#define SLC_SGPD1		pin1Slice
	
#define SPT_SGPD2		9
#define SPN_SGPD2		2
#define ALT_SGPD2		6
#define SLC_SGPD2		pin2Slice
	
#define SPT_SGPD3		9
#define SPN_SGPD3		5
#define ALT_SGPD3		6
#define SLC_SGPD3		pin3Slice
	
#define SPT_SGPD4		6
#define SPN_SGPD4		3
#define ALT_SGPD4		2
#define SLC_SGPD4		pin4Slice
	
#define SPT_SGPD5		0x6
#define SPN_SGPD5		6
#define ALT_SGPD5		2
#define SLC_SGPD5		pin5Slice
	
#define SPT_SGPD6		0xF
#define SPN_SGPD6		7
#define ALT_SGPD6		6
#define SLC_SGPD6		pin6Slice
	
#define SPT_SGPD7		0xF
#define SPN_SGPD7		8
#define ALT_SGPD7		6
#define SLC_SGPD7		pin7Slice
	
	// PCLK is both connected to SCT.IN and SGPIO pin as external shift clock
#define SPT_SGPPXCLK	0x9
#define SPN_SGPPXCLK	0x6
#define ALT_SGPPXCLK	6
#define SLC_SGPPXCLK	pin8Slice
#define SGP_SGPPXCLK	8
	
	// HSYNC is both connected to SCT.IN and SGPIO pin as clock qualifier.
#define SPT_SGPHSYNC	0x8
#define SPN_SGPHSYNC	0x1
#define ALT_SGPHSYNC	4
#define SLC_SGPHSYNC	pin9Slice
#define SGP_SGPHSYNC	9

	
#define SPT_VSYNC		1
#define SPN_VSYNC		20
#define GPT_VSYNC		0
#define GPN_VSYNC		15
#define GLT_VSYNC		0
#define ALT_VSYNC		GLT_VSYNC
#define PIQ_VSYNC		6		// Pin IRQ of VSync is slot 6
	
//! MCLK hasn't GPIO relationship
#define SPT_MCLK		0xA
#define SPN_MCLK		0
#define ALT_MCLK		6

// required for some cameras (E.g., YACBA21), not often required
#define SPT_LDO_EN		0x1
#define SPN_LDO_EN		17
#define GPT_LDO_EN		0        // ???
#define GPN_LDO_EN		12        // ???    
#define GLT_LDO_EN		0
#define ALT_LDO_EN		GLT_LDO_EN
	
#define SPT_CHIP_ENB	0xC
#define SPN_CHIP_ENB	10
#define GPT_CHIP_ENB	6
#define GPN_CHIP_ENB	9
#define GLT_CHIP_ENB	4
#define ALT_CHIP_ENB	GLT_CHIP_ENB
	



#endif

