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LPCOpen Platform for the NXP LPC112X family of Microcontrollers
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chip_112x
pmu_112x.h
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/*
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* @brief LPC11xx PMU chip driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PMU_1125_H_
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#define __PMU_1125_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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__IO uint32_t
PCON
;
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__IO uint32_t GPREG[5];
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}
LPC_PMU_T
;
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typedef
enum
CHIP_PMU_MCUPOWER {
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PMU_MCU_SLEEP
= 0,
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PMU_MCU_DEEP_SLEEP
,
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PMU_MCU_DEEP_PWRDOWN
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}
CHIP_PMU_MCUPOWER_T
;
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#define PMU_PCON_PM_SLEEP (0x0)
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#define PMU_PCON_PM_DEEPSLEEP (0x0)
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#define PMU_PCON_PM_DEEPPOWERDOWN (0x2)
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#define PMU_PCON_DPDEN (0x02)
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#define PMU_PCON_SLEEPFLAG (1 << 8)
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#define PMU_PCON_DPDFLAG (1 << 11)
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#define PMU_GPREG4_DATA ((uint32_t) 0x1fffff << 11)
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#define PMU_GPREG4_WAKEHYSENABLE (1 << 10)
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STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
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{
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pPMU->GPREG[regIndex] = value;
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}
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STATIC
INLINE
void
Chip_PMU_WriteGPREG4
(
LPC_PMU_T
*pPMU, uint32_t value)
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{
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uint32_t reg;
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reg = pPMU->
GPREG
[4] & ~
PMU_GPREG4_DATA
;
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pPMU->
GPREG
[4] = reg | (value << 11);
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}
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STATIC
INLINE
uint32_t
Chip_PMU_ReadGPREG
(
LPC_PMU_T
*pPMU, uint8_t regIndex)
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{
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return
pPMU->
GPREG
[regIndex];
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}
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void
Chip_PMU_SleepState
(
LPC_PMU_T
*pPMU);
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void
Chip_PMU_DeepSleepState
(
LPC_PMU_T
*pPMU);
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void
Chip_PMU_DeepPowerDownState
(
LPC_PMU_T
*pPMU);
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void
Chip_PMU_Sleep
(
LPC_PMU_T
*pPMU,
CHIP_PMU_MCUPOWER_T
SleepMode);
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STATIC
INLINE
uint32_t
Chip_PMU_GetSleepFlags
(
LPC_PMU_T
*pPMU)
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{
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return
pPMU->
PCON
& (
PMU_PCON_SLEEPFLAG
|
PMU_PCON_DPDFLAG
);
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}
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STATIC
INLINE
void
Chip_PMU_ClearSleepFlags
(
LPC_PMU_T
*pPMU, uint32_t flags)
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{
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pPMU->
PCON
|= flags;
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}
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STATIC
INLINE
uint32_t
Chip_PMU_GetWakeHysEnable
(
LPC_PMU_T
*pPMU)
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{
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return
pPMU->
GPREG
[4] &
PMU_GPREG4_WAKEHYSENABLE
;
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}
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STATIC
INLINE
void
Chip_PMU_SetWakeHysEnable
(
LPC_PMU_T
*pPMU)
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{
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pPMU->
GPREG
[4] |=
PMU_GPREG4_WAKEHYSENABLE
;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __PMU_1125_H_ */
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