LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
timer_112x.h
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1 /*
2  * @brief LPC11xx 16/32-bit Timer/PWM control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __TIMER_1125_H_
33 #define __TIMER_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __IO uint32_t IR;
49  __IO uint32_t TCR;
50  __IO uint32_t TC;
51  __IO uint32_t PR;
52  __IO uint32_t PC;
53  __IO uint32_t MCR;
54  __IO uint32_t MR[4];
55  __IO uint32_t CCR;
56  __IO uint32_t CR[4];
57  __IO uint32_t EMR;
58  __I uint32_t RESERVED0[12];
59  __IO uint32_t CTCR;
60  __IO uint32_t PWMC;
61 } LPC_TIMER_T;
62 
64 #define TIMER_IR_CLR(n) _BIT(n)
65 
67 #define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
68 
69 #define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
70 
72 #define TIMER_ENABLE ((uint32_t) (1 << 0))
73 
74 #define TIMER_RESET ((uint32_t) (1 << 1))
75 
77 #define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
78 
79 #define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
80 
81 #define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
82 
84 #define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
85 
86 #define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
87 
88 #define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
89 
95 void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
96 
102 void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
103 
112 STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
113 {
114  return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
115 }
116 
126 {
127  return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
128 }
129 
137 STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
138 {
139  pTMR->IR = TIMER_IR_CLR(matchnum);
140 }
141 
150 {
151  pTMR->IR = (0x10 << capnum);
152 }
153 
161 {
162  pTMR->TCR |= TIMER_ENABLE;
163 }
164 
172 {
173  pTMR->TCR &= ~TIMER_ENABLE;
174 }
175 
183 {
184  return pTMR->TC;
185 }
186 
194 {
195  return pTMR->PC;
196 }
197 
205 STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
206 {
207  pTMR->PR = prescale;
208 }
209 
218 STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
219 {
220  pTMR->MR[matchnum] = matchval;
221 }
222 
230 STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
231 {
232  return pTMR->CR[capnum];
233 }
234 
240 void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
241 
250 {
251  pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
252 }
253 
261 {
262  pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
263 }
264 
272 {
273  pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
274 }
275 
283 {
284  pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
285 }
286 
295 {
296  pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
297 }
298 
307 {
308  pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
309 }
310 
320 {
321  pTMR->CCR |= TIMER_CAP_RISING(capnum);
322 }
323 
333 {
334  pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
335 }
336 
346 {
347  pTMR->CCR |= TIMER_CAP_FALLING(capnum);
348 }
349 
359 {
360  pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
361 }
362 
372 {
373  pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
374 }
375 
383 {
384  pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
385 }
386 
390 typedef enum IP_TIMER_PIN_MATCH_STATE {
396 
409 void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
410  TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
411 
415 typedef enum IP_TIMER_CAP_SRC_STATE {
421 
432  TIMER_CAP_SRC_STATE_T capSrc,
433  int8_t capnum)
434 {
435  pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
436 }
437 
442 #ifdef __cplusplus
443 }
444 #endif
445 
446 #endif /* __TIMER_1125_H_ */