LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
ssp_112x.h
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1 /*
2  * @brief LPC11xx SSP Registers and control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SSP_1125_H_
33 #define __SSP_1125_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __IO uint32_t CR0;
49  __IO uint32_t CR1;
50  __IO uint32_t DR;
51  __I uint32_t SR;
52  __IO uint32_t CPSR;
53  __IO uint32_t IMSC;
54  __I uint32_t RIS;
55  __I uint32_t MIS;
56  __O uint32_t ICR;
57 } LPC_SSP_T;
58 
64 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
65 
66 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
67 
68 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
69 
70 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
71 
73 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
74 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
75 
77 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
78 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
79 
81 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
82 
83 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
84 
85 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
86 
88 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
89 
95 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
96 
97 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
98 
99 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
100 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
101 
103 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
104 
105 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
106 
108 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
109 
114 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
115 
121 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
122 
124 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
125 
129 typedef enum _SSP_STATUS {
130  SSP_STAT_TFE = ((uint32_t)(1 << 0)),
131  SSP_STAT_TNF = ((uint32_t)(1 << 1)),
132  SSP_STAT_RNE = ((uint32_t)(1 << 2)),
133  SSP_STAT_RFF = ((uint32_t)(1 << 3)),
134  SSP_STAT_BSY = ((uint32_t)(1 << 4)),
135 } SSP_STATUS_T;
136 
140 typedef enum _SSP_INTMASK {
141  SSP_RORIM = ((uint32_t)(1 << 0)),
142  SSP_RTIM = ((uint32_t)(1 << 1)),
143  SSP_RXIM = ((uint32_t)(1 << 2)),
144  SSP_TXIM = ((uint32_t)(1 << 3)),
145  SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
146 } SSP_INTMASK_T;
147 
151 typedef enum _SSP_MASKINTSTATUS {
152  SSP_RORMIS = ((uint32_t)(1 << 0)),
153  SSP_RTMIS = ((uint32_t)(1 << 1)),
154  SSP_RXMIS = ((uint32_t)(1 << 2)),
155  SSP_TXMIS = ((uint32_t)(1 << 3)),
156  SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
158 
162 typedef enum _SSP_RAWINTSTATUS {
163  SSP_RORRIS = ((uint32_t)(1 << 0)),
164  SSP_RTRIS = ((uint32_t)(1 << 1)),
165  SSP_RXRIS = ((uint32_t)(1 << 2)),
166  SSP_TXRIS = ((uint32_t)(1 << 3)),
167  SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
169 
170 typedef enum _SSP_INTCLEAR {
171  SSP_RORIC = 0x0,
172  SSP_RTIC = 0x1,
175 
176 /*
177  * @brief SSP clock format
178  */
179 typedef enum CHIP_SSP_CLOCK_FORMAT {
181  SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
182  SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
183  SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
189 
190 /*
191  * @brief SSP frame format
192  */
193 typedef enum CHIP_SSP_FRAME_FORMAT {
194  SSP_FRAMEFORMAT_SPI = (0 << 4),
198 
199 /*
200  * @brief Number of bits per frame
201  */
202 typedef enum CHIP_SSP_BITS {
203  SSP_BITS_4 = (3u << 0),
204  SSP_BITS_5 = (4u << 0),
205  SSP_BITS_6 = (5u << 0),
206  SSP_BITS_7 = (6u << 0),
207  SSP_BITS_8 = (7u << 0),
208  SSP_BITS_9 = (8u << 0),
209  SSP_BITS_10 = (9u << 0),
210  SSP_BITS_11 = (10u << 0),
211  SSP_BITS_12 = (11u << 0),
212  SSP_BITS_13 = (12u << 0),
213  SSP_BITS_14 = (13u << 0),
214  SSP_BITS_15 = (14u << 0),
215  SSP_BITS_16 = (15u << 0),
217 
218 /*
219  * @brief SSP config format
220  */
221 typedef struct SSP_ConfigFormat {
226 
233 {
234  pSSP->CR1 |= SSP_CR1_SSP_EN;
235 }
236 
243 {
244  pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
245 }
246 
255 {
256  pSSP->CR1 |= SSP_CR1_LBM_EN;
257 }
258 
267 {
268  pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
269 }
270 
283 {
284  return (pSSP->SR & Stat) ? SET : RESET;
285 }
286 
294 {
295  return pSSP->MIS;
296 }
297 
310 {
311  return (pSSP->RIS & RawInt) ? SET : RESET;
312 }
313 
321 {
322  return SSP_CR0_DSS(pSSP->CR0);
323 }
324 
335 {
336  pSSP->ICR = IntClear;
337 }
338 
345 {
346  pSSP->IMSC |= SSP_TXIM;
347 }
348 
355 {
356  pSSP->IMSC &= (~SSP_TXIM);
357 }
358 
365 {
366  return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
367 }
368 
375 STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
376 {
377  pSSP->DR = SSP_DR_BITMASK(tx_data);
378 }
379 
388 void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
389 
406 STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
407 {
408  pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
409 }
410 
419 STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
420 {
421  pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
422 }
423 
424 /*
425  * @brief SSP mode
426  */
427 typedef enum CHIP_SSP_MODE {
428  SSP_MODE_MASTER = (0 << 2),
429  SSP_MODE_SLAVE = (1u << 2),
431 
432 /*
433  * @brief SPI address
434  */
435 typedef struct {
436  uint8_t port;
437  uint8_t pin;
438 } SPI_Address_t;
439 
440 /*
441  * @brief SSP data setup structure
442  */
443 typedef struct {
444  void *tx_data;
445  uint32_t tx_cnt;
446  void *rx_data;
447  uint32_t rx_cnt;
448  uint32_t length;
450 
453 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
454 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
455 
457 /* There's no bug here!!!
458  * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
459  * That means the active clock is in HI state.
460  * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
461  * high between frames. That means the active clock is in LO state.
462  */
463 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
464 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
465 
467 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
468 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN
469 
476 
485 
494 
507 
518 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
519 
530 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
531 
537 void Chip_SSP_Init(LPC_SSP_T *pSSP);
538 
545 void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
546 
553 void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
554 
561 void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
562 
567 #ifdef __cplusplus
568 }
569 #endif
570 
571 #endif /* __SSP_1125_H_ */