LPCOpen Platform for LPC112X microcontrollers
112X
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iocon_112x.h
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/*
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* @brief IOCON registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __IOCON_1125_H_
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#define __IOCON_1125_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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uint32_t pin:8;
/* Pin number */
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uint32_t modefunc:24;
/* Function and mode */
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}
PINMUX_GRP_T
;
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typedef
enum
CHIP_IOCON_PIO {
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IOCON_PIO0_0
= (0x00C >> 2),
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IOCON_PIO0_1
= (0x010 >> 2),
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IOCON_PIO0_2
= (0x01C >> 2),
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IOCON_PIO0_3
= (0x02C >> 2),
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IOCON_PIO0_4
= (0x030 >> 2),
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IOCON_PIO0_5
= (0x034 >> 2),
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IOCON_PIO0_6
= (0x04C >> 2),
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IOCON_PIO0_7
= (0x050 >> 2),
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IOCON_PIO0_8
= (0x060 >> 2),
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IOCON_PIO0_9
= (0x064 >> 2),
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IOCON_PIO0_10
= (0x068 >> 2),
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IOCON_PIO0_11
= (0x074 >> 2),
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IOCON_PIO1_0
= (0x078 >> 2),
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IOCON_PIO1_1
= (0x07C >> 2),
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IOCON_PIO1_2
= (0x080 >> 2),
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IOCON_PIO1_3
= (0x090 >> 2),
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IOCON_PIO1_4
= (0x094 >> 2),
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IOCON_PIO1_5
= (0x0A0 >> 2),
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IOCON_PIO1_6
= (0x0A4 >> 2),
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IOCON_PIO1_7
= (0x0A8 >> 2),
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IOCON_PIO1_8
= (0x014 >> 2),
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IOCON_PIO1_9
= (0x038 >> 2),
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IOCON_PIO1_10
= (0x06C >> 2),
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IOCON_PIO1_11
= (0x098 >> 2),
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IOCON_PIO2_0
= (0x008 >> 2),
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IOCON_PIO2_1
= (0x028 >> 2),
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IOCON_PIO2_2
= (0x05C >> 2),
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IOCON_PIO2_3
= (0x08C >> 2),
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IOCON_PIO2_4
= (0x040 >> 2),
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IOCON_PIO2_5
= (0x044 >> 2),
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IOCON_PIO2_6
= (0x000 >> 2),
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IOCON_PIO2_7
= (0x020 >> 2),
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IOCON_PIO2_8
= (0x024 >> 2),
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IOCON_PIO2_9
= (0x054 >> 2),
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IOCON_PIO2_10
= (0x058 >> 2),
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IOCON_PIO3_0
= (0x084 >> 2),
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IOCON_PIO3_2
= (0x09C >> 2),
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IOCON_PIO3_3
= (0x0AC >> 2),
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IOCON_PIO3_4
= (0x03C >> 2),
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IOCON_PIO3_5
= (0x048 >> 2),
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}
CHIP_IOCON_PIO_T
;
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typedef
enum
CHIP_IOCON_PIN_LOC {
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IOCON_SCKLOC_PIO0_10
= (0xB0),
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IOCON_SCKLOC_PIO0_6
= (0xB0 | 2),
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IOCON_DSRLOC_PIO2_1
= (0xB4),
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IOCON_DCDLOC_PIO2_2
= (0xB8),
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IOCON_DCDLOC_PIO3_2
= (0xB8 | 1),
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IOCON_RILOC_PIO2_3
= (0xBC),
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IOCON_RILOC_PIO3_3
= (0xBC | 1),
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IOCON_SSEL1_LOC_PIO2_2
= (0x18),
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IOCON_SSEL1_LOC_PIO2_4
= (0x18 | 1),
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IOCON_CT16B0_CAP0_LOC_PIO0_2
= (0xC0),
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IOCON_CT16B0_CAP0_LOC_PIO3_3
= (0xC0 | 1),
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IOCON_SCK1_LOC_PIO2_1
= (0xC4),
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IOCON_SCK1_LOC_PIO3_2
= (0xC4 | 1),
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IOCON_MISO1_LOC_PIO2_2
= (0xC8),
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IOCON_MISO1_LOC_PIO1_10
= (0xC8 | 1),
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IOCON_MOSI1_LOC_PIO2_3
= (0xCC),
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IOCON_MOSI1_LOC_PIO1_9
= (0xCC),
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IOCON_CT326B0_CAP0_LOC_PIO1_5
= (0xD0),
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IOCON_CT326B0_CAP0_LOC_PIO2_9
= (0xD0 | 1),
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IOCON_U0_RXD_LOC_PIO1_6
= (0xD4),
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IOCON_U0_RXD_LOC_PIO2_7
= (0xD4 | 1),
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IOCON_U0_RXD_LOC_PIO3_4
= (0xD4 | 3),
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}
CHIP_IOCON_PIN_LOC_T
;
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typedef
struct
{
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__IO uint32_t REG[48];
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}
LPC_IOCON_T
;
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#define IOCON_FUNC0 0x0
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#define IOCON_FUNC1 0x1
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#define IOCON_FUNC2 0x2
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#define IOCON_FUNC3 0x3
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#define IOCON_FUNC4 0x4
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#define IOCON_FUNC5 0x5
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#define IOCON_FUNC6 0x6
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#define IOCON_FUNC7 0x7
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#define IOCON_MODE_INACT (0x0 << 3)
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#define IOCON_MODE_PULLDOWN (0x1 << 3)
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#define IOCON_MODE_PULLUP (0x2 << 3)
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#define IOCON_MODE_REPEATER (0x3 << 3)
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#define IOCON_HYS_EN (0x1 << 5)
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#define IOCON_INV_EN (0x1 << 6)
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#define IOCON_ADMODE_EN (0x0 << 7)
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#define IOCON_DIGMODE_EN (0x1 << 7)
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#define IOCON_SFI2C_EN (0x0 << 8)
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#define IOCON_STDI2C_EN (0x1 << 8)
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#define IOCON_FASTI2C_EN (0x2 << 8)
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#define IOCON_FILT_DIS (0x1 << 8)
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#define IOCON_OPENDRAIN_EN (0x1 << 10)
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#define MD_PLN (0x0 << 3)
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#define MD_PDN (0x1 << 3)
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#define MD_PUP (0x2 << 3)
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#define MD_BUK (0x3 << 3)
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#define MD_HYS (0x1 << 5)
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#define MD_INV (0x1 << 6)
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#define MD_ADMODE (0x0 << 7)
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#define MD_DIGMODE (0x1 << 7)
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#define MD_DISFIL (0x0 << 8)
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#define MD_ENFIL (0x1 << 8)
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#define MD_SFI2C (0x0 << 8)
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#define MD_STDI2C (0x1 << 8)
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#define MD_FASTI2C (0x2 << 8)
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#define MD_OPENDRAIN (0x1 << 10)
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#define FUNC0 0x0
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#define FUNC1 0x1
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#define FUNC2 0x2
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#define FUNC3 0x3
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#define FUNC4 0x4
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#define FUNC5 0x5
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#define FUNC6 0x6
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#define FUNC7 0x7
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STATIC
INLINE
void
Chip_IOCON_PinMuxSet
(
LPC_IOCON_T
*pIOCON,
CHIP_IOCON_PIO_T
pin, uint32_t modefunc)
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{
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pIOCON->
REG
[pin] = modefunc;
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}
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STATIC
INLINE
void
Chip_IOCON_PinMux
(
LPC_IOCON_T
*pIOCON,
CHIP_IOCON_PIO_T
pin, uint16_t mode, uint8_t func)
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{
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Chip_IOCON_PinMuxSet
(pIOCON, pin, (uint32_t) (mode | func));
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}
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STATIC
INLINE
void
Chip_IOCON_PinLocSel
(
LPC_IOCON_T
*pIOCON,
CHIP_IOCON_PIN_LOC_T
sel)
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{
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pIOCON->
REG
[sel >> 2] = sel & 0x03;
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}
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void
Chip_IOCON_SetPinMuxing
(
LPC_IOCON_T
*pIOCON,
const
PINMUX_GRP_T
* pinArray, uint32_t arrayLength);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __IOCON_1125_H_ */
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