LPCOpen Platform for LPC112X microcontrollers
112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
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chip_112x
i2c_common_112x.h
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/*
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* @brief LPC11xx I2C driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __I2C_COMMON_1125_H_
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#define __I2C_COMMON_1125_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
/* I2C0 Structure */
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__IO uint32_t
CONSET
;
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__I uint32_t
STAT
;
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__IO uint32_t
DAT
;
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__IO uint32_t
ADR0
;
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__IO uint32_t
SCLH
;
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__IO uint32_t
SCLL
;
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__O uint32_t
CONCLR
;
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__IO uint32_t
MMCTRL
;
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__IO uint32_t
ADR1
;
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__IO uint32_t
ADR2
;
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__IO uint32_t
ADR3
;
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__I uint32_t
DATA_BUFFER
;
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__IO uint32_t MASK[4];
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}
LPC_I2C_T
;
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/*
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* @brief I2C Control Set register description
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*/
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#define I2C_I2CONSET_AA ((0x04))
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#define I2C_I2CONSET_SI ((0x08))
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#define I2C_I2CONSET_STO ((0x10))
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#define I2C_I2CONSET_STA ((0x20))
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#define I2C_I2CONSET_I2EN ((0x40))
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/*
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* @brief I2C Control Clear register description
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*/
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#define I2C_I2CONCLR_AAC ((1 << 2))
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#define I2C_I2CONCLR_SIC ((1 << 3))
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#define I2C_I2CONCLR_STOC ((1 << 4))
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#define I2C_I2CONCLR_STAC ((1 << 5))
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#define I2C_I2CONCLR_I2ENC ((1 << 6))
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/*
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* @brief I2C Common Control register description
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*/
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#define I2C_CON_AA (1UL << 2)
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#define I2C_CON_SI (1UL << 3)
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#define I2C_CON_STO (1UL << 4)
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#define I2C_CON_STA (1UL << 5)
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#define I2C_CON_I2EN (1UL << 6)
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/*
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* @brief I2C Status Code definition (I2C Status register)
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*/
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#define I2C_STAT_CODE_BITMASK ((0xF8))
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#define I2C_STAT_CODE_ERROR ((0xFF))
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/*
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* @brief I2C Master transmit mode
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*/
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#define I2C_I2STAT_M_TX_START ((0x08))
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#define I2C_I2STAT_M_TX_RESTART ((0x10))
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#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
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#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
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#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
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#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
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#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
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/*
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* @brief I2C Master receive mode
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*/
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#define I2C_I2STAT_M_RX_START ((0x08))
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#define I2C_I2STAT_M_RX_RESTART ((0x10))
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#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
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#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
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#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
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#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
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#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
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/*
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* @brief I2C Slave receive mode
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*/
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#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
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#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
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// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
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#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
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#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
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// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
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#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
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#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
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#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
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#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
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#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
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/*
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* @brief I2C Slave transmit mode
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*/
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#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
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#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
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// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
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#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
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#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
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#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
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#define I2C_SLAVE_TIME_OUT 0x10000000UL
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/*
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* @brief I2C Data register definition
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*/
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#define I2C_I2DAT_BITMASK ((0xFF))
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#define I2C_I2DAT_IDLE_CHAR (0xFF)
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/*
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* @brief I2C Monitor mode control register description
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*/
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#define I2C_I2MMCTRL_MM_ENA ((1 << 0))
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#define I2C_I2MMCTRL_ENA_SCL ((1 << 1))
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#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2))
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#define I2C_I2MMCTRL_BITMASK ((0x07))
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/*
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* @brief I2C Data buffer register description
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*/
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#define I2DATA_BUFFER_BITMASK ((0xFF))
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/*
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* @brief I2C Slave Address registers definition
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*/
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#define I2C_I2ADR_GC ((1 << 0))
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#define I2C_I2ADR_BITMASK ((0xFF))
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/*
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* @brief I2C Mask Register definition
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*/
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#define I2C_I2MASK_MASK(n) ((n & 0xFE))
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/*
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* @brief I2C SCL HIGH duty cycle Register definition
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*/
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#define I2C_I2SCLH_BITMASK ((0xFFFF))
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/*
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* @brief I2C SCL LOW duty cycle Register definition
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*/
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#define I2C_I2SCLL_BITMASK ((0xFFFF))
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/*
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* @brief I2C monitor control configuration defines
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*/
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#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL
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#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __I2C_COMMON_1125_H_ */
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