LPCOpen Platform for LPC112X microcontrollers
112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
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chip_112x
clock_112x.h
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1
/*
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* @brief LPC11XX Clock control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_1125_H_
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#define __CLOCK_1125_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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45
#define SYSCON_IRC_FREQ (12000000)
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STATIC
INLINE
void
Chip_Clock_SetupSystemPLL
(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCON
->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
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}
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63
STATIC
INLINE
bool
Chip_Clock_IsSystemPLLLocked
(
void
)
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{
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return
(
bool
) ((
LPC_SYSCON
->SYSPLLSTAT & 1) != 0);
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}
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typedef
enum
CHIP_SYSCON_PLLCLKSRC {
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SYSCON_PLLCLKSRC_IRC
= 0,
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SYSCON_PLLCLKSRC_MAINOSC
,
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SYSCON_PLLCLKSRC_RESERVED1
,
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SYSCON_PLLCLKSRC_RESERVED2
,
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}
CHIP_SYSCON_PLLCLKSRC_T
;
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void
Chip_Clock_SetSystemPLLSource
(
CHIP_SYSCON_PLLCLKSRC_T
src);
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void
Chip_Clock_SetPLLBypass
(
bool
bypass,
bool
highfr);
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typedef
enum
CHIP_WDTLFO_OSC {
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WDTLFO_OSC_ILLEGAL
,
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WDTLFO_OSC_0_60
,
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WDTLFO_OSC_1_05
,
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WDTLFO_OSC_1_40
,
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WDTLFO_OSC_1_75
,
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WDTLFO_OSC_2_10
,
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WDTLFO_OSC_2_40
,
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WDTLFO_OSC_2_70
,
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WDTLFO_OSC_3_00
,
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WDTLFO_OSC_3_25
,
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WDTLFO_OSC_3_50
,
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WDTLFO_OSC_3_75
,
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WDTLFO_OSC_4_00
,
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WDTLFO_OSC_4_20
,
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WDTLFO_OSC_4_40
,
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WDTLFO_OSC_4_60
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}
CHIP_WDTLFO_OSC_T
;
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STATIC
INLINE
void
Chip_Clock_SetWDTOSC
(
CHIP_WDTLFO_OSC_T
wdtclk, uint8_t div)
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{
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LPC_SYSCON
->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
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}
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typedef
enum
CHIP_SYSCON_MAINCLKSRC {
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SYSCON_MAINCLKSRC_IRC
= 0,
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SYSCON_MAINCLKSRC_PLLIN
,
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SYSCON_MAINCLKSRC_LFOSC
,
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SYSCON_MAINCLKSRC_WDTOSC
=
SYSCON_MAINCLKSRC_LFOSC
,
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SYSCON_MAINCLKSRC_PLLOUT
,
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}
CHIP_SYSCON_MAINCLKSRC_T
;
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void
Chip_Clock_SetMainClockSource
(
CHIP_SYSCON_MAINCLKSRC_T
src);
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STATIC
INLINE
CHIP_SYSCON_MAINCLKSRC_T
Chip_Clock_GetMainClockSource
(
void
)
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{
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return
(
CHIP_SYSCON_MAINCLKSRC_T
) (
LPC_SYSCON
->MAINCLKSEL);
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}
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STATIC
INLINE
void
Chip_Clock_SetSysClockDiv
(uint32_t div)
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{
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LPC_SYSCON
->SYSAHBCLKDIV = div;
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}
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typedef
enum
CHIP_SYSCON_CLOCK {
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SYSCON_CLOCK_SYS
= 0,
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SYSCON_CLOCK_ROM
,
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SYSCON_CLOCK_RAM
,
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SYSCON_CLOCK_FLASHREG
,
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SYSCON_CLOCK_FLASHARRAY
,
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SYSCON_CLOCK_I2C
,
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SYSCON_CLOCK_GPIO
,
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SYSCON_CLOCK_CT16B0
,
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SYSCON_CLOCK_CT16B1
,
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SYSCON_CLOCK_CT32B0
,
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SYSCON_CLOCK_CT32B1
,
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SYSCON_CLOCK_SSP0
,
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SYSCON_CLOCK_UART0
,
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SYSCON_CLOCK_ADC
,
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SYSCON_CLOCK_RESERVED14
,
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SYSCON_CLOCK_WDT
,
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SYSCON_CLOCK_IOCON
,
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SYSCON_CLOCK_RESERVED17
,
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SYSCON_CLOCK_SSP1
,
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}
CHIP_SYSCON_CLOCK_T
;
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STATIC
INLINE
void
Chip_Clock_EnablePeriphClock
(
CHIP_SYSCON_CLOCK_T
clk)
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{
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LPC_SYSCON
->SYSAHBCLKCTRL |= (1 << clk);
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}
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STATIC
INLINE
void
Chip_Clock_DisablePeriphClock
(
CHIP_SYSCON_CLOCK_T
clk)
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{
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LPC_SYSCON
->SYSAHBCLKCTRL &= ~(1 << clk);
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}
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STATIC
INLINE
void
Chip_Clock_SetSSP0ClockDiv
(uint32_t div)
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{
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LPC_SYSCON
->SSP0CLKDIV = div;
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}
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STATIC
INLINE
uint32_t
Chip_Clock_GetSSP0ClockDiv
(
void
)
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{
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return
LPC_SYSCON
->SSP0CLKDIV;
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}
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STATIC
INLINE
void
Chip_Clock_SetUARTClockDiv
(uint32_t div)
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{
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LPC_SYSCON
->UART0CLKDIV = div;
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}
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STATIC
INLINE
uint32_t
Chip_Clock_GetUARTClockDiv
(
void
)
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{
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return
LPC_SYSCON
->UART0CLKDIV;
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}
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STATIC
INLINE
void
Chip_Clock_SetSSP1ClockDiv
(uint32_t div)
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{
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LPC_SYSCON
->SSP1CLKDIV = div;
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}
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STATIC
INLINE
uint32_t
Chip_Clock_GetSSP1ClockDiv
(
void
)
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{
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return
LPC_SYSCON
->SSP1CLKDIV;
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}
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typedef
enum
CHIP_SYSCON_WDTCLKSRC {
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SYSCON_WDTCLKSRC_IRC
= 0,
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SYSCON_WDTCLKSRC_MAINSYSCLK
,
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SYSCON_WDTCLKSRC_WDTOSC
,
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}
CHIP_SYSCON_WDTCLKSRC_T
;
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void
Chip_Clock_SetWDTClockSource
(
CHIP_SYSCON_WDTCLKSRC_T
src, uint32_t div);
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typedef
enum
CHIP_SYSCON_CLKOUTSRC {
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SYSCON_CLKOUTSRC_IRC
= 0,
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SYSCON_CLKOUTSRC_MAINOSC
,
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SYSCON_CLKOUTSRC_WDTOSC
,
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SYSCON_CLKOUTSRC_LFOSC
=
SYSCON_CLKOUTSRC_WDTOSC
,
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SYSCON_CLKOUTSRC_MAINSYSCLK
,
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}
CHIP_SYSCON_CLKOUTSRC_T
;
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void
Chip_Clock_SetCLKOUTSource
(
CHIP_SYSCON_CLKOUTSRC_T
src, uint32_t div);
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STATIC
INLINE
uint32_t
Chip_Clock_GetMainOscRate
(
void
)
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{
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return
OscRateIn
;
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}
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STATIC
INLINE
uint32_t
Chip_Clock_GetIntOscRate
(
void
)
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{
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return
SYSCON_IRC_FREQ
;
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}
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uint32_t
Chip_Clock_GetWDTOSCRate
(
void
);
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uint32_t
Chip_Clock_GetSystemPLLInClockRate
(
void
);
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uint32_t
Chip_Clock_GetSystemPLLOutClockRate
(
void
);
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uint32_t
Chip_Clock_GetMainClockRate
(
void
);
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uint32_t
Chip_Clock_GetSystemClockRate
(
void
);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __CLOCK_1125_H_ */
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