64 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
66 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
68 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
70 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
73 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
74 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
77 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
78 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
81 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
83 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
85 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
88 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
95 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
97 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
99 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
100 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
103 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
105 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
108 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
114 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
121 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
124 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
129 typedef enum _SSP_STATUS {
140 typedef enum _SSP_INTMASK {
151 typedef enum _SSP_MASKINTSTATUS {
162 typedef enum _SSP_RAWINTSTATUS {
170 typedef enum _SSP_INTCLEAR {
179 typedef enum CHIP_SSP_CLOCK_FORMAT {
193 typedef enum CHIP_SSP_FRAME_FORMAT {
202 typedef enum CHIP_SSP_BITS {
336 pSSP->
ICR = IntClear;
408 pSSP->
CR0 = (pSSP->
CR0 & ~0xFF) | bits | frameFormat | clockMode;
421 pSSP->
CR1 = (pSSP->
CR1 & ~(1 << 2)) | mode;
427 typedef enum CHIP_SSP_MODE {
453 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
454 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
463 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
464 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
467 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
468 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN