LPCOpen Platform for LPC112X microcontrollers  112X
LPCOpen Platform for the NXP LPC112X family of Microcontrollers
Enumerations
CHIP_1125: CHIP_1125 peripheral interrupt numbers

Detailed Description

Enumerations

enum  LPC1125_IRQn_Type {
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,
  SysTick_IRQn = -1, PIO0_0_IRQn = 0, PIO0_1_IRQn = 1, PIO0_2_IRQn = 2,
  PIO0_3_IRQn = 3, PIO0_4_IRQn = 4, PIO0_5_IRQn = 5, PIO0_6_IRQn = 6,
  PIO0_7_IRQn = 7, PIO0_8_IRQn = 8, PIO0_9_IRQn = 9, PIO0_10_IRQn = 10,
  PIO0_11_IRQn = 11, PIO1_0_IRQn = 12, ADC_B_IRQn = 13, SSP1_IRQn = 14,
  I2C_IRQn = 15, I2C0_IRQn = I2C_IRQn, TIMER_16_0_IRQn = 16, TIMER_16_1_IRQn = 17,
  TIMER_32_0_IRQn = 18, TIMER_32_1_IRQn = 19, SSP0_IRQn = 20, UART0_IRQn = 21,
  UART1_IRQn = 22, UART2_IRQn = 23, ADC_A_IRQn = 24, WDT_IRQn = 25,
  BOD_IRQn = 26, Reserved27_IRQn = 27, PIO3_IRQn = 28, PIO2_IRQn = 29,
  PIO1_IRQn = 30, PIO0_IRQn = 31
}
 

Enumeration Type Documentation

Enumerator
NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 Cortex-M0 Hard Fault Interrupt

SVCall_IRQn 

11 Cortex-M0 SV Call Interrupt

PendSV_IRQn 

14 Cortex-M0 Pend SV Interrupt

SysTick_IRQn 

15 Cortex-M0 System Tick Interrupt

PIO0_0_IRQn 

GPIO port 0, pin 0 Interrupt

PIO0_1_IRQn 

GPIO port 0, pin 1 Interrupt

PIO0_2_IRQn 

GPIO port 0, pin 2 Interrupt

PIO0_3_IRQn 

GPIO port 0, pin 3 Interrupt

PIO0_4_IRQn 

GPIO port 0, pin 4 Interrupt

PIO0_5_IRQn 

GPIO port 0, pin 5 Interrupt

PIO0_6_IRQn 

GPIO port 0, pin 6 Interrupt

PIO0_7_IRQn 

GPIO port 0, pin 7 Interrupt

PIO0_8_IRQn 

GPIO port 0, pin 8 Interrupt

PIO0_9_IRQn 

GPIO port 0, pin 9 Interrupt

PIO0_10_IRQn 

GPIO port 0, pin 10 Interrupt

PIO0_11_IRQn 

GPIO port 0, pin 11 Interrupt

PIO1_0_IRQn 

GPIO port 1, pin 0 Interrupt

ADC_B_IRQn 

ADC_B Interrupt

SSP1_IRQn 

SSP1 Interrupt

I2C_IRQn 

I2C Interrupt

I2C0_IRQn 
TIMER_16_0_IRQn 

16-bit Timer0 Interrupt

TIMER_16_1_IRQn 

16-bit Timer1 Interrupt

TIMER_32_0_IRQn 

32-bit Timer0 Interrupt

TIMER_32_1_IRQn 

32-bit Timer1 Interrupt

SSP0_IRQn 

SSP0 Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

ADC_A_IRQn 

ADC_A Converter Interrupt

WDT_IRQn 

Watchdog timer Interrupt

BOD_IRQn 

Brown Out Detect(BOD) Interrupt

Reserved27_IRQn 
PIO3_IRQn 

GPIO interrupt status of port 3

PIO2_IRQn 

GPIO interrupt status of port 2

PIO1_IRQn 

GPIO interrupt status of port 1

PIO0_IRQn 

GPIO interrupt status of port 0

Definition at line 75 of file cmsis.h.