Introduction to MOS Model 11
MOS Model 11 has been developed as the successor of MOS Model 9. The development goals for MOS Model 11 have been:
- suitable for digital, analog and RF;
- suitable for modern and future CMOS technologies;
- physics based;
- number of parameters comparable to MOS Model 9;
- simulation time comparable to MOS Model 9; and
- simple parameter extraction.
Model definition of MOS Model 11
The history of the model can be found here.
MOS Model 11, Level 1101, is an updated version of Level 1100. It uses the same basic equations as Level 1100, but uses different geometry scaling rules. It includes two types of geometrical scaling rules: physical rules and binning rules. Moreover, the temperature scaling has been implemented on the "miniset" level instead of the "maxiset" level as is the case for Level 1100.
MOS Model 11, Level 1102, is an updated version of Level 1101. It uses the same parameter set and parameter scaling relations as Level 1101, but uses slightly different model equations. The surface potential is calculated iteratively using a second-order Newton-Raphson procedure, resulting in a more accurate description of surface potential. Owing to the increased accuracy, some of the basic equations used in Level 1101 can be simplified, and as a result Level 1102 is computationally as fast as Level 1101. In addition, a more physical and simpler velocity saturation expression is used, and as a consequence the saturation voltage expression has changed slightly as well. This all results in a more accurate description of transconductance in saturation. Finally, more accurate physics-based equations have been implemented in Level 1102 for thermal noise, induced gate noise and their correlation.
The description of the source-bulk and drain-bulk junction diode is not included in MOS Model 11. The behaviour of these junction diodes is modelled by the Juncap model. This model has to be added between the source and bulk node and between the drain and bulk node.
Source Code & Library
The source code of MOS Model 11 is available here. The files containing the "Level 1100" code, the "Level 1101" code and the "Level 1102" code are "device_m1100.c", "device_m1101.c" and "device_m1102.c" respectively. If you use the included solver, please make sure that you compile on a system that supports Fortran 77.
The history of the source code can be found here.
The models are included in a dynamic loaded library called SiMKit.
SiMKit is related to the following circuit simulators used within NXP:
- Pstar, the circuit simulator from NXP
- Spectre, the circuit simulator from Cadence
- ADS, the circuit simulator from Agilent.
You can read how to download and install the libraries here.
The source code is protected by Copyright © 1991, 2007, NXP.
Further information on MOS Model 11 is available in the following additional reports:
- Documentation for Level 1102: NL-TN2004/00085.pdf file. The parameter extraction methodology is also described in this report. Last update April 2005.
- Report on the physical background of MOS Model 11, Level 1101: NL_TN2003_00239.pdf (1.81MB). Last update April 2003.
- Documentation for Level 1100: NLUR2001_813.pdf file (461kB). The parameter extraction methodology is also described in this report. Last update June 2004.
- Documentation for Level 1101: NLUR2002_802.pdf file (632kB). The parameter extraction methodology is also described in this report. Last update April 2005.
- Proceedings of the MOS Model 11 workshop: NLUR2002_810.pdf file (5.29MB). Handouts for presentations about the physical background and the parameter extraction of MOS Model 11. Last update April 2002.
- "BSIM4 and MOS Model 11 benchmarks for MOSFET capacitances", A.J. Scholten et al., CMC meeting, March 2001 (852 kB).
- "Compact Model Council meeting" of December 14, 2000 (793 kB).
Further information on MOS Model 11 is available in the following related publications:
- "Compact Modeling of Drain and Gate Current Noise for RF CMOS", R. van Langevelde et al., IEDM 2003 Technical Digest, pp. 867-870, 2003 (259kB).
- "Noise Modeling for RF CMOS Circuit Simulation", A.J. Scholten et al., IEEE Trans. Electron Devices, Vol. ED-50, pp. 618-632, 2003 (810kB).
- "Compact Modeling of Drain and Gate Current Noise for RF CMOS", A.J. Scholten et al., IEDM 2002 Technical Digest, pp. 129-132, 2002 (442kB).
- "Gate current: Modeling, DL extraction and impact on RF performance", R. van Langevelde et al., IEDM 2001 Technical Digest, pp. 289-292, 2001 (265kB).
- "Compact modelling of pocket-implanted MOSFETs", A.J. Scholten et al., Proceedings ESSDERC 2001, pp. 311-314, 2001.
- "Advanced compact MOS modelling", R. van Langevelde et al., Proceedings ESSDERC 2001, pp. 81-90, 2001.
- "Compact MOS modelling for RF circuit simulation", A.J. Scholten et al., Proceedings SISPAD 2001, pp. 194-201, 2001.
- "RF-CMOS performance trends", P.H. Woerlee et al., IEEE Trans. Electron Devices, Vol. ED-48, pp. 1776-1782, 2001 (160kB).
- "RF-Distortion in deep sub-micron CMOS technologies", R. van Langevelde et al., IEDM 2000 Technical Digest, pp. 807-810, 2000 (259kB).
- "Efficient parameter extraction techniques for a new surface-potential-based MOS model for RF applications", W. Liang et al., Proceedings ICMTS 2001, pp. 141-145, 2001 (327kB).
- "RF-Distortion characterisation of sub-micron CMOS", L.F. Tiemeijer et al., Proceedings ESSDERC 2000, pp. 464-467, 2000.
- "An explicit surface-potential-based MOSFET model for circuit simulation", R. van Langevelde and F.M. Klaassen, Solid-State Electronics, Vol. 44, pp. 409-418, 2000.
- "Accurate thermal noise model for deep sub-micron CMOS", A.J. Scholten et al., IEDM 1999 Technical Digest, pp. 155-158, 1999 (264kB).
- "A compact MOSFET model for distortion analysis in analog circuit design", R. van Langevelde, Ph.D. Thesis, University of Technology Eindhoven, 1998.
- "Accurate drain conductance modeling for distortion analysis in MOSFETs", R. van Langevelde and F.M. Klaassen, IEDM 1997 Technical Digest, pp. 313-317, 1997 (362kB).
- "Effect of gate-field dependent mobility degradation on distortion analysis in MOSFET's", R. van Langevelde and F.M. Klaassen, IEEE Trans. Electron Devices, Vol. ED-44, pp. 2044-2052, 1997 (264kB).
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