Introduction to MOS Model 9
MOS Model 9 is a physics based analytical model for electrical circuit simulation and design for analogue applications. It provides an excellent description of the electrical characteristics in all relevant regions of transistor operation such as the sub-threshold current, the substrate current and the output conductance.
MOS Model 9 describes transistor behaviour over a wide range of channel lengths and widths using just one parameter set. Thereby making it easy and flexible to use across a broad spectrum of applications, while maintaining consistently high accuracy. The full documentation and source code of MOS Model 9 is freely available from this website.
Initially developed for use with Pstar, the NXP analogue circuit simulator, MOS Model 9 is suitable for use both in circuit design and process technology, as well as in CAD tool development.
Model definition of MOS Model 9
The model definition of MOS Model 9, 
Level 902 (782Kb)
and Level 903 (1.19MB) are available in PDF format,
as well as a definition of the hyp functions (113KB) used in this model.
The history of the model can be found here.
The description of the source-bulk and drain-bulk junction diode is not included in MOS Model 9. The behaviour of these junction diodes is modelled by the Juncap (152kB) model. This model has to be added between the source and bulk node and between the drain and bulk node
Source Code & Library
The source code of MOS Model 9 is available here.
The files called "device_m902.c" and "device_m903.c" contain the majority of the MOS Model 9 code. If you use the included solver, please make sure that you compile on a system that supports Fortran 77.
The history of the source code can be found here.
The models are included in a dynamically loaded library called SiMKit.
SiMKit is related to the following circuit simulators used within NXP:
- Pstar, the circuit simulator from NXP
- Spectre, the circuit simulator from Cadence
MOS model 9 is not available for the ADS simulator.
You can read how to download and install the libraries here.
The source code is protected by Copyright © 1991, 2007, NXP.
Additional documentation
Further information on MOS Model 9 is available in the following additional documentation:
- "New 1/f noise model in MOS Model 9, level 903", A.J. Scholten and D.B.M. Klaassen, Philips Research, Nat.Lab. Unclassified Report 816/98, 1998 (802kB).
- "Implementation of direct extraction methods for compact model parameters. Part I: The FORTRAN code", U. Weidenmueller, E. O'hAnnaidh, S. Healey and K. McCarthy, Philips Research, Nat.Lab. Unclassified Report 010/97, 1997 (Postscript file of 1.4MB).
- "Comparison of BSIM3v3 and MOS MODEL 9", S. Healey, K. McCarthy and D.B.M. Klaassen (ed.), Philips Research, Nat.Lab. Unclassified Report 002/97, 1997 (Postscript file of 1.3MB).
- "Comparison of BSIM3v2 and MOS MODEL 9", K.G. McCarthy, R.D.M.A. Velghe and D.B.M. Klaassen, Philips Research, Nat.Lab. Unclassified Report 027/95, 1995 (Postscript file of 2.6MB).
- "A large signal non-quasi-static MOS model for circuit simulation", A.J. Scholten, L.F. Tiemeijer, P.W.H de Vreede, and D.B.M. Klaassen, IEDM Techn. Digest (Washington, DC), pp. 163-166, 1999.
- "Compact Modelling of Submicron CMOS", D.B.M. Klaassen, Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC'96), pp. 40-46, Edition Frontieres, 1996 (2.5MB).
- "RF modelling of MOSFETs", D.B.M. Klaassen, B. Nauta and R.R.J. Vanoppen, in "Analog Circuit Design: MOST RF Circuits, Sigma-Delta Converters and Translinear Circuits", eds. W. Sansen, R.J. van de Plassche and J.H. Huijsing, pp. 3-24, Kluwer Academic Publishers, 1996 (971kB).
- "Proceedings of the MOS MODEL 9 workshop", D.B.M. Klaassen (ed.), Philips Research, Nat.Lab. Unclassified Report 009/96, 1996 (933kB).
Related publications
Further information on MOS Model 9 is available in the following related publications:
- "Impact of Process Scaling on 1/f Noise in Advanced CMOS Technologies", M.J. Knitel, P.H. Woerlee, A.J. Scholten, and A.T.A. Zegers - van Duijnhoven, IEDM Techn. Digest (San Francisco), pp. 463-466, 2000 (250kB).
- "Effect of dogbone geometry on source/drain resistance in narrow-width MOSFETs", A.J. Scholten and D.B.M. Klaassen, Solid-State Electronics 43, pp.1989-1996 (1999).
- "Anomalous geometry dependence of source/drain resistance in narrow-width MOSFETs", A.J. Scholten and D.B.M. Klaassen, Proceedings of the IC-MTS'98, pp. 77-82, 1998 (427kB).
- "Statistical characterization of 0.18 micron low-power CMOS process using efficient parameter extraction", K.G. McCarthy, E.V. Saavedra Diaz, D.B.M. Klaassen and A. Mathewson, Proceedings of the IC-MTS'98 (343kB).
- "RF noise modelling of 0.25 micron CMOS and low-power LNA's", R.R.J. Vanoppen, L.M.F. de Maaijer, D.B.M. Klaassen and L.F. Tiemeijer, IEDM Techn. Digest (Washington, DC), pp. 317-320, 1997 (294kB).
- "Efficient parameter extraction and statistical analysis for a 0.25 micron low-power CMOS process", E.V. Saavedra Diaz, K.G. McCarthy, D.B.M. Klaassen and A. Mathewson, Proceedings of the 27th European Solid-State Device Research Conference (ESSDERC'97), pp. 656-659, Edition Frontieres, 1997.
- "Circuit Sensitivity Analysis in Terms of Process Parameters", M.J. van Dort and D.B.M. Klaassen, IEDM Techn. Digest (Washington, DC), pp. 941-944, 1995 (278kB).
- "Prediction of compact MOS model parameters for low-power application", R.M.D.A. Velghe and D.B.M. Klaassen, Proceedings of the 25th European Solid-State Device Research Conference (ESSDERC'95), pp. 565-568, Edition Frontieres, 1995.
- "Sensitivity Analysis of an Industrial CMOS Process using RSM Techniques", M.J. van Dort and D.B.M. Klaassen, Proc. SISDEP, pp. 432-435, 1995.
- "The high-frequency analogue performance of MOSFETs", R.R.J. Vanoppen, J.A.M. Geelen and D.B.M. Klaassen, IEDM Techn. Digest (San Francisco, CA), pp. 173-176, 1994 (252kB).
- "Compact Modelling for Analogue Circuit Simulation", R.M.D.A. Velghe, D.B.M. Klaassen and F.M. Klaassen, Proceedings of the 24th European Solid-State Device Research Conference (ESSDERC'94), pp. 833-836, Edition Frontieres, 1994.
- "Compact Modelling for Analogue Circuit Simulation", R.M.D.A. Velghe, D.B.M. Klaassen and F.M. Klaassen, IEDM Techn. Digest (Washington, DC), pp. 485-488, 1993 (278kB).
- "Compact Transistor Modelling for Circuit Design", by H.C. de Graaff and F.M. Klaassen, Springer, 1990.
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