Select site:
English
QUBiC4


Philips Semiconductors' QUBiC4 process technology

QUBiC4, the latest version of Philips Semiconductors' highly successful silicon BiCMOS process technology, matches the performance of current SiGe (Silicon-Germanium) processes, giving manufacturers of mobile telecommunications equipment the cost, reliability and manufacturing advantages of all-silicon RF solutions for wireless applications operating up to 2.5 GHz and beyond. This not only includes the current generation of mobile phones, where manufacturers can take advantage of QUBiC4's exceptionally low power consumption to extend handset talk times even further, but also includes the coming generation of 3G mobiles, where higher integration levels and lower power consumption will be even more critical to handset design.

Advanced bipolars for RF bandwidth

QUBiC4 achieves its RF performance through the integration of advanced double-polysilicon npn bipolar transistors that feature a fT of 40 GHz and a fMAX of 90 GHz at very low currents. The exceptionally high fT of these transistors, which ensures that they exhibit very high current gains at frequencies far greater than 3 GHz, means that QUBiC4 based RF amplifiers require fewer gain stages, reducing both circuit complexity and power consumption.


A highly linear 16.7 dB gain low-noise amplifier (LNA) that achieves a noise figure of 0.97 dB and an input IP3 figure of +5 dBm at 2 GHz with a supply current of only 4 mA has been demonstrated using the QUBiC4 process. This level of performance is achieved as a result of QUBiC4's optimised NPN devices, which have very low noise figures of <0.5dB. Conversely, the high power-added efficiency of QUBiC4's bipolar transistors opens up the possibility of integrating the RF power amplifier into transceiver chips for 3G mobiles, where RF output powers of a few hundred milliwatts are required.

CMOS tailored for RF

The 0.25 µm CMOS geometry used in QUBiC4 is derived directly from Philips Semiconductors' 0.25 µm baseline CMOS process, allowing designers to use the company's extensive CMOS cell library in QUBiC4 chip designs. The gate density achievable with this process-geometry/cell-library combination is capable of reaching the 100k gate densities required to implement single-chip multi-mode transceivers for 3G applications.


However, QUBiC4's CMOS transistors are not restricted to the implementation of pure logic. Fully characterized at RF frequencies, they play a vital part in creating efficient interfaces between the RF and logic sections of QUBiC4 chips in circuits such as VCOs and mixers. To allow accurate simulation of their RF performance, non-quasi-static effects have been introduced into the simulation models of these transistors.

Quality passives for critical performance

The performance of RF chips is not determined solely by its transistor capability. The quality and accuracy of passive circuit components such as inductors and capacitors is equally important. While many RF chip manufacturers rely on these components being connected externally to the chip, this is far from ideal both in terms of size, component count, cost and most importantly, RF performance. Accurate matching between passive and active components relies on very short interconnect lengths and minimal parasitic capacitance, which are difficult to achieve through external connections. QUBiC4 concentrates on putting these components on-chip, while at the same time ensuring the component accuracy necessary to achieve optimum RF performance.


In addition to the passive component integration capabilities that have been transferred to QUBiC4 from Philips Semiconductors' QUBiC3 process, QUBiC4 features important new additions that further improve passive component performance and circuit flexibility.


To minimize the series resistance of on-chip inductors and hence increase their Q-factor (Quality Factor) QUBiC4 provides a thick metal layer in which precision spiral inductors can be formed. As a result, at 2GHz, a 1.5nH on-chip inductor can achieve Q-factors as high as 20 with QUBiC4. Philips Semiconductors' QUBiC4 process is also very area efficient in implementing these inductors, as illustrated by the chip micrograph shown in Figure 1.


Figure 1
Figure 1 - Micrograph of a triple-band GSM transceiver showing area efficiency of spiral inductors in the QUBiC process (top right-hand corner)

Advanced metal-metal capacitors using tantalum pentoxide as the dielectric have also been added to the passive components that can be integrated into QUBiC4 chips. Providing an area capacitance of 5 fF/µm2, these compact high-performance capacitors offer a considerable increase in RF design flexibility combined with the opportunity to achieve a significant shrink factor for many RF designs.


Together with on-chip varactors with Q-factors as high as 40 at 2 GHz, QUBiC4's high frequency transistors, inductors and capacitors provide all the components necessary to implement functions such as the Tx channel VCO into transceiver chips - something that has not previously been possible.

Minimizing RF losses

There is little point in maintaining the quality of the passive and active components on the chip if RF losses and RF interference issues are not equally addressed. Parasitic capacitances between circuit elements tend to de-tune resonant circuits, impair correct matching and lead to crosstalk interference, while RF losses in the substrate tend to reduce resonant circuit Q-factors and increase power consumption.


In common with Philips Semiconductors' QUBiC3 process technology, QUBiC4 makes extensive use of low-k (low dielectric constant) dielectrics to minimize the parasitic capacitance associated with metal interconnect layers, as well as lightly doped high-resistivity substrate layers to minimize RF losses.


New to the process are two additional isolation techniques - shallow and deep trench isolation - designed to reduce parasitic capacitance and crosstalk to the level at which full-duplex (simultaneous transmit and receive) operation is possible on the same chip. This will be a critical requirement in producing single-chip transceivers for 3G applications. The principle of deep trench isolation is shown in Figure 2 below.


Figure 2
Figure 2 - Deep trench isolation reduces parasitic capacitance around critical RF components, maintaining frequency response and minimizing crosstalk interference

Deep Trench isolation involves etching 6 µm deep trenches around critical components and filling these trenches with a combination of insulating materials. The depth of these trenches not only minimizes component-to-component parasitic capacitances, but also reduces substrate borne interference. As a result, Philips Semiconductors expects to be able to produce single-chip transceivers that meet the full-duplex requirements of 3G systems, where both the transmit and receive channels have to be active at the same time. Without deep trench isolation it would be necessary to divide the transmit and receive functions into two separate chips, leading to a less cost-effective solution.


Shallow Trench isolation is also used as a means of increasing packing density and reducing specific device capacitances. Successfully integrating the Deep Trench isolation within areas of Shallow Trench isolation, as illustrated in Figure 3 below, is a critical feature of QUBiC4.


Figure 3
Figure 3 - Integrated Deep and Shallow Trench isolation is a key contributor to QUBiC4's advanced RF performance.

QUBiC4 - a route to RF CMOS

As mentioned earlier, QUBiC4's CMOS transistors are not only suitable for implementing logic. They are also fully characterized for RF performance, which means that in combination with QUBiC4's passive component integration capabilities, high-resistivity substrates and deep-trench isolation, they can be used as a platform to study RF CMOS. For applications such as Bluetooth, where the radio specification is not too demanding, QUBiC4 may therefore offer a fast route to investigating low cost single-chip Bluetooth solutions.


Philips Semiconductors, which had annual revenues of approximately US$5 billion in 1999, designs and manufactures semiconductors and silicon systems platforms. Philips Semiconductors is spearheading the emerging field of systems on silicon solutions with the innovative Nexperia™ platform and VLSI Velocity™ tool set. The company's Sea-of-IP™ design methodology allows plug and play intellectual property blocks for easily customizable products. The company is a leader in communications, consumer, PC peripherals and automotive semiconductors, which are key applications for convergence in end-user products. Philips Semiconductors is headquartered in Eindhoven, The Netherlands, and has operations throughout the world.
For more information: www.nxp.com.