The DSP96002 is a single-chip, dual port, HCMOS, low-power, general purpose IEEE
floating-point Digital Signal Processor (DSP) that features 1024 words of data RAM (equally
divided into X data and Y data memory), 1024 words of full speed on-chip program RAM,
two preprogrammed data ROMs, a dual channel DMA controller, special on-chip bootstrap
hardware, and On-Chip Emulation (OnCE™) debug circuitry. The Central Processing Unit
(CPU) consists of three 32-bit execution units operating in parallel. The DSP96002 has two
identical memory expansion ports with control lines that facilitate interfacing to SRAMs,
fast-access DRAMs, and Video RAMs (VRAMs). Each port can be transformed into a Host
Interface (HI), which facilitates easy interfacing to other processors for multiprocessor
applications. Linear arrays of DSP96002s can be implemented without glue logic. The MPU-style programming model and instruction set allow straightforward generation of efficient,
compact code. The high speed of the DSP96002 makes it well-suited for high bandwidth and
numerically intensive applications such as graphics, image, and numeric processing.