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74ALVCH162601
General description
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA /CEAB ).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA ,LEBA and CPBA.
To ensure the high-impedance state during power-down, OEBA and OEAB should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
The 74ALVCH162601 is designed with 30 W series resistors in both HIGH or LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
- Complies with JEDEC standard no. 8-1A
- CMOS low power consumption
- Direct interface with TTL levels
- MULTIBYTETM flow-through standard pin-out architecture
- Low inductance multiple VCC and ground pins for minimum noise and ground bounce
- All data inputs have bus hold circuitry
- Integrated 30 W termination resistors.
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH162601DGG | 74ALVCH162601DG | 9352 628 00112 | Volume production | SOT364-1
(TSSOP56) | Tube | Standard Marking | 74ALVCH162601DGG
| week 2, 2006 |
| 74ALVCH162601DGG | 74ALVCH162601DG-T | 9352 628 00118 | Volume production | SOT364-1
(TSSOP56) | Reel Pack, SMD, 13" | Standard Marking | 74ALVCH162601DGG
| week 2, 2006 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH162601DGG | 9352 628 00112 | 1.8000 | not available | |||||
| 74ALVCH162601DGG | 9352 628 00118 | 1.8000 | Order samples |
Applications
Related applications
50-60 Hz CRT integrated DTV (TV210D)
Mid-range integrated DTV (TV810)
Transceiver board
Main CPU board
Technical documents
Application Notes
Parametrics/similar products
| Type number | Package | Description | Propagation Delay(ns) | Voltage | No. of Pins | Power Dissipation Considerations | Logic Switching Levels | Output Drive Capability |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH162601DGG | SOT364-1
(TSSOP56) | 2.5/3.3V 18-Bit Universal Bus Transceiver; Positive Edge Trigger Clock with Bus Hold and 30 Ohm Termination Resistors; (3-State) | 3.1@3.3V | 1.2-3.6 | 56 | Low Power or Battery Applications | TTL | +/- 12 mA |
Similar products
74ALVCH162601 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.
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