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74ALVCH16543

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Datasheet

74ALVCH16543
(Product Specification)
23-Nov-99, 20 pages, 98 kB

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74ALVCH16543 - 16-bit D-type registered transceiver; 3-state

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary storage of the data flow in either direction.

Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control in either direction of the data flow.

The ?16543? contains two sections each consisting of two sets of eight D-type latches with separate inputs and controls for each set. For data flow from A to B, for example, the A-to-B enable (nEAB, where n equals 1 or 2) inputs must be LOW in order to enter data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function table. With nEAB LOW, a LOW signal on the A-to-B latch enable (nLEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the nLEAB signal stores the A data into the latches. With nEAB and nOEAB both LOW, the 3-state B output buffers are active and display the data present at the output of the A latches. Similarly, the nEBA, nLEBA and nOEBA signals control the data flow from B-to-A.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features

  • In accordance with JEDEC standard no 8-1A
  • CMOS low power consumption
  • Direct interface with TTL levels
  • MULTIBYTEÔ flow-through pin-out architecture
  • 16-bit transceiver with D-type latch
  • Combines 16245 and 16373 type functions in one chip
  • Back-to-back registers for storage
  • Output drive capability 50 W transmission lines at 85 °C
  • Separate controls for data flow in each direction
  • All data inputs have bus hold
  • 3-state non-inverting outputs for bus oriented applications
  • Current drive ±24 mA at 3.0 V.


Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74ALVCH16543DGG74ALVCH16543DGG:119352 625 44112Volume productionSOT364-1
(TSSOP56)
TubeStandard Marking
74ALVCH16543DGG74ALVCH16543DGG,119352 625 44118Volume productionSOT364-1
(TSSOP56)
Reel Pack, SMD, 13"Standard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74ALVCH16543DGG74ALVCH16543DGG:1174ALVCH16543DGG
week 2, 2006 3,872,58E+081
74ALVCH16543DGG74ALVCH16543DGG,1174ALVCH16543DGG
week 2, 2006 3,872,58E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74ALVCH16543DGG9352 625 44112  74ALVCH16543DGG:11  1.6700      not available
74ALVCH16543DGG9352 625 44118  74ALVCH16543DGG,11  1.6700NAARROW ELECTRONICS4,000 11/19/2009Buy onlinenot available

Block diagrams/pinning

Design support

Application Notes

Parametrics/similar products

Type numberPackageDescriptionPropagation Delay(ns)VoltageNo. of PinsPower Dissipation ConsiderationsLogic Switching LevelsOutput Drive Capability
74ALVCH16543DGGSOT364-1
(TSSOP56)
2.5/3.3V 16-Bit Latched Transceiver; Non-Inverting with Bus Hold (3-State)3.8@3.3V1.2-3.656Low Power or Battery ApplicationsTTL+/- 24 mA


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