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74ALVCH16601
General description
The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA)latch enable (LEAB and LEBA ) , and clock (CPAB and CPBA) inputs. For A-to-B data flowthe device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA /CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBALEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
- Complies with JEDEC standard no. 8-1A
- CMOS low power consumption
- Direct interface with TTL levels
- MULTIBYTEÔ flow-through standard pin-out architecture
- Low inductance multiple VCC and ground pins for minimum noise and ground bounce
- Current drive ± 24 mA at 3.0 V
- All inputs have bus hold circuitry
- Output drive capability 50W transmission lines @ 85°C
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | 74ALVCH16601DG | 9352 625 46112 | Volume production | SOT364-1
(TSSOP56) | Tube | Standard Marking | 74ALVCH16601DGG
| week 2, 2006 |
| 74ALVCH16601DGG | 74ALVCH16601DG-T | 9352 625 46118 | Volume production | SOT364-1
(TSSOP56) | Reel Pack, SMD, 13" | Standard Marking | 74ALVCH16601DGG
| week 2, 2006 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | 9352 625 46112 | 1.4300 | not available | |||||
| 74ALVCH16601DGG | 9352 625 46118 | 1.4300 | Order samples |
Applications
Related applications
Low / mid-range analog CRT TV (TV200)
Highly featured analog CRT TV (TV210)
50-60 Hz CRT integrated DTV (TV210D)
Mid-range integrated DTV (TV810)
Transceiver board
Main CPU board
Technical documents
Application Notes
Parametrics/similar products
| Type number | Package | Description | Fmax(MHz) | Propagation Delay(ns) | Voltage | No. of Pins | Power Dissipation Considerations | Logic Switching Levels | Output Drive Capability |
|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | SOT364-1
(TSSOP56) | 2.5/3.3V 18-Bit Universal Bus Transceiver; Positive Edge Trigger Clock with Bus Hold (3-State) | 390 | 2.8@3.3V | 2.3-3.6 | 56 | Low Power or Battery Applications | TTL | +/- 24 mA |
Similar products
74ALVCH16601 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.
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