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74ALVCH16601

Selection guide

Datasheet

74ALVCH16601
(Product Specification)
24-Sep-98, 12 pages, 96 kB

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74ALVCH16601 - 18-bit universal bus transceiver (3-State)

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA)latch enable (LEAB and LEBA ) , and clock (CPAB and CPBA) inputs. For A-to-B data flowthe device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA /CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBALEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features

  • Complies with JEDEC standard no. 8-1A
  • CMOS low power consumption
  • Direct interface with TTL levels
  • MULTIBYTEÔ flow-through standard pin-out architecture
  • Low inductance multiple VCC and ground pins for minimum noise and ground bounce
  • Current drive ± 24 mA at 3.0 V
  • All inputs have bus hold circuitry
  • Output drive capability 50W transmission lines @ 85°C

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74ALVCH16601DGG74ALVCH16601DGG,119352 625 46112Volume productionSOT364-1
(TSSOP56)
TubeStandard Marking
74ALVCH16601DGG74ALVCH16601DGG:119352 625 46118Volume productionSOT364-1
(TSSOP56)
Reel Pack, SMD, 13"Standard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74ALVCH16601DGG74ALVCH16601DGG,1174ALVCH16601DGG
week 2, 2006 3,872,58E+081
74ALVCH16601DGG74ALVCH16601DGG:1174ALVCH16601DGG
week 2, 2006 3,872,58E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74ALVCH16601DGG9352 625 46112  74ALVCH16601DGG,11  1.4300NAFUTURE ELECTRONICS875 11/19/2009Buy onlinenot available
74ALVCH16601DGG9352 625 46118  74ALVCH16601DGG:11  1.4300      not available

Applications


Related applications
Transceiver board
Main CPU board

Block diagrams/pinning

Design support

Application Notes

Parametrics/similar products

Type numberPackageDescriptionFmax(MHz)Propagation Delay(ns)VoltageNo. of PinsPower Dissipation ConsiderationsLogic Switching LevelsOutput Drive Capability
74ALVCH16601DGGSOT364-1
(TSSOP56)
2.5/3.3V 18-Bit Universal Bus Transceiver; Positive Edge Trigger Clock with Bus Hold (3-State)3902.8@3.3V2.3-3.656Low Power or Battery ApplicationsTTL+/- 24 mA


Similar products
74ALVCH16601 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.