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74ALVCH16601
Datasheet
(Product Specification)
24-Sep-98, 12 pages, 96 kB
General description
The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA)latch enable (LEAB and LEBA ) , and clock (CPAB and CPBA) inputs. For A-to-B data flowthe device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA /CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBALEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
- Complies with JEDEC standard no. 8-1A
- CMOS low power consumption
- Direct interface with TTL levels
- MULTIBYTEÔ flow-through standard pin-out architecture
- Low inductance multiple VCC and ground pins for minimum noise and ground bounce
- Current drive ± 24 mA at 3.0 V
- All inputs have bus hold circuitry
- Output drive capability 50W transmission lines @ 85°C
Products/packages
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking | ECCN |
|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | 74ALVCH16601DGG,11 | 9352 625 46112 | Volume production | SOT364-1
(TSSOP56) | Tube | Standard Marking | |
| 74ALVCH16601DGG | 74ALVCH16601DGG:11 | 9352 625 46118 | Volume production | SOT364-1
(TSSOP56) | Reel Pack, SMD, 13" | Standard Marking |
Quality/reliability/chemical content
| Type number | Orderable part number | Chemical content | RoHS | Leadfree Conversion date | RHF | IRF (FIT) | MTBF (hours) | MSL |
|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | 74ALVCH16601DGG,11 | 74ALVCH16601DGG |
| week 2, 2006 | 3,87 | 2,58E+08 | 1 | |
| 74ALVCH16601DGG | 74ALVCH16601DGG:11 | 74ALVCH16601DGG |
| week 2, 2006 | 3,87 | 2,58E+08 | 1 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Orderable part number | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | 9352 625 46112 | 74ALVCH16601DGG,11 | 1.4300 | NA | FUTURE ELECTRONICS | 875 | 11/19/2009 | Buy online | not available | |
| 74ALVCH16601DGG | 9352 625 46118 | 74ALVCH16601DGG:11 | 1.4300 | not available |
Parametrics/similar products
| Type number | Package | Description | Fmax(MHz) | Propagation Delay(ns) | Voltage | No. of Pins | Power Dissipation Considerations | Logic Switching Levels | Output Drive Capability |
|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16601DGG | SOT364-1
(TSSOP56) | 2.5/3.3V 18-Bit Universal Bus Transceiver; Positive Edge Trigger Clock with Bus Hold (3-State) | 390 | 2.8@3.3V | 2.3-3.6 | 56 | Low Power or Battery Applications | TTL | +/- 24 mA |
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