74AUP1G08

General description

The 74AUP1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF . The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G08 provides the single 2-input AND function.

Features

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114-C Class 3A. Exceeds 5000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101-C exceeds 1000 V
• Low static power consumption; I_CC = 0.9 uA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 pct of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 Cel to +85Cel and -40 Cel to +125 Cel

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

Related applications
Transceiver board
Main CPU board

Block diagrams/pinning

Design support

Application Notes

AN10161; PicoGate Logic footprints (2002-10-30)

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer