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74AUP1G175

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Datasheet

74AUP1G175
(Product Specification)
28-Feb-08, 20 pages, 103 kB

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74AUP1G175 - Low-power D-type flip-flop with reset; positive-edge trigger

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114E Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AUP1G175GF74AUP1G175GF,1329352 813 34132Volume productionSOT891
(XSON6)
Tape reel smd
74AUP1G175GM74AUP1G175GM,1159352 800 04115Volume productionSOT886
(XSON6)
Tape reel smdStandard Marking
74AUP1G175GM74AUP1G175GM,1329352 800 04132Volume productionSOT886
(XSON6)
Tape reel smd
74AUP1G175GW74AUP1G175GW,1259352 800 03125Volume productionSOT363
(SC-88)
Tape reel smd, ReverseStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74AUP1G175GF74AUP1G175GF,13274AUP1G175GF
Always Pb-free 3,293,04E+081
74AUP1G175GM74AUP1G175GM,11574AUP1G175GM
Always Pb-free 3,293,04E+081
74AUP1G175GM74AUP1G175GM,13274AUP1G175GM
Always Pb-free 3,293,04E+081
74AUP1G175GW74AUP1G175GW,12574AUP1G175GW
Always Pb-free 3,293,04E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1G175GF9352 813 34132  74AUP1G175GF,132        not available
74AUP1G175GM9352 800 04115  74AUP1G175GM,115  NADIGI-KEY CORPORATION9,839 11/20/2009Buy onlineOrder samples
    NAFUTURE ELECTRONICS5,000 11/19/2009Buy online 
74AUP1G175GM9352 800 04132  74AUP1G175GM,132        not available
74AUP1G175GW9352 800 03125  74AUP1G175GW,125  0.2500      Order samples

Block diagrams/pinning

Design support

Application Notes