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74AUP1G240

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Datasheet

74AUP1G240
(Product Specification)
06-Nov-06, 19 pages, 100 kB

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74AUP1G240 - Low-power inverting buffer/line driver; 3-state

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF . The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state.

This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114-D exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101-C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • Input-disable feature allows floating input conditions
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AUP1G240GF74AUP1G240GF,1329352 811 23132Volume productionSOT891
(XSON6)
Tape reel smd
74AUP1G240GM74AUP1G240GM,1159352 790 62115Volume productionSOT886
(XSON6)
Tape reel smdStandard Marking
74AUP1G240GM74AUP1G240GM,1329352 790 62132Volume productionSOT886
(XSON6)
Tape reel smd
74AUP1G240GW74AUP1G240GW,1259352 790 61125Volume productionSOT353-1
(TSSOP5)
Reel Pack, Reverse, ReverseStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74AUP1G240GF74AUP1G240GF,13274AUP1G240GF
Always Pb-free 3,293,04E+081
74AUP1G240GM74AUP1G240GM,11574AUP1G240GM
Always Pb-free 3,293,04E+081
74AUP1G240GM74AUP1G240GM,13274AUP1G240GM
Always Pb-free 3,293,04E+081
74AUP1G240GW74AUP1G240GW,12574AUP1G240GW
Always Pb-free 3,293,04E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1G240GF9352 811 23132  74AUP1G240GF,132        not available
74AUP1G240GM9352 790 62115  74AUP1G240GM,115  NADIGI-KEY CORPORATION9,814 11/20/2009Buy onlineOrder samples
74AUP1G240GM9352 790 62132  74AUP1G240GM,132        not available
74AUP1G240GW9352 790 61125  74AUP1G240GW,125  ASIAWPI30,000300011/19/2009Buy onlineOrder samples

Block diagrams/pinning

Design support

Application Notes