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Datasheet

74AUP1G374
(Product Specification)
14-Nov-06, 21 pages, 105 kB

General description

The 74AUP1G374 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF . The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the flip-flop is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the flip-flop.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114-D exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101-C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
74AUP1G374GF74AUP1G374GF-H9352 813 33132Volume productionSOT891
(XSON6)
Tape reel smd74AUP1G374GF
74AUP1G374GM74AUP1G374GM-G9352 806 24115Volume productionSOT886
(XSON6)
Tape reel smdStandard Marking74AUP1G374GM
74AUP1G374GM74AUP1G374GM-H9352 806 24132Volume productionSOT886
(XSON6)
Tape reel smd74AUP1G374GM
74AUP1G374GW74AUP1G374GW-G9352 806 23125Volume productionSOT363
(UMT6; SC-88)
Tape reel smd, ReverseStandard Marking74AUP1G374GW

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
74AUP1G374GF9352 813  33132        Order samples
74AUP1G374GM9352 806  24115       not available
74AUP1G374GM9352 806  24132        Order samples
74AUP1G374GW9352 806  23125        Order samples

Block diagrams/pinning

Technical documents

Application Notes

AN10161_2; PicoGate Logic footprints (30-Oct-02)

Support Documents

75015252; Philips ultra-low-power CMOS logic 74AUP1G/2G/3Gxx (2005-11-01)

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