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74AUP1G74

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Datasheet

74AUP1G74
(Product Specification)
03-Jun-08, 24 pages, 121 kB

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74AUP1G74 - Low-power D-type flip-flop with set and reset; positive-edge trigger

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114E Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AUP1G74DC74AUP1G74DC,1259352 807 17125Volume productionSOT765-1
(VSSOP8)
Reel Pack, Reverse, ReverseStandard Marking
74AUP1G74GD74AUP1G74GD,1259352 868 39125Volume productionSOT996-2
(XSON8U)
Reel Pack, Reverse, ReverseStandard Marking
74AUP1G74GM74AUP1G74GM,1259352 812 87125Volume productionSOT902-1
(XQFN8U)
Reel Pack, Reverse, ReverseStandard Marking
74AUP1G74GT74AUP1G74GT,1159352 807 18115Volume productionSOT833-1
(XSON8U)
Reel Pack, SMD, 7"Standard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74AUP1G74DC74AUP1G74DC,12574AUP1G74DC
Always Pb-free 3,293,04E+081
74AUP1G74GD74AUP1G74GD,12574AUP1G74GD
Always Pb-free 3,293,04E+081
74AUP1G74GM74AUP1G74GM,12574AUP1G74GM
Always Pb-free 3,293,04E+081
74AUP1G74GT74AUP1G74GT,11574AUP1G74GT
Always Pb-free 3,293,04E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1G74DC9352 807 17125  74AUP1G74DC,125  0.2600NAFUTURE ELECTRONICS3,000 11/19/2009Buy onlinenot available
74AUP1G74GD9352 868 39125  74AUP1G74GD,125        not available
74AUP1G74GM9352 812 87125  74AUP1G74GM,125  0.3200NADIGI-KEY CORPORATION6,935 11/20/2009Buy onlineOrder samples
74AUP1G74GT9352 807 18115  74AUP1G74GT,115  NADIGI-KEY CORPORATION9,362 11/20/2009Buy onlinenot available

Block diagrams/pinning

Design support

Application Notes