NXP Semiconductors


Select site:

English

74AUP1G80

Selection guide

Datasheet

74AUP1G80
(Product Specification)
20-Oct-06, 18 pages, 96 kB

Download all documentation

74AUP1G80 - Low-power D-type flip-flop; positive-edge trigger

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF . The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114-D exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101-C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AUP1G80GF74AUP1G80GF,1329352 811 18132Volume productionSOT891
(XSON6)
Tape reel smd
74AUP1G80GM74AUP1G80GM,1159352 790 51115Volume productionSOT886
(XSON6)
Tape reel smdStandard Marking
74AUP1G80GM74AUP1G80GM,1329352 790 51132Volume productionSOT886
(XSON6)
Tape reel smd
74AUP1G80GW74AUP1G80GW,1259352 790 49125Volume productionSOT353-1
(TSSOP5)
Reel Pack, Reverse, ReverseStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74AUP1G80GF74AUP1G80GF,13274AUP1G80GF
Always Pb-free 3,293,04E+081
74AUP1G80GM74AUP1G80GM,11574AUP1G80GM
Always Pb-free 3,293,04E+081
74AUP1G80GM74AUP1G80GM,13274AUP1G80GM
Always Pb-free 3,293,04E+081
74AUP1G80GW74AUP1G80GW,12574AUP1G80GW
Always Pb-free 3,293,04E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1G80GF9352 811 18132  74AUP1G80GF,132        not available
74AUP1G80GM9352 790 51115  74AUP1G80GM,115  0.2600      Order samples
74AUP1G80GM9352 790 51132  74AUP1G80GM,132  0.2600      not available
74AUP1G80GW9352 790 49125  74AUP1G80GW,125  NAMOUSER ELECTRONICS2,725 11/20/2009Buy onlineOrder samples
    NAMOUSER ELECTRONICS2,725 11/20/2009Buy online 

Block diagrams/pinning

Design support

Application Notes