74AUP1T1326

General description

The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.

The 74AUP1T1326 is designed for logic-level translation applications and combines the functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The output of the OR-gate is also available at output 1Y.

The output enable inputs (1OE and 2OE) switch at different points for positive and negative-going signals. The difference between the positive voltage V_T+ and the negative voltage V_T- is defined as the input hysteresis voltage V_H.

Both V_CC(A) and V_CC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced to V_CC(A) and pins A and 2Y are referenced to V_CC(B). A logic LOW on both output enable pins causes the output 2Y to assume a high-impedance OFF-state.

The device ensures low static and dynamic power consumption and is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the outputs, preventing any damaging backflow current through the device when it is powered down.

Features

• Wide supply voltage range:
  • V_CC(A): 1.1 V to 3.6 V; V_CC(B): 1.1 V to 3.6 V.
• High noise immunity
• Complies with JEDEC standards:
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114E Class 2A exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101C exceeds 1000 V
• Low static power consumption; I_CC = 0.9 uA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 pct of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 Cel to +85 Cel

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN10161; PicoGate Logic footprints (2002-10-30)

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer