74AUP1T57

General description

The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to V_CC or GND.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 2.3 V to 3.6 V.

The 74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V_CC range.

Features

• Wide supply voltage range from 2.3 V to 3.6 V
• High noise immunity
• ESD protection:
  • HBM JESD22-A114E Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101C exceeds 1000 V
• Low static power consumption; I_CC = 1.5 uA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 pct of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Pricing/ordering/availability

Applications

Related applications
PDA - discretes focus
Transceiver board
Main CPU board

Block diagrams/pinning

Technical documents

Application Notes

AN10161_2; PicoGate Logic footprints (30-Oct-02)

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