74AUP1Z04

General description

The 74AUP1Z04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF at output Y. The I_OFF circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down.

When not in use the EN input can be driven HIGH, pulling up the X1 input and putting the device in a low power disable mode. Schmitt-trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

The integration of the two devices into the 74AUP1Z04 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature.

Features

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• ESD protection:
• HBM JESD22-A114D Class 3A exceeds 5000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101C exceeds 1000 V
• Low static power consumption; I_CC = 0.9 uA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 pct of V_CC
• I_OFF circuitry provides partial Power-down mode operation at output Y
• Multiple package options
• Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Technical documents

Application Notes

AN10161_2; PicoGate Logic footprints (30-Oct-02)

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