NXP Semiconductors


Select site:

English

74AUP2G240

Selection guide

Datasheet

(Product Specification)
v.4, 30-Jun-09, 20 pages, 109 kB

Download all documentation

Low-power dual inverting buffer/line driver; 3-state

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114E Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low-noise overshoot and undershoot < 10 pct of VCC
  • Input-disable feature allows floating input conditions
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AUP2G240DC74AUP2G240DC,1259352 807 36125Volume productionSOT765-1
(VSSOP8)
Reel Pack, Reverse, ReverseStandard Marking
74AUP2G240GD74AUP2G240GD,1259352 888 75125Volume productionSOT996-2
(XSON8U)
Reel Pack, Reverse, ReverseStandard Marking
74AUP2G240GM74AUP2G240GM,1259352 814 37125Volume productionSOT902-1
(XQFN8U)
Reel Pack, Reverse, ReverseStandard Marking
74AUP2G240GT74AUP2G240GT,1159352 807 37115Volume productionSOT833-1
(XSON8U)
Reel Pack, SMD, 7"Standard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL Lead-free
74AUP2G240DC74AUP2G240DC,12574AUP2G240DC
Always Pb-free 3,293,04E+081
74AUP2G240GD74AUP2G240GD,12574AUP2G240GD
Always Pb-free 3,293,04E+081
74AUP2G240GM74AUP2G240GM,12574AUP2G240GM
Always Pb-free 3,293,04E+081
74AUP2G240GT74AUP2G240GT,11574AUP2G240GT
Always Pb-free 3,293,04E+081

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP2G240DC9352 807 36125  74AUP2G240DC,125  NAARROW ELECTRONICS125 3/18/2010Buy onlineOrder samples
    JAPANCHIP ONE STOPno 03/19/2010Buy online 
74AUP2G240GD9352 888 75125  74AUP2G240GD,125        not available
74AUP2G240GM9352 814 37125  74AUP2G240GM,125  NAARROW ELECTRONICS125 3/18/2010Buy onlineOrder samples
74AUP2G240GT9352 807 37115  74AUP2G240GT,115  NAARROW ELECTRONICS115 3/18/2010Buy onlineOrder samples

Block diagrams/pinning

Design support

Application Notes

Parametrics/similar products

Type numberPackageDescriptionFmax(MHz)Operating
temp.(Cel)
Propagation Delay(ns)VoltageNo. of PinsPower Dissipation ConsiderationsLogic Switching LevelsOutput Drive Capability
74AUP2G240DCSOT765-1
(VSSOP8)
dual inverter/line driver (3-state)70.0-40~1258.71.1-3.6 V8.0Ultra LowCMOS1.9/-1.9 mA
74AUP2G240GMSOT902-1
(XQFN8U)
dual inverter/line driver (3-state)70.0-40~1258.71.1-3.6 V8.0Ultra LowCMOS1.9/-1.9 mA
74AUP2G240GTSOT833-1
(XSON8U)
dual inverter/line driver (3-state)70.0-40~1258.71.1-3.6 V8.0Ultra LowCMOS1.9/-1.9 mA


Similar products
74AUP2G240 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.