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Datasheet

74AUP2GU04
(Product Specification)
15-Dec-06, 16 pages, 90 kB

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General description

The 74AUP2GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible families.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP2GU04 provides two unbuffered inverting gates.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114D Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Low static power consumption; ICC = 0.9 uA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Multiple package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
74AUP2GU04GF74AUP2GU04GF-H9352 813 22132Volume productionSOT891Tape reel smd74AUP2GU04GF
74AUP2GU04GM74AUP2GU04GM-G9352 800 01115Volume productionSOT886
(XSON6)
Tape reel smdStandard Marking74AUP2GU04GM
74AUP2GU04GM74AUP2GU04GM-H9352 800 01132Volume productionSOT886
(XSON6)
Tape reel smd74AUP2GU04GM
74AUP2GU04GW74AUP2GU04GW-G9352 799 98125Volume productionSOT363
(UMT6; SC-88)
Tape reel smd, ReverseStandard Marking74AUP2GU04GW

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
74AUP2GU04GF9352 813  22132        Order samples
74AUP2GU04GM9352 800  01115  0.3300NADIGI-KEY CORPORATION5,0009/6/2008 Buy online Order samples
   NADIGI-KEY CORPORATION4,4439/6/2008 Buy online  
74AUP2GU04GM9352 800  01132       not available
74AUP2GU04GW9352 799  98125  0.2500NADIGI-KEY CORPORATION3,0009/6/2008 Buy online Order samples
   NADIGI-KEY CORPORATION1,5809/6/2008 Buy online  
   NAMOUSER ELECTRONICS2,9909/5/2008 Buy online  

Block diagrams/pinning

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