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74AVCH2T45

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Datasheet

74AVCH2T45
(Product Specification)
06-May-09, 31 pages, 151 kB

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74AVCH2T45 - Dual-bit, dual-supply voltage level translator/transceiver; 3-state

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
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Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features

  • Wide supply voltage range:
    • VCC(A): 0.8 V to 3.6 V
    • VCC(B): 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114E Class 3B exceeds 8000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Maximum data rates:
    • 500 Mbps (1.8 V to 3.3 V translation)
    • 320 Mbps (< 1.8 V to 3.3 V translation)
    • 320 Mbps (translate to 2.5 V or 1.8 V)
    • 280 Mbps (translate to 1.5 V)
    • 240 Mbps (translate to 1.2 V)
  • Suspend mode
  • Bus hold on data inputs
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 pct of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • SOT765-1 and SOT833-1 package options
  • Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
74AVCH2T45DC74AVCH2T45DC,1259352 837 21125Volume productionSOT765-1
(VSSOP8)
Reel Pack, Reverse, ReverseStandard Marking
74AVCH2T45GD74AVCH2T45GD,1259352 882 83125Volume productionSOT996-2
(XSON8U)
Reel Pack, Reverse, ReverseStandard Marking
74AVCH2T45GT74AVCH2T45GT,1159352 837 22115Volume productionSOT833-1
(XSON8U)
Reel Pack, SMD, 7"Standard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
74AVCH2T45DC74AVCH2T45DC,12574AVCH2T45DC
Always Pb-free
74AVCH2T45GD74AVCH2T45GD,12574AVCH2T45GD
Always Pb-free
74AVCH2T45GT74AVCH2T45GT,11574AVCH2T45GT
Always Pb-free

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AVCH2T45DC9352 837 21125  74AVCH2T45DC,125        Order samples
74AVCH2T45GD9352 882 83125  74AVCH2T45GD,125        not available
74AVCH2T45GT9352 837 22115  74AVCH2T45GT,115        Order samples

Applications


Related applications
Transceiver board
Main CPU board

Block diagrams/pinning

Design support

Application Notes