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74F112
Datasheet
(Product Specification)
09-Feb-90, 10 pages, 94 kB
General description
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.
Products/packages
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking | ECCN |
|---|---|---|---|---|---|---|---|
| I74F112D | I74F112D,602 | 9350 256 50602 | Volume production | SOT109 | Tube (Signetics) | Standard Marking | |
| I74F112D | I74F112D,623 | 9350 256 50623 | Volume production | SOT109 | Reel Pack, SMD, 13" (Signetics) | Standard Marking | |
| I74F112N | I74F112N,602 | 9350 256 60602 | Volume production | SOT38-4
(DIP16) | Tube (Signetics) | Standard Marking | |
| N74F112D | N74F112D,602 | 9338 613 00602 | Volume production | SOT109 | Tube (Signetics) | Standard Marking | |
| N74F112D | N74F112D,623 | 9338 613 00623 | Volume production | SOT109 | Reel Pack, SMD, 13" (Signetics) | Standard Marking | |
| N74F112N | N74F112N,602 | 9337 946 60602 | Volume production | SOT38-4
(DIP16) | Tube (Signetics) | Standard Marking |
Quality/reliability/chemical content
| Type number | Orderable part number | Chemical content | RoHS | Leadfree Conversion date | RHF | IRF (FIT) | MTBF (hours) | MSL |
|---|---|---|---|---|---|---|---|---|
| I74F112D | I74F112D,602 | I74F112D |
| week 6, 2004 | 5,63 | 1,78E+08 | 1 | |
| I74F112D | I74F112D,623 | I74F112D |
| week 6, 2004 | 5,63 | 1,78E+08 | 1 | |
| I74F112N | I74F112N,602 | I74F112N |
| Always Pb-free | 5,63 | 1,78E+08 | NA | |
| N74F112D | N74F112D,602 | N74F112D |
| week 6, 2004 | 5,63 | 1,78E+08 | 1 | |
| N74F112D | N74F112D,623 | N74F112D |
| week 6, 2004 | 5,63 | 1,78E+08 | 1 | |
| N74F112N | N74F112N,602 | N74F112N |
| Always Pb-free | 5,63 | 1,78E+08 | NA |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Orderable part number | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|---|
| I74F112D | 9350 256 50602 | I74F112D,602 | not available | |||||||
| I74F112D | 9350 256 50623 | I74F112D,623 | not available | |||||||
| I74F112N | 9350 256 60602 | I74F112N,602 | not available | |||||||
| N74F112D | 9338 613 00602 | N74F112D,602 | 0.2300 | not available | ||||||
| N74F112D | 9338 613 00623 | N74F112D,623 | 0.2300 | not available | ||||||
| N74F112N | 9337 946 60602 | N74F112N,602 | 0.2800 | not available |
Design support
Application Notes
AN216;
Arbitration in shared resource systems (1988-07-18)AN203;
Test Fixtures for High Speed Logic (1998-04-02)AN202;
Testing and specifying FAST logic (1987-06-01)Parametrics/similar products
| Type number | Package | Description | Fmax(MHz) | Propagation Delay(ns) | Voltage | No. of Pins | Logic Switching Levels | Output Drive Capability |
|---|---|---|---|---|---|---|---|---|
| I74F112D | SOT109
| Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger | 100 | 5 | 4.5-5.5 V | 16 | TTL | -1/+20 mA |
| I74F112N | SOT38-4
(DIP16) | Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger | 100 | 5 | 4.5-5.5 V | 16 | TTL | -1/+20 mA |
| N74F112D | SOT109
| Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger | 100 | 5 | 4.5-5.5 V | 16 | TTL | -1/+20 mA |
| N74F112N | SOT38-4
(DIP16) | Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger | 100 | 5 | 4.5-5.5 V | 16 | TTL | -1/+20 mA |
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74F112
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