74F191

General description

The 74F191 is a 4-bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations.

Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D₀ - D₃) is loaded into the counter and appears on the outputs when the Parallel Load (PL) input is Low. This operation overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of outputs, the Terminal Count (TC) and Ripple Clock (RC).

The TC output is normally Low and goes High when: 1) the count reaches zero in the countdown mode or 2) reaches ?15? in the count up mode. The TC output will remain High until a state change occurs, either by counting or presetting, or until U/D is changed. TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is High and CE is Low, the RC follows the clock pulse. The RC output essentially duplicates the Low clock pulse width, although delayed in time by two gate delays.

Features

• High speed ?125MHz typical f_MAX
• Synchronous, reversible counting
• 4-Bit binary
• Asynchronous parallel load capability
• Cascadable without external logic
• Single up/down control input

Block diagrams/pinning

Technical documents

Application Notes

AN2021_1; Thermal considerations for FAST logic products (13-Mar-95)

AN202_1; Testing and specifying FAST logic (01-Jun-87)

AN203_2; Test Fixtures for High Speed Logic (02-Apr-98)

AN216_2; Arbitration in shared resource systems (18-Jul-88)

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