74F193

General description

The 74F193 is a 4-bit synchronous up/down counter in the binary mode. Separate up/down clocks, CP_U and CP_D respectively, simplify operation. The outputs change state synchronously with the Low-to-High transition of either clock input. If the CP_U clock is pulsed while CP_D is held High, the device will count up. If CP_D clock is pulsed while CP_U is held High, the device will count down. The device can be cleared at any time by the asynchronous reset pin. It may also be loaded in parallel by activating the asynchronous parallel load pin.

Inside the device are four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, asynchronous preset, load, and synchronous count up and count down functions.

Each flip-flop contains JK feedback from slave to master, such that a Low-to-High transition on the CP_D input will decrease the count by one, while a similar transition on the CP U input will advance the count by one.

One clock should be held High while counting with the other, because the circuit will either count by twos or not at all, depending on the state of the first JK flip-flop, which cannot toggle as long as either clock input is Low. Applications requiring reversible operation must make the reversing decision while the activating clock is High to avoid erroneous counts.

The Terminal Count Up (TC_U) and Terminal Count Down (TC_D) outputs are normally High. When the circuit has reached the maximum count state of 15, the next High-to-Low transition of CP_U will cause TC_U to go Low. TC_U will stay Low until CP_U goes High again, duplicating the count up clock, although delayed by two gate delays. Likewise, the TC_D output will go Low when the circuit is in the zero state and the CP_D goes Low. The TC outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms.

Multistage counters will not be fully synchronous since there is a two-gate delay time difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel Data inputs (D0 - D3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs when the Parallel Load (PL) input is Low. A High level on the Master Reset (MR) input will disable the parallel load gates, override both clock inputs, and set all Q outputs Low. If one of the clock inputs is Low during and after a reset or load operation, the next Low-to-High transition of the clock will be interpreted as a legitimate signal and will be counted.

Features

• Synchronous reversible 4-bit counting
• Asynchronous parallel load capability
• Asynchronous reset (clear)
• Cascadable without external logic

Products/packages

All type numbers in the table below are discontinued. See the table Discontinued information for more information.

Quality/reliability/chemical content

All type numbers in the table below are discontinued. See the table Discontinued information for more information.

Quality and reliability disclaimer

Discontinued information

Block diagrams/pinning

Design support

Application Notes

AN216; Arbitration in shared resource systems (1988-07-18)

AN203; Test Fixtures for High Speed Logic (1998-04-02)

AN202; Testing and specifying FAST logic (1987-06-01)

AN2021; Thermal considerations for FAST logic products (1995-03-13)

Parametrics/similar products

Similar products
74F193 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer