74F711A; 74F711-1; 74F712A; 74F712-1

General description

The 74F711A/74F711-1 consist of five 2-to-1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F711A has a common select (S) input, an Output Enable (OE) input and an Output Inverting (INV) input to control the 3-State outputs. The outputs source 15mA and sink 64mA. The 74F711-1 is the same as the 74F711A except that is has a 30 W termination impedance on each output to reduce line noise and the 3-State outputs sink 5mA.

When the inverting input (INV) is Low, the input data path is inverted.

To improve speed and noise immunity, V_CC and GND side pins are used.

The 74F712A/74F712-1 consist of five 3-to1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F712A has two select (S0, S1) inputs to determine which set of five inputs will be propagated to the five outputs. The outputs source 15mA and sink 64mA. The 74F712-1 is the same as the 74F712A except that it has a 30

termination impedance on each output to reduce line noise and the outputs sink 5mA.

Features

74F711A/74F711-1

• Consists of five 2-to-1 Multiplexers
• High impedance PNP base inputs for reduced loading (20µA in High and Low states)
• Designed for address multiplexing of dynamic RAM and other applications
• Output inverting/non-inverting option
• 30 W termination impedance on each output ? 74F711-1
• Outputs sink 64mA (74F711A only)

74F712A/74F712-1

• Consists of five 3-to-1 Multiplexers
• High impedance PNP base inputs for reduced loading (20µA in High and Low states)
• Designed for address multiplexing of dynamic RAM and other applications
• 30 W termination impedance on each output ? 74F712-1
• Outputs sink 64mA (74F712A only)

Print / Email

• Print this information
• Email this information

Disclaimers

• General product disclaimer
• Quality and reliability disclaimer