74HC/HCT109

General description

The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD ) and reset (RD ) inputs; also complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input.

The J and K inputs control the state changes of the flip-flops as described in the mode select function table.

The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features

• J, K inputs for easy D-type flip-flop
• Toggle flip-flop or "do nothing" mode
• Output capability: standard
• I_CC category: flip-flops

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Technical documents

Support Documents

HCT_USER_GUIDE; HC/T User Guide (1997-11-01)

75013486; Philips Logic Competitive Cross Reference Guide (2004-09-14)

Parametrics/similar products

Similar products

74HC/HCT109 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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