74HC/HCT163

General description

The 74HC/HCT163 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT163 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).

The outputs (Q₀ to Q₃) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D₀ to D₃) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable inputs (CEP and CET).

For the '163' the clear function is synchronous.

A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q₀ to Q₃) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs.

This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q₀. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

f_max= (1) / (t_{P (max)} (CP to TC) + t_SU (CEP to CP) )

Features

• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Synchronous reset
• Output capability: standard
• I_CC category: MSI

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• Television sets
• Home-sound sets
• Multimedia systems
• All mains fed audio systems
• Car audio (boosters).

Block diagrams/pinning

Design support

Support Documents

HCT_USER_GUIDE; HC/T User Guide (1997-11-01)

Parametrics/similar products

Similar products
74HC/HCT163 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

Print / Email

• Print this information
• Email this information

Disclaimers

• General product disclaimer
• Quality and reliability disclaimer