74HC175;74HCT175

General description

The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs.

The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The state of each D inputone set-up time before the LOW-to-HIGH clock transitionis transferred to the corresponding output (Q_n ) of the flip-flop.

All Qn outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.

Features

• Four edge-triggered D flip-flops
• Output capability: standard
• I_CC category: MSI

Products/packages

Pricing/ordering/availability

Technical documents

Support Documents

HCT_USER_GUIDE; HC/T User Guide (1997-11-01)

Parametrics/similar products

Similar products

74HC175;74HCT175 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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