74LV165

General description

The 74LV165 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165.

The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q₇ and Q₇) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D₀ to D₇ inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the D S input and shifts one place to the right (Q₀»Q₁»Q₂etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q₇ output to the D S input of the succeeding stage.

The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.

Features

• Wide operating voltage: 1.0 to 5.5 V
• Optimized for low voltage applications: 1.0 to 3.6 V
• Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
• Typical V OLP (output ground bounce) < 0.8 V at V_CC = 3.3 VT amb = 25°C
• Typical V OHV (output V OH undershoot) > 2 V at V_CC = 3.3 VT amb = 25°C
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• I_CC category: MSI

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