74LVC163

General description

The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74LVC163 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pins CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by t_PHL (propagation delay CP to TC) and t_su (set-up time CEP to CP) according to the formula: f _max = 1/(t_PHL(max) + t_su)

Features

• Wide supply voltage range from 1.2 V to 3.6 V
• Complies with JEDEC standard JESD8-B/JESD36
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Synchronous reset
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock.
• ESD protection:
• HBM EIA/JESD22-A114-B exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN240; Interfacing 3 Volt and 5 Volt Applications (1995-09-15)

AN263; Power considerations when using CMOS and BiCMOS logic devices (2002-02-05)

Parametrics/similar products

Similar products
74LVC163 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

Print / Email

• Print this information
• Email this information

Disclaimers

• General product disclaimer
• Quality and reliability disclaimer