74LVC169

General description

The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74LVC169 is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output (pins Q0 to Q3) change coincident with each other when so instructed by the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the LOW-to-HIGH transition of the clock. The counter is fully programmable; that is, the outputs may be preset to any number between 0 and it's maximum count. Presetting is synchronous with the clock and takes place regardless of the levels of the count enable inputs. A LOW level on the parallel enable (pin PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the counter counts up, when LOW, it counts down. The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a LOW-level output pulse with a duration approximately equal to a HIGH level portion of pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded stages. The 74LVC169 use edge triggered J-K type flip-flops and have no constraints on changing the control of data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the next LOW-to-HIGH transition of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enter the flip-flops on the next LOW-to-HIGH transition of the clock. In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be HIGH. The pin U/D input determines the direction of the counting. The terminal count output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW, when a counter reaches 15 in the count up mode.The pin TC output state is not a function of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For this reason the use of pin TC as a clock signal is not recommended; see the following logic equations:

count enable = CEP x CET x PE
count up: TC = Q3 x Q2 x Q1 x Q0 x CET x (U/D)
count down: TC = Q3 x Q2 x Q1 x Q0 x CET x (U/D).

Features

• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard JESD8-B/JESD36
• Up/down counting
• Two count enable inputs for n-bit cascading
• Built-in look-ahead carry capability
• Presettable for programmable operation
• ESD protection:
• HBM EIA/JESD22-A114-B exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from -40 Cel to +85 Cel and from -40 Cel to +125 Cel.

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Technical documents

Application Notes

AN240; Interfacing 3 Volt and 5 Volt Applications (15-Sep-95)

AN263_2; Power considerations when using CMOS and BiCMOS logic devices (05-Feb-02)

Parametrics/similar products

Similar products

74LVC169 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

Print / Email

• Print this information
• Email this information

Disclaimer

The information published on product information pages of the www.nxp.com or www.semiconductors.com websites is an extract from product data sheets and is for information purposes only. For detailed information please check the most recent version of the relevant product data sheet as published on these websites. In the event of any conflict between product information pages and data sheets or deviations from information provided in the product data sheets on these product information pages, the information provided in the product data sheets shall prevail.

The product status of the product(s) described in the product data sheet may have changed since publication of the data sheet and therefore information in datasheets on product status may be outdated. The latest information on product status is published on the product information pages of the above-mentioned websites.

As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below.

http://www.philips.semiconductors.com use http://www.nxp.com

http://www.semiconductors.philips.com use http://www.nxp.com (Internet)

sales.addresses@www.semiconductors.philips.com use salesaddresses@nxp.com (e-mail)

The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version)
- © Koninklijke Philips Electronics N.V. (year). All rights reserved -
is replaced with:
- © NXP B.V. (year). All rights reserved.-

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding.