74LVCH32373A

General description

The 74LVCH32373A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families.

The inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

The 74LVCH32373A is a 32-bit transparent D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable input (nLE) and one output enable input (nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices.

The 74LVCH32373A consists of 4 sections of eight D-type transparent latches with 3-state true outputs. When input nLE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes.

When input nLE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of nLE. When input nOE is LOW, the contents of the eight latches are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.

The 74LVCH32373A bushold data input circuits eliminate the need for external pull-up resistors to hold unused inputs.

Features

• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-trough standard pin-out architecture
• Low inductance multiple power and ground pins for minimum noise and ground bounce
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• All data inputs have bushold
• Complies with JEDEC standard JESD8-B/JESD36
• ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from -40 Cel to +85 Cel
• Packaged in plastic fine-pitch ball grid array package.

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Block diagrams/pinning

Design support

Application Notes

AN240; Interfacing 3 Volt and 5 Volt Applications (1995-09-15)

AN263; Power considerations when using CMOS and BiCMOS logic devices (2002-02-05)

Parametrics/similar products

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer