GTL1655

General description

The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 Ohm) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.

The device is configured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes.

The GTL1655 can be used at GTL (V_TT = 1.2 V, V_REF = 0.8 V) or GTL+ (V_TT = 1.5 V, V_REF = 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with V_REF providing the reference voltage input.

The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins.

To optimize signal integrity, the GTL1655 features an adjustable edge rate control (V_ERC ). By adjusting V_ERC between GND and V_CC , a designer can adjust the Port B edge rate to suit an application?s load conditions.

The GTL1655 permits true live insertion capability by incorporating:

• BIAS V_CC , to pre-charge outputs and avoid disturbing active data during card insertion.
• I_off to disable current flow through powered-off I/Os.
• Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once V_CC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to V_CC via a pull-up resistor.

Features

• Combination of D-type latches and D-type flip-flops for transceiver operation in clocked, latched or transparent mode
• Logic level translation between LVTTL and GTL/GTL+ signals
• HIGH-drive LOW-output-impedance (100 mA/12 Ohm) on Port B
• Configurable rise and fall times on Port B
• Supports live insertion (I_off, Power-up 3-state, and BIAS V_CC)
• Bus Hold on Port A inputs
• Over voltage tolerance on Port A
• Minimized switching noise through use of distributed V_CC and GND pins
• Available in TSSOP64 package
• Industrial temperature range (-40 Cel to +85Cel)
• ESD protection
• HBM EIA/JESD22-A114-A exceeds 2000 V
• CDM EIA/JESD22-C101 exceeds 1000 V
• Latch-up EIA/JEDS78 exceeds 200 mA

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN10897; A guide to designing for ESD and EMC (2010-01-22)

AN10216; I2C manual (2003-03-27)

Support Documents

design_con_2003_tecforum_i2c_bus_overview; DesignCon 2003 TecForum I 2 C Bus Overview (2003-01-27)

39340011_jp; I2C-bus specification (latest version) (2004-06-22)

Parametrics/similar products

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GTL1655 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer