GTL2003

General description

The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin.

When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V_CC by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control.

All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other eight matched Sn/Dn transistors, allowing for easier board layout. The translator's transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices.

Features

• 8-bit bidirectional low voltage translator
• Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
• Provides bidirectional voltage translation with no direction pin
• Low 6.5 Ohm ON-state resistance (R_on) between input and output pins (Sn/Dn)
• Supports hot insertion
• No power supply required: will not latch up
• 5 V tolerant inputs
• Low standby current
• Flow-through pinout for ease of printed-circuit board trace routing
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Packages offered: TSSOP20, DHVQFN20

Products/packages

Pricing/ordering/availability

Applications

• Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V
• The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C-bus port translation to the normal 3.3 V and/or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.

Related applications
Motherboard components

Block diagrams/pinning

Technical documents

Application Notes

AN10216_1; I2C manual (27-Mar-03)

Support Documents

75014356; Cross Bar Switch Technology (CBT) Selection Guide (14-Mar-05)

design_con_2003_tecforum_i2c_bus_overview; DesignCon 2003 TecForum I 2 C Bus Overview (2003-01-27)

75011212; I2C 2002-1A Evaluation Board Kit (2003-03-01)

39340011_jp; I2C-bus specification (latest version) (2004-06-22)

Parametrics/similar products

Similar products

GTL2003 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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