LPC1768/66/65/64

General description

The LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1768/66/65/64 operate at CPU frequencies of up to 100 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1768/66/65/64 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I²C-bus interfaces, 2-input plus 2-output I²S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.

The LPC1768/66/65/64 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series.

Features

• ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 100 MHz operation with zero wait states.
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
• On-chip SRAM includes:
  • 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
  • Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet (LPC1768/66/64 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I²S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1768/66/64 only), and the USB interface. This interconnect provides communication with no arbitration delays.
• Split APB bus allows high throughput with few stalls between the CPU and DMA.
• Serial interfaces:
  • Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/66/64 only).
  • USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1764 includes a device controller only.
  • Four UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485 support. One UART has modem control I/O, and one UART has IrDA support.
  • CAN 2.0B controller with two channels.
  • SPI controller with synchronous, serial, full duplex communication and programmable data length.
  • Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
  • Two I²C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with multiple address recognition and monitor mode.
  • One I²C-bus interface supporting full I²C-bus specification and fast mode plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
  • On the LPC1768/66/65 only, I²S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I²S-bus interface can be used with the GPDMA. The I²S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
• Other peripherals:
  • 70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors and a new, configurable open-drain operating mode.
  • 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 1 MHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
  • 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support (LPC1768/66/65 only).
  • Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input and DMA support.
  • One motor control PWM with support for three-phase motor control.
  • Quadrature encoder interface that can monitor one external quadrature encoder.
  • One standard PWM/timer block with external count input.
  • RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 64 bytes of battery-powered backup registers.
  • Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of time if it enters an erroneous state.
  • System tick timer, including an external clock input option.
  • Repetitive interrupt timer provides programmable and repeating timed interrupts.
  • Each peripheral has its own clock divider for further power savings.
• Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.
• Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
• Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
• Single 3.3 V power supply (2.4 V to 3.6 V).
• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
• Non-maskable Interrupt (NMI) input.
• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.
• The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.
• Processor wake-up from Power-down mode via interrupts from various peripherals.
• Brownout detect with separate threshold for interrupt and forced reset.
• Power-On Reset (POR).
• Crystal oscillator with an operating range of 1 MHz to 25 MHz.
• 4 MHz internal RC oscillator trimmed to 1 pct accuracy that can optionally be used as a system clock.
• PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
• USB PLL for added flexibility.
• Code Read Protection (CRP) with different security levels.
• Available as 100-pin LQFP package (14 x 14 x 1.4 mm).

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• eMetering
• Lighting
• Industrial networking
• Alarm systems
• White goods
• Motor control

Block diagrams/pinning

Design support

Application Notes

AN10875; IEC 60601-1-8 audible alert generator using the LPC1700 (2009-10-09)

AN10859; LPC1700 Ethernet MII Management (MDIO) via software (2009-08-06)

AN10849; LPC1700 RTC hardware auto calibration (2009-07-21)

AN10866; LPC1700 secondary USB bootloader (2009-09-08)

AN10850; LPC1700 timer triggered memory to GPIO data transfer (2009-07-30)

AN10878; Migrating to the LPC1700 series (2009-10-06)

AN10845; Porting uIP1.0 to LPC1700 (2009-06-30)

AN10851; Using Code Read Protection in LPC1700 (2009-07-28)

Support Documents

75016676; 100 MHz, 32-bit Microcontrollers with Cortex-M3™ core, LPC1700 series (2009-02-01)

uip_webserver_src_lpc1700; AN10845 uIP webserver source code (2009-07-01)

rtc_calibration_project; AN10849 - LPC1700 RTC calibration source code and calculator (2009-07-17)

LPC1700_GPIO_Timer_DMA_example; AN10850 - LPC1700 GPIO DMA source code (2009-07-27)

CRP_Example; AN10851 - CRP example source code (2009-07-24)

EasyWEB; AN10859 - LPC1700 EasyWEB source code (2009-08-11)

LPC1700_secondary_USB_bootloader; AN10866 - LPC1700 secondary USB bootloader source code (2009-08-31)

75016739; Development Tools for ARM-based MCUs - June 2009 (2009-06-01)

ES_LPC1764; Errata sheet LPC1764 (2009-10-01)

ES_LPC1765; Errata sheet LPC1765 (2009-10-14)

ES_LPC1766; Errata sheet LPC1766 (2009-10-14)

75016725; Microcontroller Brochure - April 2009 (2009-04-04)

75016669; Microcontroller Line Card - April 2009 (2009-04-04)

web; Sample Code Bundle for LPC17xx Peripherals using Keil's MDK-ARM (2009-06-24)

web; USB Host Lite stack with MSC support for LPC17xx (2009-07-14)

Parametrics/similar products

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer