LPC2468

General description

NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory. This flash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from flash memory at the maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM microcontroller family of products. The LPC2468 can execute both 32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means engineers can choose to optimize their application for either performance or code size at the sub-routine level. When the core executes instructions in Thumb state it can reduce code size by more than 30 pct with only a small loss in performance while executing instructions in ARM state maximizes core performance.

The LPC2468 microcontroller is ideal for multipurpose communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I²C interfaces, and an I²S interface. Supporting this collection of serial communications interfaces are the following feature components; an on-chip 4 MHz internal precision oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for communication gateways and protocol converters. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2468 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts. All of these features make the LPC2468 particularly suitable for industrial control and medical systems.

Features

• ARM7TDMI-S processor, running at up to 72 MHz.
• 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
• 98 kB on-chip SRAM includes:
  • 64 kB of SRAM on the ARM local bus for high performance CPU access.
  • 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
  • 16 kB SRAM for general purpose DMA use also accessible by the USB.
  • 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
• Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
• EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM.
• Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
• General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I²S-bus, and SD/MMC interface as well as for memory-to-memory transfers.
• Serial Interfaces:
  • Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB.
  • USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and associated DMA controller.
  • Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
  • CAN controller with two channels.
  • SPI controller.
  • Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
  • Three I²C-bus interfaces (one with open-drain and two with standard port pins).
  • I²S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
• Other peripherals:
  • SD/MMC memory card interface.
  • 160 General purpose I/O pins with configurable pull-up/down resistors.
  • 10-bit ADC with input multiplexing among 8 pins.
  • 10-bit DAC.
  • Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
  • Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs.
  • RTC with separate power domain, clock source can be the RTC oscillator or the APB clock.
  • 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
  • WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
• Standard ARM test/debug interface for compatibility with existing tools.
• Emulation trace module supports real-time trace.
• Single 3.3 V power supply (3.0 V to 3.6 V).
• Three reduced power modes: idle, sleep, and power-down.
• Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources.
• Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).
• Two independent power domains allow fine tuning of power consumption based on needed features.
• Each peripheral has its own clock divider for further power saving. These dividers help reducing active power by 20 pct to 30 pct.
• Brownout detect with separate thresholds for interrupt and forced reset.
• On-chip power-on reset.
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
• 4 MHz internal RC oscillator trimmed to 1 pct accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.
• On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
• Boundary scan for simplified board testing.
• Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• Industrial control
• Medical systems
• Protocol converter
• Communications

Related applications
Intelligent washing machine
LCD TV - MMS functionality
Color mixing for RGBA LEDs

Block diagrams/pinning

Design support

Application Notes

AN10687; AN10687 - IEC 60601-1-8 audible alert generator using the LPC2000 (2008-02-12)

lpc24xx_usb_bootloader; AN10764 (LPC24xx USB bootloader) (2008-11-20)

AN10744; Ethernet secondary ISP bootloader (2008-09-05)

AN10689; Full-duplex software UART for LPC2000 (2008-01-18)

AN10835; LPC2000 secondary bootloader for code update using IAP (2009-05-26)

AN10878; Migrating to the LPC1700 series (2009-10-06)

AN10576; Migrating to the LPC2300/2400 family (2007-02-05)

AN10674; NXP LPC2000 CAN driver with FullCAN mode (2008-01-15)

AN10703; NXP USB host lite (2008-07-24)

AN10775; NicheLite for LPC implementation notes (2009-07-16)

AN10778; PCB layout guidelines for NXP MCUs in BGA packages (2009-01-22)

AN10799; Porting uIP1.0 to LPC23xx/24xx (2009-06-15)

AN10815; SWIM: NXP's basic graphics library for LPC products (2009-05-01)

AN10764; USB secondary ISP bootloader for LPC24xx (2008-11-24)

AN10256; Using IAP for LPC2000 ARM devices (2004-10-25)

AN10771; Using the LPC24xx EMC peripheral to drive SDRAM (2008-12-01)

AN10413; uC/OS-II Time Management in LPC2000 (2007-07-18)

Support Documents

75016574; 72-MHz, 32-bit microcontroller with ARM7TDMI-S™ core LPC24xx (2008-08-01)

EthernetBootloader; AN10744 Ethernet Bootloader (2008-09-08)

AN10771_SDRAM; AN10771 sample code (2008-11-26)

uip_webserver_src; AN10799 - uIP webserver source code (2009-06-16)

LPC2000_Series_Secondary_Bootloader; AN10835 - LPC2000 series secondary bootloader source code (2009-05-27)

75016543; An industry-leading portfolio of cost-effective, power-saving solutions for major home appliances (2008-06-01)

; Design example IEC alarm (2008-02-12)

75016739; Development Tools for ARM-based MCUs - June 2009 (2009-06-01)

ES_LPC2468; Errata sheet LPC2468 (2009-05-08)

web; LPC2000 EDA files (IBIS, BSDL, OrCAD, PADS, etc.) (2009-07-27)

UM10237; LPC24XX User manual (2009-08-26)

web; LPCZone Training Video - LPC23xx and LPC24xx Overview training (2008-01-07)

web; LPCZone Training Video - NTRU Encryption Overview training (2008-01-06)

75016725; Microcontroller Brochure - April 2009 (2009-04-04)

75016669; Microcontroller Line Card - April 2009 (2009-04-04)

nxp_company_profile; NXP company profile (2009-06-16)

web; NicheLite TCP/IP stack software for LPC23xx/24xx with IAR EWB or Keil MDK (2008-02-13)

web; Sample Code Bundle for LPC23xx/LPC24xx Peripherals using Keil's MDK-ARM (2009-03-10)

Parametrics/similar products

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer