LPC2917/19

General description

Architectural overview

The LPC2917/19 consists of:

• An ARM968E-S processor with real-time emulation support
• An AMBA Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers
• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem)
• Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems.
• One ARM Peripheral Bus for event router and system control.

The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place. Completion of a second write to the same subsystem will not be executed until the first write is finished.

ARM968E-S processor

The ARM968E-S is a general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core.

Amongst the most compelling features of the ARM968E-S are:

• Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces
• Write buffers for the AHB and TCM buses
• Enhanced 16 x 32 multiplier capable of single-cycle MAC operations and 16-bit fixedpoint
• DSP instructions to accelerate signal-processing algorithms and applications.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline architecture. Typically, in a three-stage pipeline architecture, while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory. In the five-stage pipeline additional stages are added for memory access and write-back cycles.

The ARM968E-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions or to applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM968E-S processor has two instruction sets:

• Standard 32-bit ARMv5TE set
• 16-bit Thumb set

The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit controller using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code.

Thumb code can provide up to 65 pct of the code size of ARM, and 160 pct of the performance of an equivalent ARM controller connected to a 16-bit memory system.

The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2.

On-chip flash memory system

The LPC2917/19 includes a 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished in several ways. It may be programmed in-system via a serial port (e.g., CAN).

On-chip static RAM

In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one of 32 kB and one of 16 kB. Both may be used for code and/or data storage.

Features

General

• ARM968E-S processor at 80 MHz maximum.
• AHB system bus at 80 MHz.
• On-chip memory:
  • Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data TCM (DTCM).
  • Two separate internal SRAM instances; 32 kB and 16 kB.
  • Up to 768 kB flash program memory.
• Two-channel CAN controller supporting Full-CAN and extensive message filtering.
• Two LIN master controllers with full hardware support for LIN communication.
• Two 550 UARTs with 16-byte TX and RX FIFO depths.
• Three full-duplex queued SPIs with four slave-select lines; 16 bits wide; 8 locations deep; TX FIFO and RX FIFO.
• Four 32-bit timers each containing four capture-and-compare registers linked to I/Os.
• Four 6-channel PWMs with capture and trap functionality.
• 32-bit watchdog with timer change protection, running on safe clock.
• Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus keeper.
• Vectored Interrupt Controller (VIC) with 16 priority levels.
• Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion times as low as 2.44 us per channel. Each channel provides a compare function to minimize interrupts.
• Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake-up features.
• External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus.
• Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
• Flexible Reset Generation Unit (RGU) able to control resets of individual modules.
• Flexible Clock Generation Unit (CGU) able to control clock frequency of individual modules:
  • On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring.
  • On-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz - maximum PLL input 15 MHz.
  • On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz.
  • Generation of up to 10 base clocks.
  • Seven fractional dividers.
• Highly configurable system Power Management Unit (PMU):
  • Clock control of individual modules.
  • Allows minimization of system operating power consumption in any configuration.
• Standard ARM test and debug interface with real-time in-circuit emulator.
• Boundary-scan test supported.
• Dual power supply:
  • CPU operating voltage: 1.8 V +- 5 pct.
  • I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
• 144-pin LQFP package.
• -40 Cel to 85 Cel ambient operating temperature range.

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN10689_1; Full-duplex software UART for LPC2000 (2008-01-18)

AN10795_2; LPC29xx Power-down mode explained (2009-02-25)

AN10809_1; LPC29xx flash features (2009-04-13)

Support Documents

LPC29xx_PD_APPNOTE_code; AN10795 power-down appnote code (2009-03-12)

LPC29xx_samplecode; AN10809 - LPC29xx flash software examples (2009-04-20)

75016543; An industry-leading portfolio of cost-effective, power-saving solutions for major home appliances (2008-06-01)

75016739; Development Tools for ARM-based MCUs - June 2009 (2009-06-01)

web; LPCZone Training Video - LPC29xx Base Module (2009-01-01)

web; LPCZone Training Video - NTRU Encryption Overview training (2008-01-06)

75016725; Microcontroller Brochure - April 2009 (2009-04-04)

75016669; Microcontroller Line Card - April 2009 (2009-04-04)

75016101; NXP 80-MHz, 32-bit ARM968 microcontroller LPC291x with CAN and LIN (2007-08-01)

Parametrics/similar products

Similar products
LPC2917/19 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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