Datasheet
LPC2921/2923/2925
(Preliminary Specification)
15-Jun-09, 83 pages, 374 kB
General description
The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM
blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller,
CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and
multiple serial and parallel interfaces in a single chip targeted at consumer, industrial,
medical, and communication markets. To optimize system power consumption, the
LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU) that provides
dynamic clock gating and scaling.
Features
- ARM968E-S processor running at frequencies of up to 125 MHz maximum.
- Multilayer AHB system bus at 125 MHz with four separate layers.
- On-chip memory:
- Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data
TCM (DTCM).
- On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each.
- On the LPC2923 and LPC2921, one 16 kB SRAM block.
- 8 kB ETB SRAM, also usable for code execution and data.
- Up to 512 kB high-speed flash-program memory.
- 16 kB true EEPROM, byte-erasable/programmable.
- Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
- Serial interfaces:
- USB 2.0 full-speed device controller with dedicated DMA controller and on-chip
device PHY.
- Two-channel CAN controller supporting FullCAN and extensive message filtering.
- Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
- Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and
RS-485/EIA-485 (9-bit) support.
- Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
- Two I2C-bus interfaces.
- Other peripherals:
- Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8
analog inputs each with conversion times as low as 2.44 us per channel. Each
channel provides a compare function to minimize interrupts.
- Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external
signal input.
- Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
- Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
- Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
- Quadrature encoder interface that can monitor one external quadrature encoder.
- 32-bit watchdog with timer change protection, running on safe clock.
- Up to 60 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
- Vectored Interrupt Controller (VIC) with 16 priority levels.
- Up to 16 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up
features.
- Configurable clock out pin for driving external system clocks.
- Processor wake-up from power-down via external interrupt pins and CAN or LIN
activity.
- Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
- Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules:
- On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
- On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz. PLL input range 10 MHz to 25 MHz.
- On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
- Generation of up to 11 base clocks.
- Seven fractional dividers.
- Second, dedicated CGU with its own PLL generates the USB clock and a configurable
clock output.
- Highly configurable system Power Management Unit (PMU):
- clock control of individual modules.
- allows minimization of system operating power consumption in any configuration.
- Standard ARM test and debug interface with real-time in-circuit emulator.
- Boundary-scan test supported.
- ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
- Dual power supply:
- CPU operating voltage: 1.8 V +- 5 pct.
- I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
- 100-pin LQFP package.
- -40 Cel to +85 Cel ambient operating temperature range.
Products/packages
| LPC2921FBD100 | LPC2921FBD100,551 | 9352 871 14551 | Volume production | SOT407-1
(LQFP100)
| Tray Dry Pack, Bakeable, Single | Standard Marking | |
| LPC2923FBD100 | LPC2923FBD100,551 | 9352 871 15551 | Volume production | SOT407-1
(LQFP100)
| Tray Dry Pack, Bakeable, Single | Standard Marking | |
| LPC2925FBD100 | LPC2925FBD100,551 | 9352 871 16551 | Volume production | SOT407-1
(LQFP100)
| Tray Dry Pack, Bakeable, Single | Standard Marking | |
Pricing/ordering/availability
Block diagrams/pinning

Design support
Application Notes
Support Documents
Parametrics/similar products
| Type number | Package | Power supply | RAM(bytes) | SPECIAL FEATURES | ADCs | I/O pins | Operating temp.(Cel) | Timers | PWMs | Memory Type | Serial Interfaces | No. of Pins | Operating Frequency(MHz) |
| LPC2921FBD100 | SOT407-1
(LQFP100) | 1.8V / 3.3V | 24KB | QEI, GPDMA, 16KB EEPROM, 16KB ITCM/DTCM | 16-ch 10-bit | 76 | -40 to +85 | 6x32-bit + WDT | 24-ch PWM | 128KB Flash | USB 2.0 FS Device, 2xCAN,2xLIN/UART, 2xUART,3xQSPI, 2xI2C | 100 | 0~125 |
| LPC2923FBD100 | SOT407-1
(LQFP100) | 1.8V / 3.3V | 24KB | QEI, GPDMA, 16KB EEPROM, 16KB ITCM/DTCM | 16-ch 10-bit | 76 | -40 to +85 | 6x32-bit + WDT | 24-ch PWM | 256KB Flash | USB 2.0 FS Device, 2xCAN,2xLIN/UART, 2xUART,3xQSPI, 2xI2C | 100 | 0~125 |
| LPC2925FBD100 | SOT407-1
(LQFP100) | 1.8V / 3.3V | 40KB | QEI, GPDMA, 16KB EEPROM, 16KB ITCM/DTCM | 16-ch 10-bit | 76 | -40 to +85 | 6x32-bit + WDT | 24-ch PWM | 512KB Flash | USB 2.0 FS Device, 2xCAN,2xLIN/UART, 2xUART,3xQSPI, 2xI2C | 100 | 0~125 |