P5Cx012/02x/40/73/80/144 family

General description

SmartMX family approach

The new CMOS14 SmartMX family members feature a modular set of devices with:

• 12 KB to 144 KB EEPROM
• 200 KB user ROM
• 6144 B RAM
• High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC)
• Secured dual/triple-DES coprocessor
• Secured AES coprocessor
• Memory Management Unit (MMU)
• ISO/IEC 7816 contact interface
• Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)
• Optional S²C interface for NFC communication link
• 5-metal-layer 0.14 um CMOS technology
• EEPROM with typical 500000 cycles endurance and minimum 20 years retention time
• Broad spectrum of delivery types
• Optional certified crypto library modules for RSA, ECC, DES, AES, SHA and PRNG

SmartMX family properties

The long-term approved SmartMX family features a significantly enhanced secure smart card IC architecture. Extended instructions for Java and C code, linear addressing, high speed at low power and a universal memory management unit are among many other improvements added to the classic 80C51 core architecture. The technology transfer step from 5-metal-layer 0.18 um to 5-metal-layer 0.14 um CMOS technology offers now even more advantages in terms of security features, memory resources, crypto coprocessor calculation speed for RSA and ECC as well as availability of secure hardware support for 2/3-key Digital Encryption Standard (DES) and Advanced Encryption Standard (AES) operations.

The availability of contact interface, optional contactless or S²C interface enables the easy implementation of native or open platform and multi-application operating systems in market segments like e.g. banking, E-passport, ID card, Health Card, secure access, Java card, Near Field Communication (NFC) connectable mobile hand sets as well as Trusted Platform Modules (TPM).

Naming conventions

Cryptographic hardware coprocessors

FameXE coprocessor

The approved and modular FameXE architecture supports the trend of increasing RSA keys with faster execution speeds as well as Elliptic Curve Cryptography (ECC) based on GF(p) or GF(2ⁿ) at best performance. FameXE supports RSA with an operand length of up to 8-kbit (up to 4-kbit with intermediate storage in RAM only).

The FameXE PKI coprocessor supports 192-bit ECC key length that offers the same level of security as 2048-bit RSA. An ECC GF(2ⁿ) based signature, using a 163-bit key can be executed in less than 30 ms providing a security level comparable to 1024-bit RSA. The operand size for ECC, supported by FameXE, is only limited by the 2.5 KB size of the FXRAM. FameXE is easy to use and the flexible interface provides programmers with the freedom to implement their own cryptology solutions. A secured and CC EAL5+ certified crypto library providing a large range of required functions will be available for all devices in order to support customers in implementing public key-based solutions.

Triple-DES coprocessor

The DES for widely used symmetric encryption is supported by a dedicated, high performance, highly attack resistant hardware coprocessor. Single DES and triple-DES, based on two or three DES keys, can be executed within less than 40 us. Relevant standards (ISO/IEC, ANSI, FIPS) and Message Authentication Code (MAC) are fully supported. A secured crypto library element for DES is available.

AES coprocessor

SmartMX is the first smart card microcontroller platform to provide a dedicated high performance 128-bit parallel processing coprocessor to support secure AES. The implementation is based on FIPS197 as standardized by the National Institute for Standards and Technology (NIST), and supports key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to DES. AES is the next generation for symmetric data encryption and recommended successor of DES providing significantly improved security level. A secured crypto library element for AES is available.

SmartMX interfaces

SmartMX contact interface

Operating in accordance with ISO/IEC 7816, the SmartMX contact interface is supported by a built-in Universal Asynchronous Receiver/Transmitter (UART), which enables data rates of up to 1 Mbit/s allowing for the automatic generation of all typical baud rates and supports transmission protocols T = 0 and T = 1. Either one or two additional IOs are available.

SmartMX contactless interface

The optional contactless interface is fully compatible with ISO/IEC 14443 A as well as NXP Semiconductors field proven MIFARE technology. A dedicated Contactless Interface Unit (CIU) manages and supports communication using data rates of up to 848 kbit/s. A true anti-collision method (according to ISO/IEC 14443-3) enables multiple cards to be handled simultaneously.

The optional MIFARE functionality provided in configurations B1 (MIFARE 1 KB emulation) and B4 (MIFARE 4 KB emulation) safeguard the interface compatibility with any installed MIFARE infrastructure. The ability to run the MIFARE protocol concurrently with other contactless transmission protocols implemented by the user OS (T = CL or self defined) enables the combination of new services and existing applications based on MIFARE (e.g. ticketing) on a single dual interface controller based smart card.

A tutorial software library for ISO/IEC 14443-3 and ISO/IEC 14443-4 is available to support NXP Semiconductors customers for easy integration of the contactless technology into current system solutions.

SmartMX S²C interface

The S²C interface is intended for use with NXP Semiconductors NFC circuits (e.g. PN511, PN531) in order to configure a secure NFC system, e.g. in mobile hand sets.

Operated both in Contact mode (ISO/IEC 7816) and in S²C mode the user defines the final function of the controller chip with its operating system. This allows the same level of security, functionality and flexibility for the contact interface as well as for S²C interface.

The S²C interface is connected to the internal ISO 14443 CIU. The CIU handles the demodulation and the modulation of the S²C signals in a way that a full contactless communication via this interface and the NFC IC can be enabled. As the S²C interface is connected to the CIU the power of the P5CN080/P5CN144 has to be supplied via the VDD and VSS pads to use the S²C interface. The S²C interface does not need any software adaptation compared to the normal contactless operation.

Connected to the S²C interface of a NFC IC the device is compatible with existing MIFARE reader infrastructure and the optional emulation modes of MIFARE 1 KB or MIFARE 4 KB enable fast system integration and backward compatibility to MIFARE based cards. The communication on the S²C interface supports both the ISO/IEC 14443 A part 3 and the ISO/IEC 14443 part 4.

Security features

SmartMX incorporates a big range of both inherent and OS controlled security features as counter measure against all types of attacks. NXP Semiconductors has used the deep knowledge of chip security, combined with the used handshaking circuit technology, the very dense 5-metal-layer 0.14 um technology, glue logic and active shielding methodology for optimum results in CC EAL5+, EMVCo and other third party certifications and approvals.

SmartMX Memory Management Unit (MMU), designed to define various memory segments and assign security attributes accordingly, supports a strong firewall concept that keeps different applications separate from each other. Only the System mode has full access privileges to all memory space and on-chip peripherals, while the User mode only has privileges defined upon card personalization and executed under the control of the System mode.

Security evaluation and certificates

The reached target of the certification is CC EAL5+. Also third party approvals like e.g. EMVCo (Visa, CAST), ZKA and others, depending on the application requirements, are available.

NXP Semiconductors continues to drive forward third party security evaluations to provide its customers with the relevant information and documentation needed to execute subsequent composite evaluations of implemented applications.

Optional crypto library

NXP Semiconductors will offer for all family types an optional crypto library:

• Various algorithms
  • AES encryption and decryption using the AES coprocessor
  • DES and Triple-DES encryption and decryption using the DES coprocessor
  • RSA encryption and decryption, signature generation and verification for straightforward and CRT keys up to 5024 bits
  • RSA key generation
  • ECC over GF(p) signature generation and verification (ECDSA) and Diffie-Hellman key exchange for keys up to 544 bits
  • ECC over GF(p) key generation
  • ECC over GF(2ⁿ) signature generation and verification (ECDSA) and Diffie-Hellman key exchange for keys up to 571 bits
  • ECC over GF(2ⁿ) key generation
  • SHA-1, SHA-224 and SHA-256 hash algorithm
  • Pseudo-Random Number Generator (PRNG)
• Easy to use API for all algorithms
• Secure operation in contact as well as in the contactless mode
• Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks (DFA)
• Common criteria CC EAL5+ certification planned [except ECC over GF(2ⁿ)] according to BSI-PP-0002 protection profile

Features

Standard family features

• EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB
  • Data retention time: 20 years minimum
  • Endurance: 500000 cycles typical
• ROM: 200 KB
• RAM: 6144 B
  • 256 B IRAM + 3.25 KB standard RAM usable for CPU
  • 2560 B FXRAM usable for FameXE
• Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)
  • 5-metal-layer 0.14 um CMOS technology
  • Operating in Contact and Contactless mode (dependent on family type option)
  • Featuring a 24-bit universal memory space, 24-bit program counter
  • Combined universal program and data linear address range up to 16 MB
  • Additional instructions to improve:
    • Pointer operations
    • Performance
    • Code density of both C and Java source code
• ISO/IEC 7816 contact interface
• PKI coprocessor FameXE
• Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
  • 8192 bits maximum key length for RSA with randomly chosen modulus
  • 4096 bits maximum key length for calculation within RAM
  • 32-bit interface
  • Boolean operations for acceleration of standard, symmetric cipher algorithms
• High speed Triple-DES coprocessor (64-bit parallel processing DES engine)
  • Two or three keys loadable
  • DES3 performance < 40 us
• High speed AES coprocessor (128-bit parallel processing AES engine)
• Memory Management Unit (MMU)
• Low power and low voltage design using NXP Semiconductors handshaking technology
• Multiple source vectorized interrupt system with four priority levels
• Watch exception provides software debugging facility
• Multiple source RESET system
• Two 16-bit timers
• High reliable EEPROM for both data storage and program execution
• Bytewise EEPROM programming and read access
• Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at a time
• Typical EEPROM page erasing time: 1.7 ms
• Typical EEPROM page programming time: 1.0 ms
  • Power-saving Idle mode
  • Wake-up from Idle mode by RESET or any activated interrupt
  • Power-saving Sleep (power-down) mode or Clockstop mode
  • Wake-up from Sleep or Clockstop mode by RESET or external interrupt
• Contact configuration and serial interface according to ISO/IEC 7816: GND, VDD, CLK, RST_N, IO1
• ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high speed personalization up to 1 Mbit/s
• External or internally generated configurable CPU clock
• 1 MHz to 10 MHz operating external clock frequency range
  • Internal CPU clock up to 30 MHz with synchronous operation
  • Internal clocking independent of externally applied frequency
• High speed 16-bit CRC engine according to ITU-T polynomial definition
• Low power Random Number Generator (RNG) in hardware, AIS-31 compliant
• 1.62 V to 5.5 V extended operating voltage range for class C, B and A
• Optional extended Class B operation mode (targeted for battery supplied applications)
• -25 Cel to +85 Cel ambient temperature
• Broad spectrum of delivery types:
  • Wafers
  • Modules

Product specific family features

• P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144
  • ISO/IEC 7816 contact interface
  • Two additional IO ports IO2 and IO3 for full-duplex serial data communication
• P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144
  • CIU fully compatible with ISO/IEC 14443 A:
    • Fully supports the T = CL protocol according ISO/IEC 14443-4
    • Data transfer rates supported: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s
  • MIFARE contactless interface according ISO/IEC 14443-2:
    • 13.56 MHz operating frequency
    • Reliable communication due to 100 pct ASK
    • High speed efficient frame support
    • True anticollision
  • MIFARE reader infrastructure compatibility
  • Optional MIFARE 1 KB and MIFARE 4 KB emulation
  • Two additional IO ports IO2 and IO3 for full-duplex serial data communication
• P5CN080 and P5CN144
  • S²C interface
  • One additional IO port IO2 for full-duplex serial data communication

Security features

• Enhanced security sensors:
  • Low and high clock frequency sensor
  • Low and high temperature sensor
  • Low and high supply voltage sensor
  • Single Fault Injection (SFI) attack detection
  • Light sensors (included integrated memory light sensor functionality)
• Electronic fuses for safeguarded mode control
• Active shielding
• Unique ID for each die
• Clock input filter for protection against spikes
• Power-up and power-down reset
• Optional programmable card disable feature
• Memory security (encryption and physical measures) for RAM, EEPROM and ROM
• Memory Management Unit (MMU) including memory protection:
  • Secure multi application operating systems via two different operation modes: System mode and User mode
  • OS controlled access restriction mechanism to peripherals in User mode
  • Memory mapping up to 8-MB code memory
  • Memory mapping up to 8-MB (64-kbit) data memory
• Optional disabling of ROM read instructions by code executed in EEPROM
• Optional disabling of any code execution out of RAM
• EEPROM programming:
  • No external clock
  • Hardware sequencer controlled
  • On-chip high voltage generation
  • Enhanced error correction mechanism
• 64-B or 128-B EEPROM for customer-defined Security FabKey. Featuring batch, wafer or die-individual security data, included encrypted diversification features on request
• 14 B user write protected security area in EEPROM (byte access, inhibit functionality per byte)
• 32 B write once security area in EEPROM (bit access)
• 32 B user read only area in EEPROM (byte access)
• Customer specific EEPROM initialization available

Design-in support

• Approved development tool chain:
  • Keil PK51 development tool package inclusive uVision3/dScope C51 simulator, additional specific hardware drivers inclusive simulation of contactless interface and ISO/IEC 7816 card interface board. A SmartMX DBox allows software debugging and integration tests.
  • Ashling Ultra-Emulator platform, stand alone ROM prototyping boards and ISO/IEC 7816 and ISO/IEC 14443 card interface board. Code coverage and performance measurement software tools for real time software testing.
  • Dual interface dummy modules OM6711 (PDM 1.1 - SOT658) with special antenna bonding on C4 and C8 for testing the implanting process and antenna connection.
• Software libraries:
  • Libraries supporting contactless communication according to ISO 14443, part 3 and 4
  • EEPROM read/write routines

Products/packages

Pricing/ordering/availability

Applications

• Banking
• Java cards
• E-passports
• ID cards
• Secure access
• Trusted platform modules

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