PCA9512A

General description

The PCA9512A is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A provides bidirectional buffering, keeping the backplane and card capacitances isolated.

The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins.

During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.

The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or P82B96 Sx/y side.

Features

• Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
• Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
• Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ΔV/Δt rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (V_CC or V_CC2) to be the same
• 5 V to 3.3 V level translation with optimum noise margin
• High-impedance SDAn and SCLn pins for V_CC or V_CC2 = 0 V
• 1 V precharge on all SDAn and SCLn pins
• Supports clock stretching and multiple master arbitration and synchronization
• Operating power supply voltage range: 2.7 V to 5.5 V
• 0 Hz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SO8, TSSOP8 (MSOP8)

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system

Block diagrams/pinning

Design support

Support Documents

75016532; NXP 2-channel I²C-bus repeaters PCA9515x and 5-channel I²C-bus hubs PCA9516x (2008-07-01)

75016530; NXP level-shifting and hot-swappable I²C/SMBus buffers PCA951xA (2008-07-01)

Parametrics/similar products

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer