PCA9513A; PCA9514A

General description

The PCA9513A and PCA9514A are hot swappable I²C-bus and SMBus buffers that allow I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9513A and PCA9514A provides bidirectional buffering, keeping the backplane and card capacitances isolated.

Rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9513A and PCA9514A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).

The PCA9513A supplies a 92 uA current source to SCLIN and SDAIN pins in lieu of using pull-up resistors which is ideal for multidrop bus applications. Including the current source in the device provides for a consistent RC time constant as cards are removed and inserted into the backplane. The current source is high-impedance whenever the pin voltage is greater than the part V_CC.

The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V to provide better noise margin over the PCA9511A which is set to 0.6 V.

Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.

Features

• Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
• Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
• Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.8 V threshold) requires the bus pull-up voltage and supply voltage (V_CC) to be the same
• Rise time accelerator threshold moved from 0.6 V to 0.8 V for improved noise margin
• Active HIGH ENABLE input
• Active HIGH READY open-drain output
• High-impedance SDAn and SCLn pins for V_CC = 0 V
• 92 uA current source on SCLIN and SDAIN for PICMG backplane applications (PCA9513A only)
• Supports clock stretching and multiple master arbitration and synchronization
• Operating power supply voltage range: 2.7 V to 5.5 V
• 0 Hz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SO8, TSSOP8 (MSOP8)

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system

Block diagrams/pinning

Design support

Support Documents

75016532; NXP 2-channel I²C-bus repeaters PCA9515x and 5-channel I²C-bus hubs PCA9516x (2008-07-01)

75016530; NXP level-shifting and hot-swappable I²C/SMBus buffers PCA951xA (2008-07-01)

Parametrics/similar products

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer