PCA9515A

General description

The PCA9515A is a CMOS integrated circuit intended for application in I²C-bus and SMBus systems.

While retaining all the operating modes and features of the I²C-bus system, it permits extension of the I²C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.

The I²C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required.

Two or more PCA9515As cannot be put in series. The PCA9515A design does not allow this configuration. Since there is no direction pin, slightly different 'legal' low voltage levels are used to avoid lock-up conditions between the input and the output. A 'regular LOW' applied at the input of a PCA9515A will be propagated as a 'buffered LOW' with a slightly higher value. When this 'buffered LOW' is applied to another PCA9515A, PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A will not recognize it as a 'regular LOW' and will not propagate it as a 'buffered LOW' again. The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with themselves since they use shifting instead of static offsets to avoid lock-up conditions.

The output pull-down of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven LOW. This prevents a lock-up condition from occurring.

Features

• 2-channel, bidirectional buffer
• I²C-bus and SMBus compatible
• Active HIGH repeater enable input
• Open-drain input/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple masters
• Powered-off high-impedance I²C-bus pins
• Operating supply voltage range of 2.3 V to 3.6 V
• 5.5 V tolerant I²C-bus and enable pins
• 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater)
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SO8 and TSSOP8 (MSOP8)

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

Related applications
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Block diagrams/pinning

Design support

Application Notes

AN255; I2C / SMBus Repeaters, Hubs and Expanders (2002-12-19)

AN10441; Level shifting techniques in I2C-bus design (2007-06-20)

AN262; PCA954X FAMILY OF I²C / SMBus MULTIPLEXERS and SWITCHES (2004-10-01)

Support Documents

UM10206; I2C Demonstration Board 2005-1 Quick Start Guide (2006-06-13)

UM10204; I2C-bus specification and user manual (2007-06-26)

web; IBIS and HSPICE Model ()

75016532; NXP 2-channel I²C-bus repeaters PCA9515x and 5-channel I²C-bus hubs PCA9516x (2008-07-01)

75016531; NXP I2C 2002-1A evaluation board kits OM6285 and OM6278 (2008-07-01)

75016530; NXP level-shifting and hot-swappable I²C/SMBus buffers PCA951xA (2008-07-01)

UM10323; PCA9600 demonstration board OM6293 (2008-12-15)

Parametrics/similar products

Similar products
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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer