PCA9519

General description

The PCA9519 is a 4-channel level translating I²C-bus/SMBus repeater that enables the processor low voltage 2-wire serial bus to interface with standard I²C-bus or SMBus I/O. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I²C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are over-voltage tolerant and are high-impedance when the PCA9519 is unpowered.

The port B drivers are compliant with SMBus I/O levels, while port A uses a current sensing mechanism to detect the input or output LOW signal which prevents bus lock-up. The port A uses a 1 mA current source for pull-up and a 200 Ohm pull-down driver. This results in a LOW on port A accommodating smaller voltage swings. The output pull-down on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I²C-bus voltage level which enables port B to connect to any other I²C-bus device or buffer.

The PCA9519 drivers are not enabled unless V_CC(A) is above 0.8 V and V_CC(B) is above 2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the EN pin when the bus is idle.

Features

• 4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
• Voltage level translation from port A (1 V to V_CC(B) - 1.5 V) to port B (3.0 V to 5.5 V)
• Requires no external pull-up resistors on lower voltage port A
• Active HIGH repeater enable input
• Open-drain inputs/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple masters
• Powered-off high-impedance I²C-bus pins
• Operating supply voltage range of 1.0 V to V_CC(B) - 1.5 V on port A, 3.0 V to 5.5 V on port B
• 5 V tolerant B-side SCL and SDA and enable pins
• 50 ns glitch filter on B-side input
• 0 Hz to 400 kHz clock frequency
  Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: TSSOP20, HVQFN24

Products/packages

Pricing/ordering/availability

Applications

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Block diagrams/pinning

Technical documents

Application Notes

AN10441_1; Level shifting techniques in I²C-bus design (20-Jun-07)

AN255_2; I2C / SMBus Repeaters, Hubs and Expanders (19-Dec-02)

Support Documents

75015669; Continuous innovation. Timeless lifespan. (01-Sep-06)

75011212; I2C 2002-1A Evaluation Board Kit (01-Mar-03)

UM10206_1; I2C Demonstration Board 2005-1 Quick Start Guide (13-Jun-06)

UM10204_3; I2C-bus specification and user manual (26-Jun-07)

Parametrics/similar products

Similar products

PCA9519 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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