PCA9555

General description

The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I²C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I²C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.

The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I²C-bus address compatible with the PCF8575, software changes are required due to the enhancements, and are discussed in Application Note AN469.

The PCA9555 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I²C-bus address and allow up to eight devices to share the same I²C-bus/SMBus. The fixed I²C-bus address of the PCA9555 is the same as the PCA9554, allowing up to eight of these devices in any combination to share the same I²C-bus/SMBus.

Features

• Operating power supply voltage range of 2.3 V to 5.5 V
• 5 V tolerant I/Os
• Polarity Inversion register
• Active LOW interrupt output
• Low standby current
• Noise filter on SCL/SDA inputs
• No glitch on power-up
• Internal power-on reset
• 16 I/O pins which default to 16 inputs
• 0 Hz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN10146_02; I2C 2002-1A Evaluation Board (2003-02-26)

AN469_2; I2C/SMBus general purpose I/O expanders (2005-01-20)

AN10315_1; LED dimmer demoboard (2005-01-11)

Support Documents

75016543; An industry-leading portfolio of cost-effective, power-saving solutions for major home appliances (2008-06-01)

design_con_2003_tecforum_i2c_bus_overview; DesignCon 2003 TecForum I 2 C Bus Overview (2003-01-27)

i2c_overview_2h_2003; I2C Overview 2H 2003 ()

39340011_21; I2C-bus specification (version 2.1) (2000-01-01)

75016535; NXP 4/8/16-bit I²C/SMBus GPIO expanders PCA9536/54/54A/55 (2008-08-01)

75016020; NXP 8/16-bit I2C/SMBus GPIO expanders PCA9534/35/35C for low-power applications (2007-06-01)

75016531; NXP I2C 2002-1A evaluation board kits OM6285 and OM6278 (2008-07-01)

75015692; NXP LED dimmer demonstration board OM6279 (2006-11-01)

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer